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Mon, 5 Aug 2024 04:54:31 -0400 (EDT) From: Takashi Sakamoto To: linux1394-devel@lists.sourceforge.net Cc: linux-kernel@vger.kernel.org Subject: [PATCH v2 15/17] firewire: ohci: use guard macro to maintain bus time Date: Mon, 5 Aug 2024 17:54:06 +0900 Message-ID: <20240805085408.251763-16-o-takashi@sakamocchi.jp> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240805085408.251763-1-o-takashi@sakamocchi.jp> References: <20240805085408.251763-1-o-takashi@sakamocchi.jp> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The 1394 OHCI driver maintains bus time to respond to querying request. The concurrent access to the bus time is protected by spinlock. This commit uses guard macro to maintain the spinlock. Signed-off-by: Takashi Sakamoto --- drivers/firewire/ohci.c | 30 ++++++++++++------------------ 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/drivers/firewire/ohci.c b/drivers/firewire/ohci.c index 1461e008d265..5cb7c7603c2c 100644 --- a/drivers/firewire/ohci.c +++ b/drivers/firewire/ohci.c @@ -2300,9 +2300,8 @@ static irqreturn_t irq_handler(int irq, void *data) handle_dead_contexts(ohci); =20 if (event & OHCI1394_cycle64Seconds) { - spin_lock(&ohci->lock); + guard(spinlock)(&ohci->lock); update_bus_time(ohci); - spin_unlock(&ohci->lock); } else flush_writes(ohci); =20 @@ -2762,7 +2761,6 @@ static int ohci_enable_phys_dma(struct fw_card *card, static u32 ohci_read_csr(struct fw_card *card, int csr_offset) { struct fw_ohci *ohci =3D fw_ohci(card); - unsigned long flags; u32 value; =20 switch (csr_offset) { @@ -2786,16 +2784,14 @@ static u32 ohci_read_csr(struct fw_card *card, int = csr_offset) return get_cycle_time(ohci); =20 case CSR_BUS_TIME: - /* - * We might be called just after the cycle timer has wrapped - * around but just before the cycle64Seconds handler, so we - * better check here, too, if the bus time needs to be updated. - */ - spin_lock_irqsave(&ohci->lock, flags); - value =3D update_bus_time(ohci); - spin_unlock_irqrestore(&ohci->lock, flags); - return value; + { + // We might be called just after the cycle timer has wrapped around but = just before + // the cycle64Seconds handler, so we better check here, too, if the bus = time needs + // to be updated. =20 + guard(spinlock_irqsave)(&ohci->lock); + return update_bus_time(ohci); + } case CSR_BUSY_TIMEOUT: value =3D reg_read(ohci, OHCI1394_ATRetries); return (value >> 4) & 0x0ffff00f; @@ -2813,7 +2809,6 @@ static u32 ohci_read_csr(struct fw_card *card, int cs= r_offset) static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value) { struct fw_ohci *ohci =3D fw_ohci(card); - unsigned long flags; =20 switch (csr_offset) { case CSR_STATE_CLEAR: @@ -2849,12 +2844,11 @@ static void ohci_write_csr(struct fw_card *card, in= t csr_offset, u32 value) break; =20 case CSR_BUS_TIME: - spin_lock_irqsave(&ohci->lock, flags); - ohci->bus_time =3D (update_bus_time(ohci) & 0x40) | - (value & ~0x7f); - spin_unlock_irqrestore(&ohci->lock, flags); + { + guard(spinlock_irqsave)(&ohci->lock); + ohci->bus_time =3D (update_bus_time(ohci) & 0x40) | (value & ~0x7f); break; - + } case CSR_BUSY_TIMEOUT: value =3D (value & 0xf) | ((value & 0xf) << 4) | ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4); --=20 2.43.0