From nobody Sun Feb 8 01:52:30 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96F8C1A83A1 for ; Fri, 2 Aug 2024 16:15:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722615344; cv=none; b=LA0WL0R5LVGvFmfv+0JCvCAf5nzr3ZRWPiWC8qSS8B0feGp1L2Axg79vVxfxjT7kkf5ap0GfjccrX5GmUYfDzZ3DWLFx9/AET1sO2tPXhjCI39st5Zj7cjlg2zIuNfcbTI+2C5xtehyBCLApDjhvb2OZXzUaElE30aV6RCnFWI0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722615344; c=relaxed/simple; bh=ilZMM4NaYv40DK38mq7juuAum7aGWknaTsRlWEpVbBU=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=FBdIBOhCMHIwb1I5HBtVqA80eyEY5J2hYZTCBs40p6vcQabt7OrFKaZ7FKG/JDCv2q/50RJQhnhj5Q3nSqurXb4aBRdRODTrSnzYQj9Aqi8AulK7WWT16TeQUIF+h44Lchz0+j0AOGedTx8jERVgvCg2OGG/cuaMHWg9Tkrop3o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ZqIzkm9Z; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=gr+ayd6O; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ZqIzkm9Z"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="gr+ayd6O" Message-ID: <20240802155440.275200843@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1722615335; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=VI6ArGD5nH+JTATcGxIw1bvZF42wAjPrLzfbKGCDYP0=; b=ZqIzkm9Zi4c5Sph+AzKrZg02TE9Nk8RvXiqlEHnlHORL2aaQc93kuEBSxCqASHAWoKgdsg z20HpXMxwhtWug4+OsWM08wQC4jPwr2DLxi6nIzkHM52ie8slOhVJ0zJIalvU+d/9pe839 rzQPhhY/AQsweIHQn9+F6Ctmn7kzvUOOboWvX+Ef87qpUWWcSUCO1bQZCCdrotdF/kidpB 5NSij9fuZWYbZfW+96HvA04cuOW8+MmwtJZyMtP3KEIeoR/N+MyTh1v37rRkFHRYZouxPz IxH/rbrLDxOiIAzRss4x45sKhMwzKpnHQ5Li4eOFIVMeIEEoeJEf7DIu1Ls1TQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1722615335; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=VI6ArGD5nH+JTATcGxIw1bvZF42wAjPrLzfbKGCDYP0=; b=gr+ayd6OdYb8XRJqaM6Fl4Rg8CypB0f34dNfn6hWfMwDz8uIjyr0toaobUMl1r6WRpdYVH v8gCX0wh4gWp+PDg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Breno Leitao Subject: [patch 01/15] x86/ioapic: Handle allocation failures gracefully References: <20240802155038.556977544@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Fri, 2 Aug 2024 18:15:34 +0200 (CEST) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Breno observed panics when using failslab under certain conditions during runtime: can not alloc irq_pin_list (-1,0,20) Kernel panic - not syncing: IO-APIC: failed to add irq-pin. Can not proc= eed panic+0x4e9/0x590 mp_irqdomain_alloc+0x9ab/0xa80 irq_domain_alloc_irqs_locked+0x25d/0x8d0 __irq_domain_alloc_irqs+0x80/0x110 mp_map_pin_to_irq+0x645/0x890 acpi_register_gsi_ioapic+0xe6/0x150 hpet_open+0x313/0x480 That's a pointless panic which is a leftover of the historic IO/APIC code which panic'ed during early boot when the interrupt allocation failed. The only place which might justify panic is the PIT/HPET timer_check() code which tries to figure out whether the timer interrupt is delivered through the IO/APIC. But that code does not require to handle interrupt allocation failures. If the interrupt cannot be allocated then timer delivery fails and it either panics due to that or falls back to legacy mode. Cure this by removing the panic wrapper around __add_pin_to_irq_node() and making mp_irqdomain_alloc() aware of the failure condition and handle it as any other failure in this function gracefully. Reported-by: Breno Leitao Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/all/ZqfJmUF8sXIyuSHN@gmail.com Tested-by: Breno Leitao --- arch/x86/kernel/apic/io_apic.c | 46 +++++++++++++++++++-----------------= ----- 1 file changed, 22 insertions(+), 24 deletions(-) --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -352,27 +352,26 @@ static void ioapic_mask_entry(int apic, * shared ISA-space IRQs, so we have to support them. We are super * fast in the common case, and fast for shared ISA-space IRQs. */ -static int __add_pin_to_irq_node(struct mp_chip_data *data, - int node, int apic, int pin) +static bool add_pin_to_irq_node(struct mp_chip_data *data, int node, int a= pic, int pin) { struct irq_pin_list *entry; =20 - /* don't allow duplicates */ - for_each_irq_pin(entry, data->irq_2_pin) + /* Don't allow duplicates */ + for_each_irq_pin(entry, data->irq_2_pin) { if (entry->apic =3D=3D apic && entry->pin =3D=3D pin) - return 0; + return true; + } =20 entry =3D kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node); if (!entry) { - pr_err("can not alloc irq_pin_list (%d,%d,%d)\n", - node, apic, pin); - return -ENOMEM; + pr_err("Cannot allocate irq_pin_list (%d,%d,%d)\n", node, apic, pin); + return false; } + entry->apic =3D apic; entry->pin =3D pin; list_add_tail(&entry->list, &data->irq_2_pin); - - return 0; + return true; } =20 static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int= pin) @@ -387,13 +386,6 @@ static void __remove_pin_from_irq(struct } } =20 -static void add_pin_to_irq_node(struct mp_chip_data *data, - int node, int apic, int pin) -{ - if (__add_pin_to_irq_node(data, node, apic, pin)) - panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); -} - /* * Reroute an IRQ to a different pin. */ @@ -1002,8 +994,7 @@ static int alloc_isa_irq_from_domain(str if (irq_data && irq_data->parent_data) { if (!mp_check_pin_attr(irq, info)) return -EBUSY; - if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic, - info->ioapic.pin)) + if (!add_pin_to_irq_node(irq_data->chip_data, node, ioapic, info->ioapic= .pin)) return -ENOMEM; } else { info->flags |=3D X86_IRQ_ALLOC_LEGACY; @@ -3017,10 +3008,8 @@ int mp_irqdomain_alloc(struct irq_domain return -ENOMEM; =20 ret =3D irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info); - if (ret < 0) { - kfree(data); - return ret; - } + if (ret < 0) + goto free_data; =20 INIT_LIST_HEAD(&data->irq_2_pin); irq_data->hwirq =3D info->ioapic.pin; @@ -3029,7 +3018,10 @@ int mp_irqdomain_alloc(struct irq_domain irq_data->chip_data =3D data; mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info); =20 - add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin); + if (!add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin)= ) { + ret =3D -ENOMEM; + goto free_irqs; + } =20 mp_preconfigure_entry(data); mp_register_handler(virq, data->is_level); @@ -3044,6 +3036,12 @@ int mp_irqdomain_alloc(struct irq_domain ioapic, mpc_ioapic_id(ioapic), pin, virq, data->is_level, data->active_low); return 0; + +free_irqs: + irq_domain_free_irqs_parent(domain, virq, nr_irqs); +free_data: + kfree(data); + return ret; } =20 void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq, From nobody Sun Feb 8 01:52:30 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95D701537CB for ; Fri, 2 Aug 2024 16:15:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722615345; cv=none; b=tTmBEzcQAQyemCecZaeYOIbcFMYqPowHq7AVPtk36FcL3901HEoLOhXjqcE5QaPxvGcRgQmsFR80u8mKX2XZAWgB0U1oaPyjfYT8fQ2CCFSGPdgcQsuyci4Ebl4PCjuCXqWI47nfJ4zg3n5uKbZeFH0tQuEiPY4SlgzGdtR7Dfk= ARC-Message-Signature: i=1; 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dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="e2zQbNLz"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="mHHRCZP0" Message-ID: <20240802155440.339321108@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1722615336; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=qtachSD9CHGIuW1+NiF6ehzxlAFmcNUSE5sNOCErmPE=; b=e2zQbNLzh10c99bYqN0iVZoekTOpkGNYH07rMObKCOZkshvl9ZDwvvAg12HsTTjpVONTnn gyXWAyllh4M9VssF+ruAnOJcWRIAGqr+bN4HXZl8lGhU9Ot6FOSgrP2JNkexFLdBY+gdL1 185WU8yrBaMPgtUgomvU+MbCopF9MfpS8ZtiYZ4wX8GNv4zLbkbvFmvA+YMjrJMQRHREmN nkRMi3oQ+kF4sX3KHTmbMZQNRdqGodrt/9m7Ek6t/ChZ0+ciscyqHboEi/EMulyor6hU/V JV+mvvXX5IZtX3P1/Uopy4lYvROBjlc7ATpRROIpHn7pAhdCY5jJH0+X5uaegw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1722615336; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=qtachSD9CHGIuW1+NiF6ehzxlAFmcNUSE5sNOCErmPE=; b=mHHRCZP0GqA64z1LB4h654m6R4+/gQYL9cFS4oc8jENyIwOH7J/GHDjmTO3XyHx4f9glSc 5rZz3/mHPVohpYAQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org Subject: [patch 02/15] x86/ioapic: Mark mp_alloc_timer_irq() __init References: <20240802155038.556977544@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Fri, 2 Aug 2024 18:15:36 +0200 (CEST) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Only invoked from check_timer() which is __init too. Cleanup the variable declaration while at it. Signed-off-by: Thomas Gleixner Reviewed-by: Breno Leitao Tested-by: Breno Leitao --- arch/x86/kernel/apic/io_apic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -2122,10 +2122,10 @@ static int __init disable_timer_pin_setu } early_param("disable_timer_pin_1", disable_timer_pin_setup); =20 -static int mp_alloc_timer_irq(int ioapic, int pin) +static int __init mp_alloc_timer_irq(int ioapic, int pin) { - int irq =3D -1; struct irq_domain *domain =3D mp_ioapic_irqdomain(ioapic); + int irq =3D -1; =20 if (domain) { struct irq_alloc_info info; From nobody Sun Feb 8 01:52:30 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48CAC1537DA for ; Fri, 2 Aug 2024 16:15:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722615345; cv=none; b=hHTVVKay+Kd5FrkCsH4auYLVqqa78qFNHeV71cSEsuk2e+W+BbkHgMEuoCEhgB5dJXvDtjN9uVnHNV++d58oNt8fK2WknyIv8DuuaYD9oWcLjMldK354+wHJXDF9umvalrrkpeEQ3TTGFIpVPW2hDyfSAlcG2YAmGmjpwYv4exA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722615345; c=relaxed/simple; bh=q1nyCI9+/a85UsWDuTd9B4jBeh4y7VZxEQ9MkGP9QuU=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=gygZ16FQJFpJB+L8CVguuXEGo7rDYtdZ905/tBBkF5ePZPnSKET3+uQE5hY+lIygT4LDZZqj7KeiD9+oAXCooKaE7b5R1xxp5yddLUZRLhkZlA/qwcWzNi9T6vOUs5wslH9n0Mc6aeNBhczk0pkPxF97pHUHYKk3oAuElqTi6F0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=jWYgpnxf; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=rK66vc4p; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="jWYgpnxf"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="rK66vc4p" Message-ID: <20240802155440.402005874@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1722615337; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=+O+7pwggQzEjLaphpw3Ohc+YFDfRA7SuEbINblJ/VjA=; b=jWYgpnxffi6/osyZdgcRt6uHyQWK3chulNzOZniz+2FsXnTDERcfOtlTclS8UpJa4L4j9Y nBtEjXtCDrzZYaxQlkhGYDRIWnvuNHJM5oIRkscCb39zGhY70y6Ngre3rLEY+KyN+UXvmt 21G7r1zGZzMoK6fMAS6RTPlkciCzukTQhOn0NOjOmcvU+pieQ0L6u6zJExqEsGzhxHgXdb 3q7SheLvr+rs7XeZa2wWnnQGKeM+r64dMPzPOw/UMKCW7Ty35BSfF8DcnTB4snIYuE9ImZ u1Cy6zr0tjEbk2Bqs2Q+8JvWurvainue8SNdllrbsssN7kMhcn1yVPOhoYfxeg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1722615337; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=+O+7pwggQzEjLaphpw3Ohc+YFDfRA7SuEbINblJ/VjA=; b=rK66vc4pZb2Flkw5VKwsJdccTelYemHIVx0bXK4hX594Gh0hmI8EcZbl32bE0sKmd6SYMa DEqo2lkIgflfcuCA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org Subject: [patch 03/15] x86/ioapic: Cleanup structs References: <20240802155038.556977544@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Fri, 2 Aug 2024 18:15:37 +0200 (CEST) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Make them conforming to the TIP coding style guide. Signed-off-by: Thomas Gleixner Tested-by: Breno Leitao --- arch/x86/kernel/apic/io_apic.c | 32 ++++++++++++++------------------ 1 file changed, 14 insertions(+), 18 deletions(-) --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -86,8 +86,8 @@ static unsigned int ioapic_dynirq_base; static int ioapic_initialized; =20 struct irq_pin_list { - struct list_head list; - int apic, pin; + struct list_head list; + int apic, pin; }; =20 struct mp_chip_data { @@ -96,7 +96,7 @@ struct mp_chip_data { bool is_level; bool active_low; bool isa_irq; - u32 count; + u32 count; }; =20 struct mp_ioapic_gsi { @@ -105,21 +105,17 @@ struct mp_ioapic_gsi { }; =20 static struct ioapic { - /* - * # of IRQ routing registers - */ - int nr_registers; - /* - * Saved state during suspend/resume, or while enabling intr-remap. - */ - struct IO_APIC_route_entry *saved_registers; + /* # of IRQ routing registers */ + int nr_registers; + /* Saved state during suspend/resume, or while enabling intr-remap. */ + struct IO_APIC_route_entry *saved_registers; /* I/O APIC config */ - struct mpc_ioapic mp_config; + struct mpc_ioapic mp_config; /* IO APIC gsi routing info */ - struct mp_ioapic_gsi gsi_config; - struct ioapic_domain_cfg irqdomain_cfg; - struct irq_domain *irqdomain; - struct resource *iomem_res; + struct mp_ioapic_gsi gsi_config; + struct ioapic_domain_cfg irqdomain_cfg; + struct irq_domain *irqdomain; + struct resource *iomem_res; } ioapics[MAX_IO_APICS]; =20 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver @@ -2431,8 +2427,8 @@ static void ioapic_resume(void) } =20 static struct syscore_ops ioapic_syscore_ops =3D { - .suspend =3D save_ioapic_entries, - .resume =3D ioapic_resume, + .suspend =3D save_ioapic_entries, + .resume =3D ioapic_resume, }; =20 static int __init ioapic_init_ops(void) From nobody Sun Feb 8 01:52:30 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F075515C149 for ; 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a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1722615338; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=nr6zjw/gg7flMSt9T0LIwxjmi11hTeV/4/wlk1cq0b8=; b=YP+r6d85B8B3wZs49sWMlWWDmZHrP6S6l5AaKONraLHalZz65m4Ni59egaNOAgshbb/tnI xZOpbBfIdCP3tqDg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org Subject: [patch 04/15] x86/ioapic: Use guard() for locking where applicable References: <20240802155038.556977544@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Fri, 2 Aug 2024 18:15:38 +0200 (CEST) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" KISS rules! Signed-off-by: Thomas Gleixner Tested-by: Breno Leitao --- arch/x86/kernel/apic/io_apic.c | 192 +++++++++++++-----------------------= ----- 1 file changed, 64 insertions(+), 128 deletions(-) --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -296,14 +296,8 @@ static struct IO_APIC_route_entry __ioap =20 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) { - struct IO_APIC_route_entry entry; - unsigned long flags; - - raw_spin_lock_irqsave(&ioapic_lock, flags); - entry =3D __ioapic_read_entry(apic, pin); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); - - return entry; + guard(raw_spinlock_irqsave)(&ioapic_lock); + return __ioapic_read_entry(apic, pin); } =20 /* @@ -320,11 +314,8 @@ static void __ioapic_write_entry(int api =20 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_ent= ry e) { - unsigned long flags; - - raw_spin_lock_irqsave(&ioapic_lock, flags); + guard(raw_spinlock_irqsave)(&ioapic_lock); __ioapic_write_entry(apic, pin, e); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); } =20 /* @@ -335,12 +326,10 @@ static void ioapic_write_entry(int apic, static void ioapic_mask_entry(int apic, int pin) { struct IO_APIC_route_entry e =3D { .masked =3D true }; - unsigned long flags; =20 - raw_spin_lock_irqsave(&ioapic_lock, flags); + guard(raw_spinlock_irqsave)(&ioapic_lock); io_apic_write(apic, 0x10 + 2*pin, e.w1); io_apic_write(apic, 0x11 + 2*pin, e.w2); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); } =20 /* @@ -433,11 +422,9 @@ static void io_apic_sync(struct irq_pin_ static void mask_ioapic_irq(struct irq_data *irq_data) { struct mp_chip_data *data =3D irq_data->chip_data; - unsigned long flags; =20 - raw_spin_lock_irqsave(&ioapic_lock, flags); + guard(raw_spinlock_irqsave)(&ioapic_lock); io_apic_modify_irq(data, true, &io_apic_sync); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); } =20 static void __unmask_ioapic(struct mp_chip_data *data) @@ -448,11 +435,9 @@ static void __unmask_ioapic(struct mp_ch static void unmask_ioapic_irq(struct irq_data *irq_data) { struct mp_chip_data *data =3D irq_data->chip_data; - unsigned long flags; =20 - raw_spin_lock_irqsave(&ioapic_lock, flags); + guard(raw_spinlock_irqsave)(&ioapic_lock); __unmask_ioapic(data); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); } =20 /* @@ -497,13 +482,11 @@ static void __eoi_ioapic_pin(int apic, i =20 static void eoi_ioapic_pin(int vector, struct mp_chip_data *data) { - unsigned long flags; struct irq_pin_list *entry; =20 - raw_spin_lock_irqsave(&ioapic_lock, flags); + guard(raw_spinlock_irqsave)(&ioapic_lock); for_each_irq_pin(entry, data->irq_2_pin) __eoi_ioapic_pin(entry->apic, entry->pin, vector); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); } =20 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) @@ -526,8 +509,6 @@ static void clear_IO_APIC_pin(unsigned i } =20 if (entry.irr) { - unsigned long flags; - /* * Make sure the trigger mode is set to level. Explicit EOI * doesn't clear the remote-IRR if the trigger mode is not @@ -537,9 +518,8 @@ static void clear_IO_APIC_pin(unsigned i entry.is_level =3D true; ioapic_write_entry(apic, pin, entry); } - raw_spin_lock_irqsave(&ioapic_lock, flags); + guard(raw_spinlock_irqsave)(&ioapic_lock); __eoi_ioapic_pin(apic, pin, entry.vector); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); } =20 /* @@ -1033,7 +1013,7 @@ static int mp_map_pin_to_irq(u32 gsi, in return -EINVAL; } =20 - mutex_lock(&ioapic_mutex); + guard(mutex)(&ioapic_mutex); if (!(flags & IOAPIC_MAP_ALLOC)) { if (!legacy) { irq =3D irq_find_mapping(domain, pin); @@ -1054,8 +1034,6 @@ static int mp_map_pin_to_irq(u32 gsi, in data->count++; } } - mutex_unlock(&ioapic_mutex); - return irq; } =20 @@ -1120,10 +1098,9 @@ void mp_unmap_irq(int irq) if (!data || data->isa_irq) return; =20 - mutex_lock(&ioapic_mutex); + guard(mutex)(&ioapic_mutex); if (--data->count =3D=3D 0) irq_domain_free_irqs(irq, 1); - mutex_unlock(&ioapic_mutex); } =20 /* @@ -1251,16 +1228,15 @@ static void __init print_IO_APIC(int ioa union IO_APIC_reg_01 reg_01; union IO_APIC_reg_02 reg_02; union IO_APIC_reg_03 reg_03; - unsigned long flags; =20 - raw_spin_lock_irqsave(&ioapic_lock, flags); - reg_00.raw =3D io_apic_read(ioapic_idx, 0); - reg_01.raw =3D io_apic_read(ioapic_idx, 1); - if (reg_01.bits.version >=3D 0x10) - reg_02.raw =3D io_apic_read(ioapic_idx, 2); - if (reg_01.bits.version >=3D 0x20) - reg_03.raw =3D io_apic_read(ioapic_idx, 3); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); + scoped_guard (raw_spinlock_irqsave, &ioapic_lock) { + reg_00.raw =3D io_apic_read(ioapic_idx, 0); + reg_01.raw =3D io_apic_read(ioapic_idx, 1); + if (reg_01.bits.version >=3D 0x10) + reg_02.raw =3D io_apic_read(ioapic_idx, 2); + if (reg_01.bits.version >=3D 0x20) + reg_03.raw =3D io_apic_read(ioapic_idx, 3); + } =20 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx)); printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); @@ -1451,7 +1427,6 @@ static void __init setup_ioapic_ids_from const u32 broadcast_id =3D 0xF; union IO_APIC_reg_00 reg_00; unsigned char old_id; - unsigned long flags; int ioapic_idx, i; =20 /* @@ -1465,9 +1440,8 @@ static void __init setup_ioapic_ids_from */ for_each_ioapic(ioapic_idx) { /* Read the register 0 value */ - raw_spin_lock_irqsave(&ioapic_lock, flags); - reg_00.raw =3D io_apic_read(ioapic_idx, 0); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); + scoped_guard (raw_spinlock_irqsave, &ioapic_lock) + reg_00.raw =3D io_apic_read(ioapic_idx, 0); =20 old_id =3D mpc_ioapic_id(ioapic_idx); =20 @@ -1522,16 +1496,11 @@ static void __init setup_ioapic_ids_from mpc_ioapic_id(ioapic_idx)); =20 reg_00.bits.ID =3D mpc_ioapic_id(ioapic_idx); - raw_spin_lock_irqsave(&ioapic_lock, flags); - io_apic_write(ioapic_idx, 0, reg_00.raw); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); - - /* - * Sanity check - */ - raw_spin_lock_irqsave(&ioapic_lock, flags); - reg_00.raw =3D io_apic_read(ioapic_idx, 0); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); + scoped_guard (raw_spinlock_irqsave, &ioapic_lock) { + io_apic_write(ioapic_idx, 0, reg_00.raw); + reg_00.raw =3D io_apic_read(ioapic_idx, 0); + } + /* Sanity check */ if (reg_00.bits.ID !=3D mpc_ioapic_id(ioapic_idx)) pr_cont("could not set ID!\n"); else @@ -1661,17 +1630,14 @@ static int __init timer_irq_works(void) static unsigned int startup_ioapic_irq(struct irq_data *data) { int was_pending =3D 0, irq =3D data->irq; - unsigned long flags; =20 - raw_spin_lock_irqsave(&ioapic_lock, flags); + guard(raw_spinlock_irqsave)(&ioapic_lock); if (irq < nr_legacy_irqs()) { legacy_pic->mask(irq); if (legacy_pic->irq_pending(irq)) was_pending =3D 1; } __unmask_ioapic(data->chip_data); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); - return was_pending; } =20 @@ -1681,9 +1647,8 @@ atomic_t irq_mis_count; static bool io_apic_level_ack_pending(struct mp_chip_data *data) { struct irq_pin_list *entry; - unsigned long flags; =20 - raw_spin_lock_irqsave(&ioapic_lock, flags); + guard(raw_spinlock_irqsave)(&ioapic_lock); for_each_irq_pin(entry, data->irq_2_pin) { struct IO_APIC_route_entry e; int pin; @@ -1691,13 +1656,9 @@ static bool io_apic_level_ack_pending(st pin =3D entry->pin; e.w1 =3D io_apic_read(entry->apic, 0x10 + pin*2); /* Is the remote IRR bit set? */ - if (e.irr) { - raw_spin_unlock_irqrestore(&ioapic_lock, flags); + if (e.irr) return true; - } } - raw_spin_unlock_irqrestore(&ioapic_lock, flags); - return false; } =20 @@ -1898,18 +1859,16 @@ static void ioapic_configure_entry(struc __ioapic_write_entry(entry->apic, entry->pin, mpd->entry); } =20 -static int ioapic_set_affinity(struct irq_data *irq_data, - const struct cpumask *mask, bool force) +static int ioapic_set_affinity(struct irq_data *irq_data, const struct cpu= mask *mask, bool force) { struct irq_data *parent =3D irq_data->parent_data; - unsigned long flags; int ret; =20 ret =3D parent->chip->irq_set_affinity(parent, mask, force); - raw_spin_lock_irqsave(&ioapic_lock, flags); + + guard(raw_spinlock_irqsave)(&ioapic_lock); if (ret >=3D 0 && ret !=3D IRQ_SET_MASK_OK_DONE) ioapic_configure_entry(irq_data); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); =20 return ret; } @@ -1928,9 +1887,8 @@ static int ioapic_set_affinity(struct ir * * Verify that the corresponding Remote-IRR bits are clear. */ -static int ioapic_irq_get_chip_state(struct irq_data *irqd, - enum irqchip_irq_state which, - bool *state) +static int ioapic_irq_get_chip_state(struct irq_data *irqd, enum irqchip_i= rq_state which, + bool *state) { struct mp_chip_data *mcd =3D irqd->chip_data; struct IO_APIC_route_entry rentry; @@ -1940,7 +1898,8 @@ static int ioapic_irq_get_chip_state(str return -EINVAL; =20 *state =3D false; - raw_spin_lock(&ioapic_lock); + + guard(raw_spinlock)(&ioapic_lock); for_each_irq_pin(p, mcd->irq_2_pin) { rentry =3D __ioapic_read_entry(p->apic, p->pin); /* @@ -1954,7 +1913,6 @@ static int ioapic_irq_get_chip_state(str break; } } - raw_spin_unlock(&ioapic_lock); return 0; } =20 @@ -2129,9 +2087,8 @@ static int __init mp_alloc_timer_irq(int ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0); info.devid =3D mpc_ioapic_id(ioapic); info.ioapic.pin =3D pin; - mutex_lock(&ioapic_mutex); + guard(mutex)(&ioapic_mutex); irq =3D alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info); - mutex_unlock(&ioapic_mutex); } =20 return irq; @@ -2142,8 +2099,6 @@ static int __init mp_alloc_timer_irq(int * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ * is so screwy. Thanks to Brian Perkins for testing/hacking this beast * fanatically on his truly buggy board. - * - * FIXME: really need to revamp this for all platforms. */ static inline void __init check_timer(void) { @@ -2404,16 +2359,14 @@ void __init setup_IO_APIC(void) =20 static void resume_ioapic_id(int ioapic_idx) { - unsigned long flags; union IO_APIC_reg_00 reg_00; =20 - raw_spin_lock_irqsave(&ioapic_lock, flags); + guard(raw_spinlock_irqsave)(&ioapic_lock); reg_00.raw =3D io_apic_read(ioapic_idx, 0); if (reg_00.bits.ID !=3D mpc_ioapic_id(ioapic_idx)) { reg_00.bits.ID =3D mpc_ioapic_id(ioapic_idx); io_apic_write(ioapic_idx, 0, reg_00.raw); } - raw_spin_unlock_irqrestore(&ioapic_lock, flags); } =20 static void ioapic_resume(void) @@ -2443,15 +2396,13 @@ device_initcall(ioapic_init_ops); static int io_apic_get_redir_entries(int ioapic) { union IO_APIC_reg_01 reg_01; - unsigned long flags; =20 - raw_spin_lock_irqsave(&ioapic_lock, flags); + guard(raw_spinlock_irqsave)(&ioapic_lock); reg_01.raw =3D io_apic_read(ioapic, 1); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); =20 - /* The register returns the maximum index redir index - * supported, which is one less than the total number of redir - * entries. + /* + * The register returns the maximum index redir index supported, + * which is one less than the total number of redir entries. */ return reg_01.bits.entries + 1; } @@ -2481,16 +2432,14 @@ static int io_apic_get_unique_id(int ioa static DECLARE_BITMAP(apic_id_map, MAX_LOCAL_APIC); const u32 broadcast_id =3D 0xF; union IO_APIC_reg_00 reg_00; - unsigned long flags; int i =3D 0; =20 /* Initialize the ID map */ if (bitmap_empty(apic_id_map, MAX_LOCAL_APIC)) copy_phys_cpu_present_map(apic_id_map); =20 - raw_spin_lock_irqsave(&ioapic_lock, flags); - reg_00.raw =3D io_apic_read(ioapic, 0); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); + scoped_guard (raw_spinlock_irqsave, &ioapic_lock) + reg_00.raw =3D io_apic_read(ioapic, 0); =20 if (apic_id >=3D broadcast_id) { pr_warn("IOAPIC[%d]: Invalid apic_id %d, trying %d\n", @@ -2517,21 +2466,19 @@ static int io_apic_get_unique_id(int ioa if (reg_00.bits.ID !=3D apic_id) { reg_00.bits.ID =3D apic_id; =20 - raw_spin_lock_irqsave(&ioapic_lock, flags); - io_apic_write(ioapic, 0, reg_00.raw); - reg_00.raw =3D io_apic_read(ioapic, 0); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); + scoped_guard (raw_spinlock_irqsave, &ioapic_lock) { + io_apic_write(ioapic, 0, reg_00.raw); + reg_00.raw =3D io_apic_read(ioapic, 0); + } =20 /* Sanity check */ if (reg_00.bits.ID !=3D apic_id) { - pr_err("IOAPIC[%d]: Unable to change apic_id!\n", - ioapic); + pr_err("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); return -1; } } =20 - apic_printk(APIC_VERBOSE, KERN_INFO - "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); + apic_printk(APIC_VERBOSE, KERN_INFO "IOAPIC[%d]: Assigned apic_id %d\n", = ioapic, apic_id); =20 return apic_id; } @@ -2547,7 +2494,6 @@ static u8 io_apic_unique_id(int idx, u8 { union IO_APIC_reg_00 reg_00; DECLARE_BITMAP(used, 256); - unsigned long flags; u8 new_id; int i; =20 @@ -2563,26 +2509,23 @@ static u8 io_apic_unique_id(int idx, u8 * Read the current id from the ioapic and keep it if * available. */ - raw_spin_lock_irqsave(&ioapic_lock, flags); - reg_00.raw =3D io_apic_read(idx, 0); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); + scoped_guard (raw_spinlock_irqsave, &ioapic_lock) + reg_00.raw =3D io_apic_read(idx, 0); + new_id =3D reg_00.bits.ID; if (!test_bit(new_id, used)) { - apic_printk(APIC_VERBOSE, KERN_INFO - "IOAPIC[%d]: Using reg apic_id %d instead of %d\n", - idx, new_id, id); + apic_printk(APIC_VERBOSE, KERN_INFO "IOAPIC[%d]: Using reg apic_id %d in= stead of %d\n", + idx, new_id, id); return new_id; } =20 - /* - * Get the next free id and write it to the ioapic. - */ + /* Get the next free id and write it to the ioapic. */ new_id =3D find_first_zero_bit(used, 256); reg_00.bits.ID =3D new_id; - raw_spin_lock_irqsave(&ioapic_lock, flags); - io_apic_write(idx, 0, reg_00.raw); - reg_00.raw =3D io_apic_read(idx, 0); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); + scoped_guard (raw_spinlock_irqsave, &ioapic_lock) { + io_apic_write(idx, 0, reg_00.raw); + reg_00.raw =3D io_apic_read(idx, 0); + } /* Sanity check */ BUG_ON(reg_00.bits.ID !=3D new_id); =20 @@ -2592,12 +2535,10 @@ static u8 io_apic_unique_id(int idx, u8 =20 static int io_apic_get_version(int ioapic) { - union IO_APIC_reg_01 reg_01; - unsigned long flags; + union IO_APIC_reg_01 reg_01; =20 - raw_spin_lock_irqsave(&ioapic_lock, flags); + guard(raw_spinlock_irqsave)(&ioapic_lock); reg_01.raw =3D io_apic_read(ioapic, 1); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); =20 return reg_01.bits.version; } @@ -3050,22 +2991,17 @@ void mp_irqdomain_free(struct irq_domain irq_data =3D irq_domain_get_irq_data(domain, virq); if (irq_data && irq_data->chip_data) { data =3D irq_data->chip_data; - __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain), - (int)irq_data->hwirq); + __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain), (int)irq_da= ta->hwirq); WARN_ON(!list_empty(&data->irq_2_pin)); kfree(irq_data->chip_data); } irq_domain_free_irqs_top(domain, virq, nr_irqs); } =20 -int mp_irqdomain_activate(struct irq_domain *domain, - struct irq_data *irq_data, bool reserve) +int mp_irqdomain_activate(struct irq_domain *domain, struct irq_data *irq_= data, bool reserve) { - unsigned long flags; - - raw_spin_lock_irqsave(&ioapic_lock, flags); + guard(raw_spinlock_irqsave)(&ioapic_lock); ioapic_configure_entry(irq_data); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); return 0; } From nobody Sun Feb 8 01:52:30 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48C571537D8 for ; Fri, 2 Aug 2024 16:15:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722615345; cv=none; b=u7VhrzOKRIM46UqMDdIPjknchV4qGNkg9sgUePoNyW+pdrcUJIDAIgNGF5+viC9vuY/YMiN2lsou7qbH3sE9C76hweHdoimvNpR3MTTHAgmiGAoOxlAUuwSdFn9msEqGdVsPgwr8Lia4Y9/0Y8PFB3Yfky9XYLBZz0RfBD6oSno= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722615345; c=relaxed/simple; bh=+lhf1qJQ0eCZ0gZ26l9fyyX3+JU0tfa4kDsXcHnTpa8=; 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charset="utf-8" apic_printk() requires the APIC verbosity level and printk level which is tedious and horrible to read. Provide helpers to simplify all of that. Signed-off-by: Thomas Gleixner Tested-by: Breno Leitao --- arch/x86/include/asm/apic.h | 33 +++++++++++++++++++-------------- 1 file changed, 19 insertions(+), 14 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -18,6 +18,11 @@ =20 #define ARCH_APICTIMER_STOPS_ON_C3 1 =20 +/* Macros for apic_extnmi which controls external NMI masking */ +#define APIC_EXTNMI_BSP 0 /* Default */ +#define APIC_EXTNMI_ALL 1 +#define APIC_EXTNMI_NONE 2 + /* * Debugging macros */ @@ -25,22 +30,22 @@ #define APIC_VERBOSE 1 #define APIC_DEBUG 2 =20 -/* Macros for apic_extnmi which controls external NMI masking */ -#define APIC_EXTNMI_BSP 0 /* Default */ -#define APIC_EXTNMI_ALL 1 -#define APIC_EXTNMI_NONE 2 - /* - * Define the default level of output to be very little - * This can be turned up by using apic=3Dverbose for more - * information and apic=3Ddebug for _lots_ of information. - * apic_verbosity is defined in apic.c + * Define the default level of output to be very little This can be turned + * up by using apic=3Dverbose for more information and apic=3Ddebug for _l= ots_ + * of information. apic_verbosity is defined in apic.c */ -#define apic_printk(v, s, a...) do { \ - if ((v) <=3D apic_verbosity) \ - printk(s, ##a); \ - } while (0) - +#define apic_printk(v, s, a...) \ +do { \ + if ((v) <=3D apic_verbosity) \ + printk(s, ##a); \ +} while (0) + +#define apic_pr_verbose(s, a...) apic_printk(APIC_VERBOSE, KERN_INFO s, ##= a) +#define apic_pr_debug(s, a...) apic_printk(APIC_DEBUG, KERN_DEBUG s, ##a) +#define apic_pr_debug_cont(s, a...) apic_printk(APIC_DEBUG, KERN_CONT s, #= #a) +/* Unconditional debug prints for code which is guarded by apic_verbosity = already */ +#define apic_dbg(s, a...) printk(KERN_DEBUG s, ##a) =20 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) extern void x86_32_probe_apic(void); From nobody Sun Feb 8 01:52:30 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48CEC1537DD for ; Fri, 2 Aug 2024 16:15:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; 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a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1722615341; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=lCvkAigTlvnFjCeCyGJ6ZWYJAg8BjhRd+upNYUEttLE=; b=Bg5DIahBaczWJdlUMn/rtBuRilettrj7Ddo9gLv5rUgY1Q4MVvXpiiQVu2x9tujJm+q2oS cR5orcFagrORX3DQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org Subject: [patch 06/15] x86/apic: Cleanup apic_printk()s References: <20240802155038.556977544@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Fri, 2 Aug 2024 18:15:41 +0200 (CEST) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use the new apic_pr_*() helpers and cleanup the apic_printk() maze. Signed-off-by: Thomas Gleixner Tested-by: Breno Leitao --- arch/x86/kernel/apic/apic.c | 81 +++++++++++++++++++--------------------= ----- 1 file changed, 35 insertions(+), 46 deletions(-) --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -677,7 +677,7 @@ calibrate_by_pmtimer(u32 deltapm, long * return -1; #endif =20 - apic_printk(APIC_VERBOSE, "... PM-Timer delta =3D %u\n", deltapm); + apic_pr_verbose("... PM-Timer delta =3D %u\n", deltapm); =20 /* Check, if the PM timer is available */ if (!deltapm) @@ -687,14 +687,14 @@ calibrate_by_pmtimer(u32 deltapm, long * =20 if (deltapm > (pm_100ms - pm_thresh) && deltapm < (pm_100ms + pm_thresh)) { - apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); + apic_pr_verbose("... PM-Timer result ok\n"); return 0; } =20 res =3D (((u64)deltapm) * mult) >> 22; do_div(res, 1000000); - pr_warn("APIC calibration not consistent " - "with PM-Timer: %ldms instead of 100ms\n", (long)res); + pr_warn("APIC calibration not consistent with PM-Timer: %ldms instead of = 100ms\n", + (long)res); =20 /* Correct the lapic counter value */ res =3D (((u64)(*delta)) * pm_100ms); @@ -707,9 +707,8 @@ calibrate_by_pmtimer(u32 deltapm, long * if (boot_cpu_has(X86_FEATURE_TSC)) { res =3D (((u64)(*deltatsc)) * pm_100ms); do_div(res, deltapm); - apic_printk(APIC_VERBOSE, "TSC delta adjusted to " - "PM-Timer: %lu (%ld)\n", - (unsigned long)res, *deltatsc); + apic_pr_verbose("TSC delta adjusted to PM-Timer: %lu (%ld)\n", + (unsigned long)res, *deltatsc); *deltatsc =3D (long)res; } =20 @@ -792,8 +791,7 @@ static int __init calibrate_APIC_clock(v * in the clockevent structure and return. */ if (!lapic_init_clockevent()) { - apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", - lapic_timer_period); + apic_pr_verbose("lapic timer already calibrated %d\n", lapic_timer_perio= d); /* * Direct calibration methods must have an always running * local APIC timer, no need for broadcast timer. @@ -802,8 +800,7 @@ static int __init calibrate_APIC_clock(v return 0; } =20 - apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" - "calibrating APIC timer ...\n"); + apic_pr_verbose("Using local APIC timer interrupts. Calibrating APIC time= r ...\n"); =20 /* * There are platforms w/o global clockevent devices. Instead of @@ -866,7 +863,7 @@ static int __init calibrate_APIC_clock(v =20 /* Build delta t1-t2 as apic timer counts down */ delta =3D lapic_cal_t1 - lapic_cal_t2; - apic_printk(APIC_VERBOSE, "... lapic delta =3D %ld\n", delta); + apic_pr_verbose("... lapic delta =3D %ld\n", delta); =20 deltatsc =3D (long)(lapic_cal_tsc2 - lapic_cal_tsc1); =20 @@ -877,22 +874,19 @@ static int __init calibrate_APIC_clock(v lapic_timer_period =3D (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; lapic_init_clockevent(); =20 - apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); - apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); - apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", - lapic_timer_period); + apic_pr_verbose("..... delta %ld\n", delta); + apic_pr_verbose("..... mult: %u\n", lapic_clockevent.mult); + apic_pr_verbose("..... calibration result: %u\n", lapic_timer_period); =20 if (boot_cpu_has(X86_FEATURE_TSC)) { - apic_printk(APIC_VERBOSE, "..... CPU clock speed is " - "%ld.%04ld MHz.\n", - (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), - (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); + apic_pr_verbose("..... CPU clock speed is %ld.%04ld MHz.\n", + (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), + (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); } =20 - apic_printk(APIC_VERBOSE, "..... host bus clock speed is " - "%u.%04u MHz.\n", - lapic_timer_period / (1000000 / HZ), - lapic_timer_period % (1000000 / HZ)); + apic_pr_verbose("..... host bus clock speed is %u.%04u MHz.\n", + lapic_timer_period / (1000000 / HZ), + lapic_timer_period % (1000000 / HZ)); =20 /* * Do a sanity check on the APIC calibration result @@ -911,7 +905,7 @@ static int __init calibrate_APIC_clock(v * available. */ if (!pm_referenced && global_clock_event) { - apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); + apic_pr_verbose("... verify APIC timer\n"); =20 /* * Setup the apic timer manually @@ -932,11 +926,11 @@ static int __init calibrate_APIC_clock(v =20 /* Jiffies delta */ deltaj =3D lapic_cal_j2 - lapic_cal_j1; - apic_printk(APIC_VERBOSE, "... jiffies delta =3D %lu\n", deltaj); + apic_pr_verbose("... jiffies delta =3D %lu\n", deltaj); =20 /* Check, if the jiffies result is consistent */ if (deltaj >=3D LAPIC_CAL_LOOPS-2 && deltaj <=3D LAPIC_CAL_LOOPS+2) - apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); + apic_pr_verbose("... jiffies result ok\n"); else levt->features |=3D CLOCK_EVT_FEAT_DUMMY; } @@ -1221,9 +1215,8 @@ void __init sync_Arb_IDs(void) */ apic_wait_icr_idle(); =20 - apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); - apic_write(APIC_ICR, APIC_DEST_ALLINC | - APIC_INT_LEVELTRIG | APIC_DM_INIT); + apic_pr_debug("Synchronizing Arb IDs.\n"); + apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | APIC_DM_INIT= ); } =20 enum apic_intr_mode_id apic_intr_mode __ro_after_init; @@ -1409,10 +1402,10 @@ static void lapic_setup_esr(void) if (maxlvt > 3) apic_write(APIC_ESR, 0); value =3D apic_read(APIC_ESR); - if (value !=3D oldvalue) - apic_printk(APIC_VERBOSE, "ESR value before enabling " - "vector: 0x%08x after: 0x%08x\n", - oldvalue, value); + if (value !=3D oldvalue) { + apic_pr_verbose("ESR value before enabling vector: 0x%08x after: 0x%08x= \n", + oldvalue, value); + } } =20 #define APIC_IR_REGS APIC_ISR_NR @@ -1599,10 +1592,10 @@ static void setup_local_APIC(void) value =3D apic_read(APIC_LVT0) & APIC_LVT_MASKED; if (!cpu && (pic_mode || !value || ioapic_is_disabled)) { value =3D APIC_DM_EXTINT; - apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); + apic_pr_verbose("Enabled ExtINT on CPU#%d\n", cpu); } else { value =3D APIC_DM_EXTINT | APIC_LVT_MASKED; - apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); + apic_pr_verbose("Masked ExtINT on CPU#%d\n", cpu); } apic_write(APIC_LVT0, value); =20 @@ -2066,8 +2059,7 @@ static __init void apic_set_fixmap(bool { set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); apic_mmio_base =3D APIC_BASE; - apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", - apic_mmio_base, mp_lapic_addr); + apic_pr_verbose("Mapped APIC to %16lx (%16lx)\n", apic_mmio_base, mp_lapi= c_addr); if (read_apic) apic_read_boot_cpu_id(false); } @@ -2170,18 +2162,17 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_error_inte apic_eoi(); atomic_inc(&irq_err_count); =20 - apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", - smp_processor_id(), v); + apic_pr_debug("APIC error on CPU%d: %02x", smp_processor_id(), v); =20 v &=3D 0xff; while (v) { if (v & 0x1) - apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); + apic_pr_debug_cont(" : %s", error_interrupt_reason[i]); i++; v >>=3D 1; } =20 - apic_printk(APIC_DEBUG, KERN_CONT "\n"); + apic_pr_debug_cont("\n"); =20 trace_error_apic_exit(ERROR_APIC_VECTOR); } @@ -2201,8 +2192,7 @@ static void __init connect_bsp_APIC(void * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's * local APIC to INT and NMI lines. */ - apic_printk(APIC_VERBOSE, "leaving PIC mode, " - "enabling APIC mode.\n"); + apic_pr_verbose("Leaving PIC mode, enabling APIC mode.\n"); imcr_pic_to_apic(); } #endif @@ -2227,8 +2217,7 @@ void disconnect_bsp_APIC(int virt_wire_s * IPIs, won't work beyond this point! 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Signed-off-by: Thomas Gleixner Tested-by: Breno Leitao --- arch/x86/kernel/apic/io_apic.c | 176 +++++++++++++++++-------------------= ----- 1 file changed, 73 insertions(+), 103 deletions(-) --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -201,10 +201,9 @@ void mp_save_irq(struct mpc_intsrc *m) { int i; =20 - apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," - " IRQ %02x, APIC ID %x, APIC INT %02x\n", - m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, - m->srcbusirq, m->dstapic, m->dstirq); + apic_pr_verbose("Int: type %d, pol %d, trig %d, bus %02x, IRQ %02x, APIC = ID %x, APIC INT %02x\n", + m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, + m->srcbusirq, m->dstapic, m->dstirq); =20 for (i =3D 0; i < mp_irq_entries; i++) { if (!memcmp(&mp_irqs[i], m, sizeof(*m))) @@ -554,28 +553,23 @@ static int pirq_entries[MAX_PIRQS] =3D { =20 static int __init ioapic_pirq_setup(char *str) { - int i, max; - int ints[MAX_PIRQS+1]; + int i, max, ints[MAX_PIRQS+1]; =20 get_options(str, ARRAY_SIZE(ints), ints); =20 - apic_printk(APIC_VERBOSE, KERN_INFO - "PIRQ redirection, working around broken MP-BIOS.\n"); + apic_pr_verbose("PIRQ redirection, working around broken MP-BIOS.\n"); + max =3D MAX_PIRQS; if (ints[0] < MAX_PIRQS) max =3D ints[0]; =20 for (i =3D 0; i < max; i++) { - apic_printk(APIC_VERBOSE, KERN_DEBUG - "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); - /* - * PIRQs are mapped upside down, usually. - */ + apic_pr_verbose("... PIRQ%d -> IRQ %d\n", i, ints[i + 1]); + /* PIRQs are mapped upside down, usually */ pirq_entries[MAX_PIRQS-i-1] =3D ints[i+1]; } return 1; } - __setup("pirq=3D", ioapic_pirq_setup); #endif /* CONFIG_X86_32 */ =20 @@ -737,8 +731,7 @@ static bool EISA_ELCR(unsigned int irq) unsigned int port =3D PIC_ELCR1 + (irq >> 3); return (inb(port) >> (irq & 7)) & 1; } - apic_printk(APIC_VERBOSE, KERN_INFO - "Broken MPtable reports ISA irq %d\n", irq); + apic_pr_verbose("Broken MPtable reports ISA irq %d\n", irq); return false; } =20 @@ -1052,15 +1045,13 @@ static int pin_2_irq(int idx, int ioapic * PCI IRQ command line redirection. Yes, limits are hardcoded. */ if ((pin >=3D 16) && (pin <=3D 23)) { - if (pirq_entries[pin-16] !=3D -1) { - if (!pirq_entries[pin-16]) { - apic_printk(APIC_VERBOSE, KERN_DEBUG - "disabling PIRQ%d\n", pin-16); + if (pirq_entries[pin - 16] !=3D -1) { + if (!pirq_entries[pin - 16]) { + apic_pr_verbose("Disabling PIRQ%d\n", pin - 16); } else { int irq =3D pirq_entries[pin-16]; - apic_printk(APIC_VERBOSE, KERN_DEBUG - "using PIRQ%d -> IRQ %d\n", - pin-16, irq); + + apic_pr_verbose("Using PIRQ%d -> IRQ %d\n", pin - 16, irq); return irq; } } @@ -1111,12 +1102,10 @@ int IO_APIC_get_PCI_irq_vector(int bus, { int irq, i, best_ioapic =3D -1, best_idx =3D -1; =20 - apic_printk(APIC_DEBUG, - "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", - bus, slot, pin); + apic_pr_debug("Querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", + bus, slot, pin); if (test_bit(bus, mp_bus_not_pci)) { - apic_printk(APIC_VERBOSE, - "PCI BIOS passed nonexistent PCI bus %d!\n", bus); + apic_pr_verbose("PCI BIOS passed nonexistent PCI bus %d!\n", bus); return -1; } =20 @@ -1173,17 +1162,16 @@ static void __init setup_IO_APIC_irqs(vo unsigned int ioapic, pin; int idx; =20 - apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); + apic_pr_verbose("Init IO_APIC IRQs\n"); =20 for_each_ioapic_pin(ioapic, pin) { idx =3D find_irq_entry(ioapic, pin, mp_INT); - if (idx < 0) - apic_printk(APIC_VERBOSE, - KERN_DEBUG " apic %d pin %d not connected\n", - mpc_ioapic_id(ioapic), pin); - else - pin_2_irq(idx, ioapic, pin, - ioapic ? 0 : IOAPIC_MAP_ALLOC); + if (idx < 0) { + apic_pr_verbose("apic %d pin %d not connected\n", + mpc_ioapic_id(ioapic), pin); + } else { + pin_2_irq(idx, ioapic, pin, ioapic ? 0 : IOAPIC_MAP_ALLOC); + } } } =20 @@ -1359,29 +1347,24 @@ void __init enable_IO_APIC(void) i8259_apic =3D find_isa_irq_apic(0, mp_ExtINT); /* Trust the MP table if nothing is setup in the hardware */ if ((ioapic_i8259.pin =3D=3D -1) && (i8259_pin >=3D 0)) { - printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP tab= le\n"); + pr_warn("ExtINT not setup in hardware but reported by MP table\n"); ioapic_i8259.pin =3D i8259_pin; ioapic_i8259.apic =3D i8259_apic; } /* Complain if the MP table and the hardware disagree */ if (((ioapic_i8259.apic !=3D i8259_apic) || (ioapic_i8259.pin !=3D i8259_= pin)) && - (i8259_pin >=3D 0) && (ioapic_i8259.pin >=3D 0)) - { - printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); - } + (i8259_pin >=3D 0) && (ioapic_i8259.pin >=3D 0)) + pr_warn("ExtINT in hardware and MP table differ\n"); =20 - /* - * Do not trust the IO-APIC being empty at bootup - */ + /* Do not trust the IO-APIC being empty at bootup */ clear_IO_APIC(); } =20 void native_restore_boot_irq_mode(void) { /* - * If the i8259 is routed through an IOAPIC - * Put that IOAPIC in virtual wire mode - * so legacy interrupts can be delivered. + * If the i8259 is routed through an IOAPIC Put that IOAPIC in + * virtual wire mode so legacy interrupts can be delivered. */ if (ioapic_i8259.pin !=3D -1) { struct IO_APIC_route_entry entry; @@ -1469,8 +1452,8 @@ static void __init setup_ioapic_ids_from set_bit(i, phys_id_present_map); ioapics[ioapic_idx].mp_config.apicid =3D i; } else { - apic_printk(APIC_VERBOSE, "Setting %d in the phys_id_present_map\n", - mpc_ioapic_id(ioapic_idx)); + apic_pr_verbose("Setting %d in the phys_id_present_map\n", + mpc_ioapic_id(ioapic_idx)); set_bit(mpc_ioapic_id(ioapic_idx), phys_id_present_map); } =20 @@ -1491,9 +1474,8 @@ static void __init setup_ioapic_ids_from if (mpc_ioapic_id(ioapic_idx) =3D=3D reg_00.bits.ID) continue; =20 - apic_printk(APIC_VERBOSE, KERN_INFO - "...changing IO-APIC physical APIC ID to %d ...", - mpc_ioapic_id(ioapic_idx)); + apic_pr_verbose("...changing IO-APIC physical APIC ID to %d ...", + mpc_ioapic_id(ioapic_idx)); =20 reg_00.bits.ID =3D mpc_ioapic_id(ioapic_idx); scoped_guard (raw_spinlock_irqsave, &ioapic_lock) { @@ -1504,7 +1486,7 @@ static void __init setup_ioapic_ids_from if (reg_00.bits.ID !=3D mpc_ioapic_id(ioapic_idx)) pr_cont("could not set ID!\n"); else - apic_printk(APIC_VERBOSE, " ok.\n"); + apic_pr_verbose(" ok.\n"); } } =20 @@ -2136,9 +2118,8 @@ static inline void __init check_timer(vo pin2 =3D ioapic_i8259.pin; apic2 =3D ioapic_i8259.apic; =20 - apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=3D0x%02X " - "apic1=3D%d pin1=3D%d apic2=3D%d pin2=3D%d\n", - cfg->vector, apic1, pin1, apic2, pin2); + pr_info("..TIMER: vector=3D0x%02X apic1=3D%d pin1=3D%d apic2=3D%d pin2=3D= %d\n", + cfg->vector, apic1, pin1, apic2, pin2); =20 /* * Some BIOS writers are clueless and report the ExtINTA @@ -2182,13 +2163,10 @@ static inline void __init check_timer(vo panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-API= C"); clear_IO_APIC_pin(apic1, pin1); if (!no_pin1) - apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " - "8254 timer not connected to IO-APIC\n"); + pr_err("..MP-BIOS bug: 8254 timer not connected to IO-APIC\n"); =20 - apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " - "(IRQ0) through the 8259A ...\n"); - apic_printk(APIC_QUIET, KERN_INFO - "..... (found apic %d pin %d) ...\n", apic2, pin2); + pr_info("...trying to set up timer (IRQ0) through the 8259A ...\n"); + pr_info("..... (found apic %d pin %d) ...\n", apic2, pin2); /* * legacy devices should be connected to IO APIC #0 */ @@ -2197,7 +2175,7 @@ static inline void __init check_timer(vo irq_domain_activate_irq(irq_data, false); legacy_pic->unmask(0); if (timer_irq_works()) { - apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); + pr_info("....... works.\n"); goto out; } /* @@ -2205,26 +2183,24 @@ static inline void __init check_timer(vo */ legacy_pic->mask(0); clear_IO_APIC_pin(apic2, pin2); - apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); + pr_info("....... failed.\n"); } =20 - apic_printk(APIC_QUIET, KERN_INFO - "...trying to set up timer as Virtual Wire IRQ...\n"); + pr_info("...trying to set up timer as Virtual Wire IRQ...\n"); =20 lapic_register_intr(0); apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ legacy_pic->unmask(0); =20 if (timer_irq_works()) { - apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); + pr_info("..... works.\n"); goto out; } legacy_pic->mask(0); apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); - apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); + pr_info("..... failed.\n"); =20 - apic_printk(APIC_QUIET, KERN_INFO - "...trying to set up timer as ExtINT IRQ...\n"); + pr_info("...trying to set up timer as ExtINT IRQ...\n"); =20 legacy_pic->init(0); legacy_pic->make_irq(0); @@ -2234,14 +2210,15 @@ static inline void __init check_timer(vo unlock_ExtINT_logic(); =20 if (timer_irq_works()) { - apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); + pr_info("..... works.\n"); goto out; } - apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); - if (apic_is_x2apic_enabled()) - apic_printk(APIC_QUIET, KERN_INFO - "Perhaps problem with the pre-enabled x2apic mode\n" - "Try booting with x2apic and interrupt-remapping disabled in the bi= os.\n"); + + pr_info("..... failed :\n"); + if (apic_is_x2apic_enabled()) { + pr_info("Perhaps problem with the pre-enabled x2apic mode\n" + "Try booting with x2apic and interrupt-remapping disabled in the bios.\= n"); + } panic("IO-APIC + timer doesn't work! Boot with apic=3Ddebug and send a " "report. Then try booting with the 'noapic' option.\n"); out: @@ -2339,7 +2316,7 @@ void __init setup_IO_APIC(void) =20 io_apic_irqs =3D nr_legacy_irqs() ? ~PIC_IRQS : ~0UL; =20 - apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); + apic_pr_verbose("ENABLING IO-APIC IRQs\n"); for_each_ioapic(ioapic) BUG_ON(mp_irqdomain_create(ioapic)); =20 @@ -2478,7 +2455,7 @@ static int io_apic_get_unique_id(int ioa } } =20 - apic_printk(APIC_VERBOSE, KERN_INFO "IOAPIC[%d]: Assigned apic_id %d\n", = ioapic, apic_id); + apic_pr_verbose("IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); =20 return apic_id; } @@ -2514,8 +2491,8 @@ static u8 io_apic_unique_id(int idx, u8 =20 new_id =3D reg_00.bits.ID; if (!test_bit(new_id, used)) { - apic_printk(APIC_VERBOSE, KERN_INFO "IOAPIC[%d]: Using reg apic_id %d in= stead of %d\n", - idx, new_id, id); + apic_pr_verbose("IOAPIC[%d]: Using reg apic_id %d instead of %d\n", + idx, new_id, id); return new_id; } =20 @@ -2614,9 +2591,7 @@ void __init io_apic_init_mappings(void) ioapic_phys =3D mpc_ioapic_addr(i); #ifdef CONFIG_X86_32 if (!ioapic_phys) { - printk(KERN_ERR - "WARNING: bogus zero IO-APIC " - "address found in MPTABLE, " + pr_err("WARNING: bogus zero IO-APIC address found in MPTABLE, " "disabling IO/APIC support!\n"); smp_found_config =3D 0; ioapic_is_disabled =3D true; @@ -2635,9 +2610,8 @@ void __init io_apic_init_mappings(void) ioapic_phys =3D __pa(ioapic_phys); } io_apic_set_fixmap(idx, ioapic_phys); - apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", - __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), - ioapic_phys); + apic_pr_verbose("mapped IOAPIC to %08lx (%08lx)\n", + __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), ioapic_phys); idx++; =20 ioapic_res->start =3D ioapic_phys; @@ -2648,13 +2622,12 @@ void __init io_apic_init_mappings(void) =20 void __init ioapic_insert_resources(void) { - int i; struct resource *r =3D ioapic_resources; + int i; =20 if (!r) { if (nr_ioapics > 0) - printk(KERN_ERR - "IO APIC resources couldn't be allocated.\n"); + pr_err("IO APIC resources couldn't be allocated.\n"); return; } =20 @@ -2674,11 +2647,12 @@ int mp_find_ioapic(u32 gsi) /* Find the IOAPIC that manages this GSI. */ for_each_ioapic(i) { struct mp_ioapic_gsi *gsi_cfg =3D mp_ioapic_gsi_routing(i); + if (gsi >=3D gsi_cfg->gsi_base && gsi <=3D gsi_cfg->gsi_end) return i; } =20 - printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); + pr_err("ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); return -1; } =20 @@ -2745,12 +2719,13 @@ int mp_register_ioapic(int id, u32 addre pr_warn("Bogus (zero) I/O APIC address found, skipping!\n"); return -EINVAL; } - for_each_ioapic(ioapic) + + for_each_ioapic(ioapic) { if (ioapics[ioapic].mp_config.apicaddr =3D=3D address) { - pr_warn("address 0x%x conflicts with IOAPIC%d\n", - address, ioapic); + pr_warn("address 0x%x conflicts with IOAPIC%d\n", address, ioapic); return -EEXIST; } + } =20 idx =3D find_free_ioapic_entry(); if (idx >=3D MAX_IO_APICS) { @@ -2785,8 +2760,7 @@ int mp_register_ioapic(int id, u32 addre (gsi_end >=3D gsi_cfg->gsi_base && gsi_end <=3D gsi_cfg->gsi_end)) { pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n", - gsi_base, gsi_end, - gsi_cfg->gsi_base, gsi_cfg->gsi_end); + gsi_base, gsi_end, gsi_cfg->gsi_base, gsi_cfg->gsi_end); clear_fixmap(FIX_IO_APIC_BASE_0 + idx); return -ENOSPC; } @@ -2820,8 +2794,7 @@ int mp_register_ioapic(int id, u32 addre ioapics[idx].nr_registers =3D entries; =20 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n", - idx, mpc_ioapic_id(idx), - mpc_ioapic_ver(idx), mpc_ioapic_addr(idx), + idx, mpc_ioapic_id(idx), mpc_ioapic_ver(idx), mpc_ioapic_addr(idx), gsi_cfg->gsi_base, gsi_cfg->gsi_end); =20 return 0; @@ -2850,8 +2823,7 @@ int mp_unregister_ioapic(u32 gsi_base) if (irq >=3D 0) { data =3D irq_get_chip_data(irq); if (data && data->count) { - pr_warn("pin%d on IOAPIC%d is still in use.\n", - pin, ioapic); + pr_warn("pin%d on IOAPIC%d is still in use.\n", pin, ioapic); return -EBUSY; } } @@ -2968,10 +2940,8 @@ int mp_irqdomain_alloc(struct irq_domain legacy_pic->mask(virq); local_irq_restore(flags); =20 - apic_printk(APIC_VERBOSE, KERN_DEBUG - "IOAPIC[%d]: Preconfigured routing entry (%d-%d -> IRQ %d Level:%i A= ctiveLow:%i)\n", - ioapic, mpc_ioapic_id(ioapic), pin, virq, - data->is_level, data->active_low); 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dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ihoDIcVy" Message-ID: <20240802155440.714763708@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1722615343; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=/AChwy4D2Z7ZJmgJ7d3iZD2+yd7etU8zolVSlXE4sZg=; b=Q+sW0RFblTFhYmwXU5vE6tteQFOFaVHhkWqrDJwdXDtDC/0V6uOJ2Z2ggiJ2KSOEsvUO8q sZqKDBhsc9c47IlbiQXChO5M+l+NjPJHYPuPWw8tm64gkUekOo7wJ+5gb7aL9FQ15C+T7F VOWUKKjEa2Q4ZTGKgIF4RN90JpJoT+N18FLqXo00fsctbambpBcdZY2RYKAKmU/2B+WJo0 upiEb/MrR70rh6FISl87KkEN3pyoiD0vRTOxKrzOhxhrk1hHG1P0LAJD3boptIPA5+SRpt Hcn8URFa9t8818DByTTA/hc/AYUKeBZnpFx65/Ap4xCDQ8EhCCls67Ok8w9ERA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1722615343; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=/AChwy4D2Z7ZJmgJ7d3iZD2+yd7etU8zolVSlXE4sZg=; b=ihoDIcVywzYbsAb9J0iWNHLA9iMJNnblQtcPalrVRSmJlLc/11rAvMBQRLDM+ZMeityRkO fQyvkuv9kOrEowCA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org Subject: [patch 08/15] x86/ioapic: Cleanup guarded debug printk()s References: <20240802155038.556977544@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Fri, 2 Aug 2024 18:15:43 +0200 (CEST) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Cleanup the APIC printk()s which are inside of a apic verbosity guarded region by using apic_dbg() for the KERN_DEBUG level prints. Signed-off-by: Thomas Gleixner Tested-by: Breno Leitao --- arch/x86/kernel/apic/io_apic.c | 67 +++++++++++++++++-------------------= ----- 1 file changed, 29 insertions(+), 38 deletions(-) --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -1186,26 +1186,21 @@ static void io_apic_print_entries(unsign char buf[256]; int i; =20 - printk(KERN_DEBUG "IOAPIC %d:\n", apic); + apic_dbg("IOAPIC %d:\n", apic); for (i =3D 0; i <=3D nr_entries; i++) { entry =3D ioapic_read_entry(apic, i); - snprintf(buf, sizeof(buf), - " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)", - i, - entry.masked ? "disabled" : "enabled ", + snprintf(buf, sizeof(buf)," pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1= d)", + i, entry.masked ? "disabled" : "enabled ", entry.is_level ? "level" : "edge ", entry.active_low ? "low " : "high", entry.vector, entry.irr, entry.delivery_status); if (entry.ir_format) { - printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n", - buf, - (entry.ir_index_15 << 15) | entry.ir_index_0_14, - entry.ir_zero); + apic_dbg("%s, remapped, I(%04X), Z(%X)\n", buf, + (entry.ir_index_15 << 15) | entry.ir_index_0_14, entry.ir_zero); } else { - printk(KERN_DEBUG "%s, %s, D(%02X%02X), M(%1d)\n", buf, - entry.dest_mode_logical ? "logical " : "physical", - entry.virt_destid_8_14, entry.destid_0_7, - entry.delivery_mode); + apic_dbg("%s, %s, D(%02X%02X), M(%1d)\n", buf, + entry.dest_mode_logical ? "logical " : "physic al", + entry.virt_destid_8_14, entry.destid_0_7, entry.delivery_mode); } } } @@ -1226,19 +1221,15 @@ static void __init print_IO_APIC(int ioa reg_03.raw =3D io_apic_read(ioapic_idx, 3); } =20 - printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx)); - printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); - printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID= ); - printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.deliver= y_type); - printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); - - printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); - printk(KERN_DEBUG "....... : max redirection entries: %02X\n", - reg_01.bits.entries); - - printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); - printk(KERN_DEBUG "....... : IO APIC version: %02X\n", - reg_01.bits.version); + apic_dbg("IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx)); + apic_dbg(".... register #00: %08X\n", reg_00.raw); + apic_dbg("....... : physical APIC id: %02X\n", reg_00.bits.ID); + apic_dbg("....... : Delivery Type: %X\n", reg_00.bits.delivery_type); + apic_dbg("....... : LTS : %X\n", reg_00.bits.LTS); + apic_dbg(".... register #01: %08X\n", *(int *)®_01); + apic_dbg("....... : max redirection entries: %02X\n",reg_01.bits.entr= ies); + apic_dbg("....... : PRQ implemented: %X\n", reg_01.bits.PRQ); + apic_dbg("....... : IO APIC version: %02X\n", reg_01.bits.version); =20 /* * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, @@ -1246,8 +1237,8 @@ static void __init print_IO_APIC(int ioa * value, so ignore it if reg_02 =3D=3D reg_01. */ if (reg_01.bits.version >=3D 0x10 && reg_02.raw !=3D reg_01.raw) { - printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); - printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbit= ration); + apic_dbg(".... register #02: %08X\n", reg_02.raw); + apic_dbg("....... : arbitration: %02X\n", reg_02.bits.arbitration); } =20 /* @@ -1257,11 +1248,11 @@ static void __init print_IO_APIC(int ioa */ if (reg_01.bits.version >=3D 0x20 && reg_03.raw !=3D reg_02.raw && reg_03.raw !=3D reg_01.raw) { - printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); - printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT= ); + apic_dbg(".... register #03: %08X\n", reg_03.raw); + apic_dbg("....... : Boot DT : %X\n", reg_03.bits.boot_DT); } =20 - printk(KERN_DEBUG ".... IRQ redirection table:\n"); + apic_dbg(".... IRQ redirection table:\n"); io_apic_print_entries(ioapic_idx, reg_01.bits.entries); } =20 @@ -1270,11 +1261,11 @@ void __init print_IO_APICs(void) int ioapic_idx; unsigned int irq; =20 - printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); - for_each_ioapic(ioapic_idx) - printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", - mpc_ioapic_id(ioapic_idx), - ioapics[ioapic_idx].nr_registers); + apic_dbg("number of MP IRQ sources: %d.\n", mp_irq_entries); + for_each_ioapic(ioapic_idx) { + apic_dbg("number of IO-APIC #%d registers: %d.\n", + mpc_ioapic_id(ioapic_idx), ioapics[ioapic_idx].nr_registers); + } =20 /* * We are a bit conservative about what we expect. We have to @@ -1285,7 +1276,7 @@ void __init print_IO_APICs(void) for_each_ioapic(ioapic_idx) print_IO_APIC(ioapic_idx); =20 - printk(KERN_DEBUG "IRQ to pin mappings:\n"); + apic_dbg("IRQ to pin mappings:\n"); for_each_active_irq(irq) { struct irq_pin_list *entry; struct irq_chip *chip; @@ -1300,7 +1291,7 @@ void __init print_IO_APICs(void) if (list_empty(&data->irq_2_pin)) continue; =20 - printk(KERN_DEBUG "IRQ%d ", irq); + apic_dbg("IRQ%d ", irq); for_each_irq_pin(entry, data->irq_2_pin) pr_cont("-> %d:%d", entry->apic, entry->pin); pr_cont("\n"); From nobody Sun Feb 8 01:52:30 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B226166F03 for ; Fri, 2 Aug 2024 16:15:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722615348; cv=none; b=udC4jZYK0/beZNglDGNpih0QASh1lZjgx0MoqqsR8wOd5HIkoafvB7QobEEKWoBnPJIUpOqhB4AH1vc2VVjTzwONCQcuOpvBM7GurqhcPZmvD9HULtBzKbXfW1oKrISnJC0U/WqsPj4SP+iRNPKZZH18ggY0kTpbkIH3SKpx9L0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722615348; c=relaxed/simple; bh=joGtQ+2N69Ik6xvxIoZy2SV0eRi8wasUBBpnChs/kok=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=hWpZS6Bv0Q5FQB13/nOWcqVtIva1O2RFPwmHY2xMFFNustVjHIKvq4B+T76oVzU+mVAU0QmXnTXlhexNANC/hEjshiZ0RG3jQPrj6BuU//0TxlW66XahOSCiDuSSc9QBNxe2wK98uHzyYFkxeung9wBL8A0LB3z5Ym0cHe4JMjQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Y6sFIyKb; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=yDcRcizV; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Y6sFIyKb"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="yDcRcizV" Message-ID: <20240802155440.779537108@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1722615344; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=2ttF1MAUDY4YRNHsjpOQQVG3OtWwhiDniK/3/J3rcqM=; b=Y6sFIyKbWefT0fA1xukJ1KPLFso7xKxl09qyqAYhT8Ms1GDnnfiwGWAZZlTg9WGag9uKuz Fh9jofTDcDGBIFA6A6xe5v6CwkJx9Sx3NbArIoKpMYrb3PArSNwAf96W/EZFlCiCQanM+5 PgJz0HySsCGQnlgkfBatpHku7M3DgWmi6LK34/BuqyD1NcNYDmUGZLE1dOlsPOwdQesBAL 5vlXsotMQeX9M6YuoyrIWRRl/EDPbqF5Q3fDStkWWJzZyM3vCMobFJOm5R4rgb5TE2cgpi oTOCAr/z4HcFjRDWtpN2ZBAlb+LGO8fzJ/8NRgYpnJPAgEtoLEtPNOuVL/rAFQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1722615344; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=2ttF1MAUDY4YRNHsjpOQQVG3OtWwhiDniK/3/J3rcqM=; b=yDcRcizV/WxLOvQ/Dda5Dk/uLCarRdqgUES5f5XVmCAgi5LagdmUUS9I0g6W5fKR6RpZDb p3Ogaffzr3wmFJCQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org Subject: [patch 09/15] x86/mpparse: Cleanup apic_printk()s References: <20240802155038.556977544@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Fri, 2 Aug 2024 18:15:44 +0200 (CEST) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use the new apic_pr_verbose() helper. Signed-off-by: Thomas Gleixner Tested-by: Breno Leitao --- arch/x86/kernel/mpparse.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) --- a/arch/x86/kernel/mpparse.c +++ b/arch/x86/kernel/mpparse.c @@ -68,7 +68,7 @@ static void __init mpc_oem_bus_info(stru { memcpy(str, m->bustype, 6); str[6] =3D 0; - apic_printk(APIC_VERBOSE, "Bus #%d is %s\n", m->busid, str); + apic_pr_verbose("Bus #%d is %s\n", m->busid, str); } =20 static void __init MP_bus_info(struct mpc_bus *m) @@ -417,7 +417,7 @@ static unsigned long __init get_mpc_size mpc =3D early_memremap(physptr, PAGE_SIZE); size =3D mpc->length; early_memunmap(mpc, PAGE_SIZE); - apic_printk(APIC_VERBOSE, " mpc: %lx-%lx\n", physptr, physptr + size); + apic_pr_verbose(" mpc: %lx-%lx\n", physptr, physptr + size); =20 return size; } @@ -560,7 +560,7 @@ static int __init smp_scan_config(unsign struct mpf_intel *mpf; int ret =3D 0; =20 - apic_printk(APIC_VERBOSE, "Scan for SMP in [mem %#010lx-%#010lx]\n", + apic_pr_verbose("Scan for SMP in [mem %#010lx-%#010lx]\n", base, base + length - 1); BUILD_BUG_ON(sizeof(*mpf) !=3D 16); =20 @@ -683,13 +683,13 @@ static void __init check_irq_src(struct { int i; =20 - apic_printk(APIC_VERBOSE, "OLD "); + apic_pr_verbose("OLD "); print_mp_irq_info(m); =20 i =3D get_MP_intsrc_index(m); if (i > 0) { memcpy(m, &mp_irqs[i], sizeof(*m)); - apic_printk(APIC_VERBOSE, "NEW "); + apic_pr_verbose("NEW "); print_mp_irq_info(&mp_irqs[i]); return; } @@ -772,7 +772,7 @@ static int __init replace_intsrc_all(st continue; =20 if (nr_m_spare > 0) { - apic_printk(APIC_VERBOSE, "*NEW* found\n"); + apic_pr_verbose("*NEW* found\n"); nr_m_spare--; memcpy(m_spare[nr_m_spare], &mp_irqs[i], sizeof(mp_irqs[i])); m_spare[nr_m_spare] =3D NULL; From nobody Sun Feb 8 01:52:30 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A43DE166F2B for ; Fri, 2 Aug 2024 16:15:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1722615346; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=NvWyjYqggPv9q7d5bTQ1InFLBiONgQR2ak2ONK1XkAI=; b=NoGZhqoi0yqQvvecCQI1ccNwhPuv7sf333AuPOurG4RQPxM8w/cE+PxJg0x/BXnVdFshaK y9+MfUj7sfINYCAw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org Subject: [patch 10/15] iommu/vt-d: Cleanup apic_printk() References: <20240802155038.556977544@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Fri, 2 Aug 2024 18:15:45 +0200 (CEST) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use the new apic_pr_verbose() helper. Signed-off-by: Thomas Gleixner Tested-by: Breno Leitao --- drivers/iommu/intel/irq_remapping.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -1352,12 +1352,11 @@ static void intel_irq_remapping_prepare_ case X86_IRQ_ALLOC_TYPE_IOAPIC: /* Set source-id of interrupt request */ set_ioapic_sid(irte, info->devid); - apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d F= PD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:= %02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n", - info->devid, irte->present, irte->fpd, - irte->dst_mode, irte->redir_hint, - irte->trigger_mode, irte->dlvry_mode, - irte->avail, irte->vector, irte->dest_id, - irte->sid, irte->sq, irte->svt); + apic_pr_verbose("IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Red= ir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%0= 4X SQ:%X SVT:%X)\n", + info->devid, irte->present, irte->fpd, irte->dst_mode, + irte->redir_hint, irte->trigger_mode, irte->dlvry_mode, + irte->avail, irte->vector, irte->dest_id, irte->sid, + irte->sq, irte->svt); sub_handle =3D info->ioapic.pin; break; case X86_IRQ_ALLOC_TYPE_HPET: From nobody Sun Feb 8 01:52:30 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06D751537CB for ; Fri, 2 Aug 2024 16:15:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722615350; cv=none; b=N7uf9BKD7DR7FAsooP5Y7/pugzp1kiZhIwdFwPh++eKbg+fozxQiRA6NpHbY8xekxxdSzkB406PlqzduaXXu5scul0D37LAJ4FDJCTPGehDopZZmoxS/VOR7eYgLHSXEDiPZygccs+i6iDsFzysTdINmZIjlMwzPyBj/U+VQnCU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722615350; c=relaxed/simple; bh=Fs0K/UjwZhMJSjeEiZJnFQQy1pNOEUGEst5p68HK7JA=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=rX0EcpWQDv0t+Dr5YuI71Ue6UNCpxHkJxHeg0+apyOOy5NsWPzjzxCWCFUG40UnT8mYdbQfRWy04zKC9tDLK7f1NDBqo6FtFAh7KAnbwlgYAQ1LVlngoErMyBW8TCwVYdafFX2kGuszcmDCEotcL77IgrJMYBhhfrZgz2UGwV24= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=rt18SADs; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=N8ZZeT6X; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="rt18SADs"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="N8ZZeT6X" Message-ID: <20240802155440.906636514@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1722615347; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=17mnREW+bYg81keMy3JfytNa+W5aLA1S7jMZdqHm8g0=; b=rt18SADsyo/bPuxqk01T3JazHQHCpC0gTP/4GtYqWrG7X0gWcedj+5OhQ06yCoNZG5x4G8 zmaGUya2Zxcr6i7ACdN2PcPLYj4mwa8qY+0W/cFvoGVcWkC5rXUV7ejLEZ6KmHwQk9tw7P yS+rw/O1/hJIiEJrbOoVruHHzgXm5FOUE4Ybm4+lgT9B6VL21TYPXLDTj5yJREFgiHymZH 0oifYjdg3vrKB+QjXqGPJdCpa+sdewMUcnV/b7ugSmCJnJ6/3bkTCBvefFEsd9+MRJ6kZ7 WFXjuG1fH0qLMkxet1prhVvufFi4mMBWoXy+qtJcl78ws8NlWrSUqGYkn6DOHg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1722615347; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=17mnREW+bYg81keMy3JfytNa+W5aLA1S7jMZdqHm8g0=; b=N8ZZeT6Xs8PckH1wOd57k6AuGsR5NjEWYXIHQV3/l/5UuFWnSSmtWqtXNbrw7Qdu8hCv/A pV0O5ZP1yVxFFNBg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org Subject: [patch 11/15] x86/ioapic: Move replace_pin_at_irq_node() to the call site References: <20240802155038.556977544@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Fri, 2 Aug 2024 18:15:47 +0200 (CEST) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It's only used by check_timer(). Signed-off-by: Thomas Gleixner Tested-by: Breno Leitao --- arch/x86/kernel/apic/io_apic.c | 40 ++++++++++++++++++------------------= ---- 1 file changed, 18 insertions(+), 22 deletions(-) --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -370,28 +370,6 @@ static void __remove_pin_from_irq(struct } } =20 -/* - * Reroute an IRQ to a different pin. - */ -static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int = node, - int oldapic, int oldpin, - int newapic, int newpin) -{ - struct irq_pin_list *entry; - - for_each_irq_pin(entry, data->irq_2_pin) { - if (entry->apic =3D=3D oldapic && entry->pin =3D=3D oldpin) { - entry->apic =3D newapic; - entry->pin =3D newpin; - /* every one is different, right? */ - return; - } - } - - /* old apic/pin didn't exist, so just add new ones */ - add_pin_to_irq_node(data, node, newapic, newpin); -} - static void io_apic_modify_irq(struct mp_chip_data *data, bool masked, void (*final)(struct irq_pin_list *entry)) { @@ -2069,6 +2047,24 @@ static int __init mp_alloc_timer_irq(int return irq; } =20 +static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int = node, + int oldapic, int oldpin, + int newapic, int newpin) +{ + struct irq_pin_list *entry; + + for_each_irq_pin(entry, data->irq_2_pin) { + if (entry->apic =3D=3D oldapic && entry->pin =3D=3D oldpin) { + entry->apic =3D newapic; + entry->pin =3D newpin; + return; + } + } + + /* Old apic/pin didn't exist, so just add a new one */ + add_pin_to_irq_node(data, node, newapic, newpin); +} + /* * This code may look a bit paranoid, but it's supposed to cooperate with * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ From nobody Sun Feb 8 01:52:31 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48C251E287F for ; Fri, 2 Aug 2024 16:15:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722615352; cv=none; b=czoIvnGEdu8GNV5td/UwRxzFGpzR39Rj7auU6y5lzTP+1wByNLlaQmVNHF+XTbFKdjClnr7fgHoIlMJx4IaSZeLrUJp3C0055nJd/1LPbrospLLPTxDE/Bz3W25tulWzaglSBltqHJ+I4zBqUspOXTfp13dvWlhMwdVkN6qZ9Ms= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722615352; c=relaxed/simple; bh=ApuFP7hUkB4GG2CDVVRZNYbtp2I1Rn1Ost0KRvUQ9vQ=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=DxarIfCsYqlhYrPs1u3E7IHO5ORGkulbqwxMXKW4JbfvGKKTkqMo2e+T6GMaOQvSs7nHQ/IYSQbKqqg7dox8bkSJhAxzAXlk3VMP5V8cCYqelLH/GqNwNpp+IlqF+4C6DuQ9CA+tIpJW+Ek5UEOuX4GLDDqiMk2vvr9aoC+L6xg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=IZPHPvdj; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=cpmGYs0k; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="IZPHPvdj"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="cpmGYs0k" Message-ID: <20240802155440.969619978@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1722615348; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=xqjWzalHB8Wp0VvFcAWCmZ5DG9g95Nn4RtzOchAdDo8=; b=IZPHPvdj2qjXXhnizchH12MLk8SVBYIJFw9FjEIxTca+9VLOqrIRl29YOzoP0a6gyyBV60 5PfRSYiApHp4JBRfJ1GHNrJl35vjGZotd2HuwNiS/B9D25P/Juf/n2wxnNZlRnj+N3t1dX 2TX2AHP7+wmWsUrN09jrBge5poJMPRYjSpCJ/KeVlf1/29n3MoLP8pFqnTRZSlAWko0BDl CvNKVhVgpu14r1fd5jwD7fwlcOdbT2u8PeN8EzKL1tnp6YCtzsLppoYjopFJptjsRcDj7+ h5DUx/dQpJQdzVuCN5WmR2tVk7q1VAFVEK3tacJ+pcftGfMgnlmASN2o890xeA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1722615348; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=xqjWzalHB8Wp0VvFcAWCmZ5DG9g95Nn4RtzOchAdDo8=; b=cpmGYs0kGPvNrf5ipO8pbfpDUHqeGBr6h3OGcaEVZGEM9ddpNdcTkivSBqENUhhicfA7oP pOe90vlYvGMBEFCA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org Subject: [patch 12/15] x86/ioapic: Cleanup comments References: <20240802155038.556977544@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Fri, 2 Aug 2024 18:15:48 +0200 (CEST) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use proper comment styles and shrink comments to their scope where applicable. Signed-off-by: Thomas Gleixner Tested-by: Breno Leitao --- arch/x86/kernel/apic/io_apic.c | 86 +++++++++++++++++-------------------= ----- 1 file changed, 37 insertions(+), 49 deletions(-) --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -384,12 +384,12 @@ static void io_apic_modify_irq(struct mp } } =20 +/* + * Synchronize the IO-APIC and the CPU by doing a dummy read from the + * IO-APIC + */ static void io_apic_sync(struct irq_pin_list *entry) { - /* - * Synchronize the IO-APIC and the CPU by doing - * a dummy read from the IO-APIC - */ struct io_apic __iomem *io_apic; =20 io_apic =3D io_apic_base(entry->apic); @@ -442,17 +442,13 @@ static void __eoi_ioapic_pin(int apic, i =20 entry =3D entry1 =3D __ioapic_read_entry(apic, pin); =20 - /* - * Mask the entry and change the trigger mode to edge. - */ + /* Mask the entry and change the trigger mode to edge. */ entry1.masked =3D true; entry1.is_level =3D false; =20 __ioapic_write_entry(apic, pin, entry1); =20 - /* - * Restore the previous level triggered entry. - */ + /* Restore the previous level triggered entry. */ __ioapic_write_entry(apic, pin, entry); } } @@ -1012,16 +1008,12 @@ static int pin_2_irq(int idx, int ioapic { u32 gsi =3D mp_pin_to_gsi(ioapic, pin); =20 - /* - * Debugging check, we are in big trouble if this message pops up! - */ + /* Debugging check, we are in big trouble if this message pops up! */ if (mp_irqs[idx].dstirq !=3D pin) pr_err("broken BIOS or MPTABLE parser, ayiee!!\n"); =20 #ifdef CONFIG_X86_32 - /* - * PCI IRQ command line redirection. Yes, limits are hardcoded. - */ + /* PCI IRQ command line redirection. Yes, limits are hardcoded. */ if ((pin >=3D 16) && (pin <=3D 23)) { if (pirq_entries[pin - 16] !=3D -1) { if (!pirq_entries[pin - 16]) { @@ -1296,8 +1288,9 @@ void __init enable_IO_APIC(void) /* See if any of the pins is in ExtINT mode */ struct IO_APIC_route_entry entry =3D ioapic_read_entry(apic, pin); =20 - /* If the interrupt line is enabled and in ExtInt mode - * I have found the pin where the i8259 is connected. + /* + * If the interrupt line is enabled and in ExtInt mode I + * have found the pin where the i8259 is connected. */ if (!entry.masked && entry.delivery_mode =3D=3D APIC_DELIVERY_MODE_EXTINT) { @@ -1307,8 +1300,11 @@ void __init enable_IO_APIC(void) } } found_i8259: - /* Look to see what if the MP table has reported the ExtINT */ - /* If we could not find the appropriate pin by looking at the ioapic + + /* + * Look to see what if the MP table has reported the ExtINT + * + * If we could not find the appropriate pin by looking at the ioapic * the i8259 probably is not connected the ioapic but give the * mptable a chance anyway. */ @@ -1348,9 +1344,7 @@ void native_restore_boot_irq_mode(void) entry.destid_0_7 =3D apic_id & 0xFF; entry.virt_destid_8_14 =3D apic_id >> 8; =20 - /* - * Add it to the IO-APIC irq-routing table: - */ + /* Add it to the IO-APIC irq-routing table */ ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); } =20 @@ -1427,8 +1421,8 @@ static void __init setup_ioapic_ids_from } =20 /* - * We need to adjust the IRQ routing table - * if the ID changed. + * We need to adjust the IRQ routing table if the ID + * changed. */ if (old_id !=3D mpc_ioapic_id(ioapic_idx)) for (i =3D 0; i < mp_irq_entries; i++) @@ -1437,8 +1431,8 @@ static void __init setup_ioapic_ids_from =3D mpc_ioapic_id(ioapic_idx); =20 /* - * Update the ID register according to the right value - * from the MPC table if they are different. + * Update the ID register according to the right value from + * the MPC table if they are different. */ if (mpc_ioapic_id(ioapic_idx) =3D=3D reg_00.bits.ID) continue; @@ -1562,21 +1556,17 @@ static int __init timer_irq_works(void) * so we 'resend' these IRQs via IPIs, to the same CPU. It's much * better to do it this way as thus we do not have to be aware of * 'pending' interrupts in the IRQ path, except at this point. - */ -/* - * Edge triggered needs to resend any interrupt - * that was delayed but this is now handled in the device - * independent code. - */ - -/* - * Starting up a edge-triggered IO-APIC interrupt is - * nasty - we need to make sure that we get the edge. - * If it is already asserted for some reason, we need - * return 1 to indicate that is was pending. * - * This is not complete - we should be able to fake - * an edge even if it isn't on the 8259A... + * + * Edge triggered needs to resend any interrupt that was delayed but this + * is now handled in the device independent code. + * + * Starting up a edge-triggered IO-APIC interrupt is nasty - we need to + * make sure that we get the edge. If it is already asserted for some + * reason, we need return 1 to indicate that is was pending. + * + * This is not complete - we should be able to fake an edge even if it + * isn't on the 8259A... */ static unsigned int startup_ioapic_irq(struct irq_data *data) { @@ -1627,7 +1617,8 @@ static inline bool ioapic_prepare_move(s static inline void ioapic_finish_move(struct irq_data *data, bool moveit) { if (unlikely(moveit)) { - /* Only migrate the irq if the ack has been received. + /* + * Only migrate the irq if the ack has been received. * * On rare occasions the broadcast level triggered ack gets * delayed going to ioapics, and if we reprogram the @@ -1904,14 +1895,13 @@ static inline void init_IO_APIC_traps(vo cfg =3D irq_cfg(irq); if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { /* - * Hmm.. We don't have an entry for this, - * so default to an old-fashioned 8259 - * interrupt if we can.. + * Hmm.. We don't have an entry for this, so + * default to an old-fashioned 8259 interrupt if we + * can. Otherwise set the dummy interrupt chip. */ if (irq < nr_legacy_irqs()) legacy_pic->make_irq(irq); else - /* Strange. Oh, well.. */ irq_set_chip(irq, &no_irq_chip); } } @@ -2307,9 +2297,7 @@ void __init setup_IO_APIC(void) for_each_ioapic(ioapic) BUG_ON(mp_irqdomain_create(ioapic)); =20 - /* - * Set up IO-APIC IRQ routing. - */ + /* Set up IO-APIC IRQ routing. */ x86_init.mpparse.setup_ioapic_ids(); =20 sync_Arb_IDs(); From nobody Sun Feb 8 01:52:31 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72D652101B3 for ; Fri, 2 Aug 2024 16:15:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722615353; cv=none; b=sQ00QghZ3bdEs1kN8e/z11jFLed8jMtkGM3VszIfjhzhyxGQfi052CDoioMc917pGKOMWk40TIAUiMpA5qUHHBsHfFFJsYhIXk4udDy99I63BRqwD7+N/XpNB9XzhepPJXnbH7Uiah37RWYQla7M3xI8q717Ag0m3FzzvFTbTv8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722615353; c=relaxed/simple; bh=4joPjqYEQP1EZM/mKEFP/7OQQSP2kumvms7FfENrhiI=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=k5DLlKb11vuRcSKXlHLJoXRW0JVZOCQj3kCbFVWJb8QlQtrsXUaiHDrIchIfUUxMnjlRBG+p+UdLF02WlSZov+RWegIrN+N/Yvb+ZRda1XYNnWzWE3OOt87ju9MaFdNkVllmrc/3IJBdFZ8iZ51B3yNX74MdO0/M4C37jvNXpqE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=SuHgct+A; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ny5DpkZZ; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="SuHgct+A"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ny5DpkZZ" Message-ID: <20240802155441.032045616@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1722615349; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Dhes1tKIxTk1JJs3+ZEKAxniIS8S9bZ/SOxPoiAxujU=; b=SuHgct+AllcbTQrVfvZHWvWkxazys3y+/DqLm8CNc4SsPA9lAvzolwybv/XdmyirOsLC5N 72a71oPLr2/zr+ZwsrDXzJSkw6ugwzwkp+EqKDmXmEmoFTKDuCCysYhZdIXXVab7d2gOjK KDh6ORu7q6NXWp6llM5GNM+RbNPEJKob8hEYYgy21oBmgnsq+MZ975cVeyrfsqxHXS7EDL Y/XLS8rDwROasjCZwYFd+lgwgqB3PvfmJdS/OZCOMehZWk6+7AxBbL3XCtvfamGOSfdVxq T6V0/GmmLhvGt/CFwpWV/xyudR135yYcH8y7oV4VMzHOI5bgoj41r/Y5kkWoaw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1722615349; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Dhes1tKIxTk1JJs3+ZEKAxniIS8S9bZ/SOxPoiAxujU=; b=ny5DpkZZlOzC1zv9wFla0Frd7g5caUvIOLfx+uTVKNccrHQj3UECxu60uhPYNfbTcgDgWC AmIO/FP/1mZ/xCBA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org Subject: [patch 13/15] x86/ioapic: Cleanup bracket usage References: <20240802155038.556977544@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Fri, 2 Aug 2024 18:15:49 +0200 (CEST) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add brackets around if/for constructs as required by coding style or remove pointless line breaks to make it true single line statements which do not require brackets. Signed-off-by: Thomas Gleixner Tested-by: Breno Leitao --- arch/x86/kernel/apic/io_apic.c | 34 ++++++++++++++++++---------------- 1 file changed, 18 insertions(+), 16 deletions(-) --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -362,12 +362,13 @@ static void __remove_pin_from_irq(struct { struct irq_pin_list *tmp, *entry; =20 - list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list) + list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list) { if (entry->apic =3D=3D apic && entry->pin =3D=3D pin) { list_del(&entry->list); kfree(entry); return; } + } } =20 static void io_apic_modify_irq(struct mp_chip_data *data, bool masked, @@ -562,8 +563,7 @@ int save_ioapic_entries(void) } =20 for_each_pin(apic, pin) - ioapics[apic].saved_registers[pin] =3D - ioapic_read_entry(apic, pin); + ioapics[apic].saved_registers[pin] =3D ioapic_read_entry(apic, pin); } =20 return err; @@ -604,8 +604,7 @@ int restore_ioapic_entries(void) continue; =20 for_each_pin(apic, pin) - ioapic_write_entry(apic, pin, - ioapics[apic].saved_registers[pin]); + ioapic_write_entry(apic, pin, ioapics[apic].saved_registers[pin]); } return 0; } @@ -617,12 +616,13 @@ static int find_irq_entry(int ioapic_idx { int i; =20 - for (i =3D 0; i < mp_irq_entries; i++) + for (i =3D 0; i < mp_irq_entries; i++) { if (mp_irqs[i].irqtype =3D=3D type && (mp_irqs[i].dstapic =3D=3D mpc_ioapic_id(ioapic_idx) || mp_irqs[i].dstapic =3D=3D MP_APIC_ALL) && mp_irqs[i].dstirq =3D=3D pin) return i; + } =20 return -1; } @@ -662,9 +662,10 @@ static int __init find_isa_irq_apic(int if (i < mp_irq_entries) { int ioapic_idx; =20 - for_each_ioapic(ioapic_idx) + for_each_ioapic(ioapic_idx) { if (mpc_ioapic_id(ioapic_idx) =3D=3D mp_irqs[i].dstapic) return ioapic_idx; + } } =20 return -1; @@ -1424,11 +1425,12 @@ static void __init setup_ioapic_ids_from * We need to adjust the IRQ routing table if the ID * changed. */ - if (old_id !=3D mpc_ioapic_id(ioapic_idx)) - for (i =3D 0; i < mp_irq_entries; i++) + if (old_id !=3D mpc_ioapic_id(ioapic_idx)) { + for (i =3D 0; i < mp_irq_entries; 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Signed-off-by: Thomas Gleixner Tested-by: Breno Leitao --- arch/x86/kernel/apic/io_apic.c | 55 +++++++++++++-----------------------= ----- 1 file changed, 18 insertions(+), 37 deletions(-) --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -637,10 +637,8 @@ static int __init find_isa_irq_pin(int i for (i =3D 0; i < mp_irq_entries; i++) { int lbus =3D mp_irqs[i].srcbus; =20 - if (test_bit(lbus, mp_bus_not_pci) && - (mp_irqs[i].irqtype =3D=3D type) && + if (test_bit(lbus, mp_bus_not_pci) && (mp_irqs[i].irqtype =3D=3D type) && (mp_irqs[i].srcbusirq =3D=3D irq)) - return mp_irqs[i].dstirq; } return -1; @@ -653,8 +651,7 @@ static int __init find_isa_irq_apic(int for (i =3D 0; i < mp_irq_entries; i++) { int lbus =3D mp_irqs[i].srcbus; =20 - if (test_bit(lbus, mp_bus_not_pci) && - (mp_irqs[i].irqtype =3D=3D type) && + if (test_bit(lbus, mp_bus_not_pci) && (mp_irqs[i].irqtype =3D=3D type) && (mp_irqs[i].srcbusirq =3D=3D irq)) break; } @@ -907,8 +904,7 @@ static int alloc_irq_from_domain(struct return -1; } =20 - return __irq_domain_alloc_irqs(domain, irq, 1, - ioapic_alloc_attr_node(info), + return __irq_domain_alloc_irqs(domain, irq, 1, ioapic_alloc_attr_node(inf= o), info, legacy, NULL); } =20 @@ -922,13 +918,12 @@ static int alloc_irq_from_domain(struct * PIRQs instead of reprogramming the interrupt routing logic. Thus there = may be * multiple pins sharing the same legacy IRQ number when ACPI is disabled. */ -static int alloc_isa_irq_from_domain(struct irq_domain *domain, - int irq, int ioapic, int pin, +static int alloc_isa_irq_from_domain(struct irq_domain *domain, int irq, i= nt ioapic, int pin, struct irq_alloc_info *info) { - struct mp_chip_data *data; struct irq_data *irq_data =3D irq_get_irq_data(irq); int node =3D ioapic_alloc_attr_node(info); + struct mp_chip_data *data; =20 /* * Legacy ISA IRQ has already been allocated, just add pin to @@ -942,8 +937,7 @@ static int alloc_isa_irq_from_domain(str return -ENOMEM; } else { info->flags |=3D X86_IRQ_ALLOC_LEGACY; - irq =3D __irq_domain_alloc_irqs(domain, irq, 1, node, info, true, - NULL); + irq =3D __irq_domain_alloc_irqs(domain, irq, 1, node, info, true, NULL); if (irq >=3D 0) { irq_data =3D irq_domain_get_irq_data(domain, irq); data =3D irq_data->chip_data; @@ -1121,8 +1115,7 @@ int IO_APIC_get_PCI_irq_vector(int bus, return -1; =20 out: - return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq, - IOAPIC_MAP_ALLOC); + return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq, IOAPIC_= MAP_ALLOC); } EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); =20 @@ -1293,14 +1286,12 @@ void __init enable_IO_APIC(void) * If the interrupt line is enabled and in ExtInt mode I * have found the pin where the i8259 is connected. */ - if (!entry.masked && - entry.delivery_mode =3D=3D APIC_DELIVERY_MODE_EXTINT) { + if (!entry.masked && entry.delivery_mode =3D=3D APIC_DELIVERY_MODE_EXTIN= T) { ioapic_i8259.apic =3D apic; ioapic_i8259.pin =3D pin; - goto found_i8259; + break; } } - found_i8259: =20 /* * Look to see what if the MP table has reported the ExtINT @@ -1496,8 +1487,7 @@ static void __init delay_with_tsc(void) do { rep_nop(); now =3D rdtsc(); - } while ((now - start) < 40000000000ULL / HZ && - time_before_eq(jiffies, end)); + } while ((now - start) < 40000000000ULL / HZ && time_before_eq(jiffies, e= nd)); } =20 static void __init delay_without_tsc(void) @@ -1912,20 +1902,17 @@ static inline void init_IO_APIC_traps(vo /* * The local APIC irq-chip implementation: */ - static void mask_lapic_irq(struct irq_data *data) { - unsigned long v; + unsigned long v =3D apic_read(APIC_LVT0); =20 - v =3D apic_read(APIC_LVT0); apic_write(APIC_LVT0, v | APIC_LVT_MASKED); } =20 static void unmask_lapic_irq(struct irq_data *data) { - unsigned long v; + unsigned long v =3D apic_read(APIC_LVT0); =20 - v =3D apic_read(APIC_LVT0); apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); } =20 @@ -1944,8 +1931,7 @@ static struct irq_chip lapic_chip __read static void lapic_register_intr(int irq) { irq_clear_status_flags(irq, IRQ_LEVEL); - irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, - "edge"); + irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, "edge"); } =20 /* @@ -2265,10 +2251,8 @@ static int mp_irqdomain_create(int ioapi return -ENOMEM; } =20 - if (cfg->type =3D=3D IOAPIC_DOMAIN_LEGACY || - cfg->type =3D=3D IOAPIC_DOMAIN_STRICT) - ioapic_dynirq_base =3D max(ioapic_dynirq_base, - gsi_cfg->gsi_end + 1); + if (cfg->type =3D=3D IOAPIC_DOMAIN_LEGACY || cfg->type =3D=3D IOAPIC_DOMA= IN_STRICT) + ioapic_dynirq_base =3D max(ioapic_dynirq_base, gsi_cfg->gsi_end + 1); =20 return 0; } @@ -2682,8 +2666,7 @@ static int find_free_ioapic_entry(void) * @gsi_base: base of GSI associated with the IOAPIC * @cfg: configuration information for the IOAPIC */ -int mp_register_ioapic(int id, u32 address, u32 gsi_base, - struct ioapic_domain_cfg *cfg) +int mp_register_ioapic(int id, u32 address, u32 gsi_base, struct ioapic_do= main_cfg *cfg) { bool hotplug =3D !!ioapic_initialized; struct mp_ioapic_gsi *gsi_cfg; @@ -2835,8 +2818,7 @@ static void mp_irqdomain_get_attr(u32 gs if (info && info->ioapic.valid) { data->is_level =3D info->ioapic.is_level; data->active_low =3D info->ioapic.active_low; - } else if (__acpi_get_override_irq(gsi, &data->is_level, - &data->active_low) < 0) { + } else if (__acpi_get_override_irq(gsi, &data->is_level, &data->active_lo= w) < 0) { /* PCI interrupts are always active low level triggered. */ data->is_level =3D true; data->active_low =3D true; @@ -2956,8 +2938,7 @@ void mp_irqdomain_deactivate(struct irq_ struct irq_data *irq_data) { /* It won't be called for IRQ with multiple IOAPIC pins associated */ - ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain), - (int)irq_data->hwirq); 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charset="utf-8" Add missing new lines and reorder variable definitions. Signed-off-by: Thomas Gleixner Tested-by: Breno Leitao --- arch/x86/kernel/apic/io_apic.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -264,12 +264,14 @@ static __attribute_const__ struct io_api static inline void io_apic_eoi(unsigned int apic, unsigned int vector) { struct io_apic __iomem *io_apic =3D io_apic_base(apic); + writel(vector, &io_apic->eoi); } =20 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg) { struct io_apic __iomem *io_apic =3D io_apic_base(apic); + writel(reg, &io_apic->index); return readl(&io_apic->data); } @@ -880,9 +882,9 @@ static bool mp_check_pin_attr(int irq, s static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u3= 2 gsi, struct irq_alloc_info *info) { + int type =3D ioapics[ioapic].irqdomain_cfg.type; bool legacy =3D false; int irq =3D -1; - int type =3D ioapics[ioapic].irqdomain_cfg.type; =20 switch (type) { case IOAPIC_DOMAIN_LEGACY: @@ -951,11 +953,11 @@ static int alloc_isa_irq_from_domain(str static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin, unsigned int flags, struct irq_alloc_info *info) { - int irq; - bool legacy =3D false; + struct irq_domain *domain =3D mp_ioapic_irqdomain(ioapic); struct irq_alloc_info tmp; struct mp_chip_data *data; - struct irq_domain *domain =3D mp_ioapic_irqdomain(ioapic); + bool legacy =3D false; + int irq; =20 if (!domain) return -ENOSYS; @@ -1269,8 +1271,7 @@ static struct { int pin, apic; } ioapic_ =20 void __init enable_IO_APIC(void) { - int i8259_apic, i8259_pin; - int apic, pin; + int i8259_apic, i8259_pin, apic, pin; =20 if (ioapic_is_disabled) nr_ioapics =3D 0; @@ -1943,9 +1944,9 @@ static void lapic_register_intr(int irq) */ static inline void __init unlock_ExtINT_logic(void) { - int apic, pin, i; - struct IO_APIC_route_entry entry0, entry1; unsigned char save_control, save_freq_select; + struct IO_APIC_route_entry entry0, entry1; + int apic, pin, i; u32 apic_id; =20 pin =3D find_isa_irq_pin(8, mp_INT); @@ -2211,11 +2212,11 @@ static inline void __init check_timer(vo =20 static int mp_irqdomain_create(int ioapic) { - struct irq_domain *parent; + struct mp_ioapic_gsi *gsi_cfg =3D mp_ioapic_gsi_routing(ioapic); int hwirqs =3D mp_ioapic_pin_count(ioapic); struct ioapic *ip =3D &ioapics[ioapic]; struct ioapic_domain_cfg *cfg =3D &ip->irqdomain_cfg; - struct mp_ioapic_gsi *gsi_cfg =3D mp_ioapic_gsi_routing(ioapic); + struct irq_domain *parent; struct fwnode_handle *fn; struct irq_fwspec fwspec; =20 @@ -2491,8 +2492,8 @@ static struct resource *ioapic_resources =20 static struct resource * __init ioapic_setup_resources(void) { - unsigned long n; struct resource *res; + unsigned long n; char *mem; int i;