From nobody Mon Feb 9 10:47:53 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9FB81D54EB; Fri, 2 Aug 2024 09:06:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722589579; cv=none; b=nVHSRihhJE6tHhePF7HoslmbxBpGKFKliAFB932cpzmBmKvXBg2aSAAb86US3L2SR50u7mE9hJnOIOw6fXJPttjWrRmEfnzLsRkNYUYQL0z9K/gQ0IDS7gSxt9fFkzZxm+v8t8JcYaLTjGny8+spwXfivQHtn/hvwSEZoQkkRsE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722589579; c=relaxed/simple; bh=v8UC+BcyUjcKe1V7WwSHfVEphUcMN/i9HlnF04ekApU=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tNvTHUu/7v0VE2gpokLSMZP1C51o+thaC3+rQ+DUw4cZVMzUg7aBjRy8xZUkxPayCggn6t4Wu5HWX9wU+D3q2UUjYS+3Hd4ef7JpVLsnViWQrQkHxwQXpNNsm1tZ3W2qAi292PDQjGnSHgIfNcAmFk+zstzyrvY50gMdlrJXROk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 2 Aug 2024 17:05:52 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 2 Aug 2024 17:05:52 +0800 From: Kevin Chen To: , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 8/9] arm64: dts: aspeed: Add initial AST27XX device tree Date: Fri, 2 Aug 2024 17:05:43 +0800 Message-ID: <20240802090544.2741206-10-kevin_chen@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240802090544.2741206-1-kevin_chen@aspeedtech.com> References: <20240802090544.2741206-1-kevin_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add aspeed-g7.dtsi to be AST27XX device tree. Signed-off-by: Kevin Chen --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi | 185 ++++++++++++++++++++++ 2 files changed, 186 insertions(+) create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 21cd3a87f385..c909c19dc5dd 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -34,3 +34,4 @@ subdir-y +=3D tesla subdir-y +=3D ti subdir-y +=3D toshiba subdir-y +=3D xilinx +subdir-y +=3D aspeed diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi b/arch/arm64/boot/dt= s/aspeed/aspeed-g7.dtsi new file mode 100644 index 000000000000..85f7977a753a --- /dev/null +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +#include +#include +#include +#include + +/ { + compatible =3D "aspeed,ast2700"; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + compatible =3D "arm,cortex-a35"; + device_type =3D "cpu"; + enable-method =3D "psci"; + reg =3D <0>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + next-level-cache =3D <&l2>; + }; + + cpu@1 { + compatible =3D "arm,cortex-a35"; + device_type =3D "cpu"; + enable-method =3D "psci"; + reg =3D <1>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + next-level-cache =3D <&l2>; + }; + + cpu@2 { + compatible =3D "arm,cortex-a35"; + device_type =3D "cpu"; + enable-method =3D "psci"; + reg =3D <2>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + next-level-cache =3D <&l2>; + }; + + cpu@3 { + compatible =3D "arm,cortex-a35"; + device_type =3D "cpu"; + enable-method =3D "psci"; + reg =3D <3>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + next-level-cache =3D <&l2>; + }; + + l2: l2-cache0 { + compatible =3D "cache"; + cache-size =3D <0x80000>; + cache-unified; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + cache-level =3D <2>; + }; + }; + + pmu { + compatible =3D "arm,cortex-a35-pmu"; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + ; + arm,cpu-registers-not-fw-configured; + always-on; + }; + + soc0: soc@10000000 { + compatible =3D "simple-bus"; + reg =3D <0x0 0x10000000 0x0 0x10000000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + gic: interrupt-controller@12200000 { + compatible =3D "arm,gic-v3"; + interrupts =3D ; + #interrupt-cells =3D <3>; + interrupt-controller; + interrupt-parent =3D <&gic>; + reg =3D <0 0x12200000 0 0x10000>, /* GICD */ + <0 0x12280000 0 0x80000>, /* GICR */ + <0 0x40440000 0 0x1000>; /* GICC */ + #address-cells =3D <2>; + #size-cells =3D <2>; + }; + + syscon0: syscon@12c02000 { + compatible =3D "aspeed,ast2700-scu0", "syscon", "simple-mfd"; + reg =3D <0x0 0x12c02000 0x0 0x1000>; + ranges =3D <0x0 0x0 0 0x12c02000 0 0x1000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + + silicon-id@0 { + compatible =3D "aspeed,ast2700-silicon-id", "aspeed,silicon-id"; + reg =3D <0 0x0 0 0x4>; + }; + + soc0_rst: reset-controller@200 { + reg =3D <0 0x200 0 0x40>; + }; + + soc0_clk: clock-controller@240 { + reg =3D <0 0x240 0 0x1c0>; + }; + }; + + uart4: serial@12c1a000 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x12c1a000 0x0 0x1000>; + clocks =3D <&syscon0 SCU0_CLK_GATE_UART4CLK>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + no-loopback-test; + }; + }; + + soc1: soc@14000000 { + compatible =3D "simple-bus"; + reg =3D <0x0 0x14000000 0x0 0x10000000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + syscon1: syscon@14c02000 { + compatible =3D "aspeed,ast2700-scu1", "syscon", "simple-mfd"; + reg =3D <0x0 0x14c02000 0x0 0x1000>; + ranges =3D <0x0 0x0 0x0 0x14c02000 0x0 0x1000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + + soc1_rst: reset-controller@200 { + reg =3D <0 0x200 0 0x40>; + #reset-cells =3D <1>; + }; + + soc1_clk: clock-controller@240 { + reg =3D <0 0x240 0 0x1c0>; + }; + }; + }; +}; --=20 2.34.1