From nobody Thu Oct 31 00:25:36 2024 Received: from mail-yb1-f201.google.com (mail-yb1-f201.google.com [209.85.219.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E9C3146D7A for ; Thu, 1 Aug 2024 18:34:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722537300; cv=none; b=jEG+LY2AVRY1197kYX29suJNUWQaRXeApoEp/cxp9SVmrOcjz5y4moFPmuRy/VCJaaMTLv9O3/nu/86/GQRFpdMA8iA+lgOKP3Vnv/bIdGf2W4SgEFABlZuzFL32Vl4sJTMHGkO2vOiao8CzRKcxu2BwHbWQeBFlM+ZgmW/J5F8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722537300; c=relaxed/simple; bh=B4M5zM2LxlbX4e+OKo938Pgq8tauyjOo2Mz9UK1WRwE=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=X9plHNFGXjcFFaoL1YaUyffLyU3qzuQdZHvTEeujguU+jmZxWxbP8r0p2+MCNs2FZKPOZR+w0VpieodJYzfkmvP08CvrEbX1sTy38hufzt0p72Q6XAa2PxxIaMYI5sR+JSnMbjgTIolFs8i4qRrx7d4viwTVYAvRWPjwRTuCfIk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=xqnkioJg; arc=none smtp.client-ip=209.85.219.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="xqnkioJg" Received: by mail-yb1-f201.google.com with SMTP id 3f1490d57ef6-e0be2fa8f68so53262276.3 for ; Thu, 01 Aug 2024 11:34:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1722537298; x=1723142098; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=pYuydgqnu7KvS+vD/kJx/xLlR2Fg91BOlW6zTjcno7Q=; b=xqnkioJgRWzyMTa9C3AyqvcLKXN1NXw1GUktnC8nbyN5UNZOJf49BsVPbZikkX1xXR x+4xK5Q2URGVSmX0ZbAQ70ZwN9eFbPW6jrUJuqA2rhMI2vzLwHxVK/CU8VHU26QyyPmv sB5LDDsFOym5GSofCSESv1Iop7cZzQ1TOMBN38YOTaHqQEClvXoed/8ZO0DEbpk674Xb EYzGWJbuNXZJrepSbzsqm/WUThX5yu3M8+5kAUN93pvcVDOl8Ki8vMwdJnKUc46M73TZ VP5TFcLtBjfYB1JCMysdb/tUVWiJCKM7sAKuL7c9p2o+GDrq/Fgc5vtCKYUnwadbuB7b 0AFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722537298; x=1723142098; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=pYuydgqnu7KvS+vD/kJx/xLlR2Fg91BOlW6zTjcno7Q=; b=NUmwf6cEfErsl/zCt6EKoszB9RCSPnoZLexsJarAJoeQ5nGP/svTbHmUfjVdYEIZXL 2wbjoPwZmbF9r1o6v+9InXtn4/zncfOyr/jhfFbIoP5vJKpo099L9hGmL3+41t6tsr3W Wen8wxxIZwE797H+f+2GBuVaHjLpuX/t3BbyXhBiuEfwB5KAd3topzDBFLCxu5eQJFdM IiT9/oV991A6Bhifd85oU+rxH7ba7YSkJRe5mOYZfTK2HnQPbMHpMPHdO0fkTI0weEO2 QhEVms6LLWSxQNByLChJZPd3qi9FwTbCrfifCRRBSoHmLwR4YKNdBAj9MLCX81f3kPB0 7Jgw== X-Forwarded-Encrypted: i=1; AJvYcCWgr7zBK7I13mWfDjkaTj5uY7ybTkwJShaaCWXuS8s2ZRSRsWRIG4kRCJN2Nd8+6z4G+Ts2rUVKc+ES5LDuixGH4NSVl5qGxWi9le8A X-Gm-Message-State: AOJu0Yy54DJ879TOSjUV9Jot2Xt25kmACTcS6zfFCZXMEOzZucRJ4xe7 GZZjorXfnP5PjtxcGAFLHb5qjbTf1SaUdQhz42dU3I3MF92bjglRNCPyfxYKO3V58lxHLdCUoJF EbA== X-Google-Smtp-Source: AGHT+IFfRgjDzueDHA1wB4xIJlPq2Sh0SGDxzPYZTvnWrBT2GBLIr7FzlALzApVC+WiYgVOffmnlJ9uzeLA= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a05:6902:2b02:b0:e03:31ec:8a24 with SMTP id 3f1490d57ef6-e0bde422b24mr29349276.8.1722537298373; Thu, 01 Aug 2024 11:34:58 -0700 (PDT) Reply-To: Sean Christopherson Date: Thu, 1 Aug 2024 11:34:45 -0700 In-Reply-To: <20240801183453.57199-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240801183453.57199-1-seanjc@google.com> X-Mailer: git-send-email 2.46.0.rc2.264.g509ed76dc8-goog Message-ID: <20240801183453.57199-2-seanjc@google.com> Subject: [RFC PATCH 1/9] KVM: x86/mmu: Add a dedicated flag to track if A/D bits are globally enabled From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a dedicated flag to track if KVM has enabled A/D bits at the module level, instead of inferring the state based on whether or not the MMU's shadow_accessed_mask is non-zero. This will allow defining and using shadow_accessed_mask even when A/D bits aren't used by hardware. Signed-off-by: Sean Christopherson --- arch/x86/kvm/mmu/mmu.c | 6 +++--- arch/x86/kvm/mmu/spte.c | 6 ++++++ arch/x86/kvm/mmu/spte.h | 20 +++++++++----------- arch/x86/kvm/mmu/tdp_mmu.c | 4 ++-- 4 files changed, 20 insertions(+), 16 deletions(-) diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index 5979eeb916cd..1e24bc4a06db 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -3319,7 +3319,7 @@ static bool page_fault_can_be_fast(struct kvm *kvm, s= truct kvm_page_fault *fault * by setting the Writable bit, which can be done out of mmu_lock. */ if (!fault->present) - return !kvm_ad_enabled(); + return !kvm_ad_enabled; =20 /* * Note, instruction fetches and writes are mutually exclusive, ignore @@ -3454,7 +3454,7 @@ static int fast_page_fault(struct kvm_vcpu *vcpu, str= uct kvm_page_fault *fault) * uses A/D bits for non-nested MMUs. Thus, if A/D bits are * enabled, the SPTE can't be an access-tracked SPTE. */ - if (unlikely(!kvm_ad_enabled()) && is_access_track_spte(spte)) + if (unlikely(!kvm_ad_enabled) && is_access_track_spte(spte)) new_spte =3D restore_acc_track_spte(new_spte); =20 /* @@ -5429,7 +5429,7 @@ kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, role.efer_nx =3D true; role.smm =3D cpu_role.base.smm; role.guest_mode =3D cpu_role.base.guest_mode; - role.ad_disabled =3D !kvm_ad_enabled(); + role.ad_disabled =3D !kvm_ad_enabled; role.level =3D kvm_mmu_get_tdp_level(vcpu); role.direct =3D true; role.has_4_byte_gpte =3D false; diff --git a/arch/x86/kvm/mmu/spte.c b/arch/x86/kvm/mmu/spte.c index 2c5650390d3b..b713a6542eeb 100644 --- a/arch/x86/kvm/mmu/spte.c +++ b/arch/x86/kvm/mmu/spte.c @@ -24,6 +24,8 @@ static bool __ro_after_init allow_mmio_caching; module_param_named(mmio_caching, enable_mmio_caching, bool, 0444); EXPORT_SYMBOL_GPL(enable_mmio_caching); =20 +bool __read_mostly kvm_ad_enabled; + u64 __read_mostly shadow_host_writable_mask; u64 __read_mostly shadow_mmu_writable_mask; u64 __read_mostly shadow_nx_mask; @@ -435,6 +437,8 @@ EXPORT_SYMBOL_GPL(kvm_mmu_set_me_spte_mask); =20 void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only) { + kvm_ad_enabled =3D has_ad_bits; + shadow_user_mask =3D VMX_EPT_READABLE_MASK; shadow_accessed_mask =3D has_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull; shadow_dirty_mask =3D has_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull; @@ -468,6 +472,8 @@ void kvm_mmu_reset_all_pte_masks(void) u8 low_phys_bits; u64 mask; =20 + kvm_ad_enabled =3D true; + /* * If the CPU has 46 or less physical address bits, then set an * appropriate mask to guard against L1TF attacks. Otherwise, it is diff --git a/arch/x86/kvm/mmu/spte.h b/arch/x86/kvm/mmu/spte.h index ef793c459b05..d722b37b7434 100644 --- a/arch/x86/kvm/mmu/spte.h +++ b/arch/x86/kvm/mmu/spte.h @@ -167,6 +167,15 @@ static_assert(!(SHADOW_NONPRESENT_VALUE & SPTE_MMU_PRE= SENT_MASK)); #define SHADOW_NONPRESENT_VALUE 0ULL #endif =20 + +/* + * True if A/D bits are supported in hardware and are enabled by KVM. When + * enabled, KVM uses A/D bits for all non-nested MMUs. Because L1 can dis= able + * A/D bits in EPTP12, SP and SPTE variants are needed to handle the scena= rio + * where KVM is using A/D bits for L1, but not L2. + */ +extern bool __read_mostly kvm_ad_enabled; + extern u64 __read_mostly shadow_host_writable_mask; extern u64 __read_mostly shadow_mmu_writable_mask; extern u64 __read_mostly shadow_nx_mask; @@ -285,17 +294,6 @@ static inline bool is_ept_ve_possible(u64 spte) (spte & VMX_EPT_RWX_MASK) !=3D VMX_EPT_MISCONFIG_WX_VALUE; } =20 -/* - * Returns true if A/D bits are supported in hardware and are enabled by K= VM. - * When enabled, KVM uses A/D bits for all non-nested MMUs. Because L1 can - * disable A/D bits in EPTP12, SP and SPTE variants are needed to handle t= he - * scenario where KVM is using A/D bits for L1, but not L2. - */ -static inline bool kvm_ad_enabled(void) -{ - return !!shadow_accessed_mask; -} - static inline bool sp_ad_disabled(struct kvm_mmu_page *sp) { return sp->role.ad_disabled; diff --git a/arch/x86/kvm/mmu/tdp_mmu.c b/arch/x86/kvm/mmu/tdp_mmu.c index dc153cf92a40..2b0fc601d2ce 100644 --- a/arch/x86/kvm/mmu/tdp_mmu.c +++ b/arch/x86/kvm/mmu/tdp_mmu.c @@ -1072,7 +1072,7 @@ static int tdp_mmu_map_handle_target_level(struct kvm= _vcpu *vcpu, static int tdp_mmu_link_sp(struct kvm *kvm, struct tdp_iter *iter, struct kvm_mmu_page *sp, bool shared) { - u64 spte =3D make_nonleaf_spte(sp->spt, !kvm_ad_enabled()); + u64 spte =3D make_nonleaf_spte(sp->spt, !kvm_ad_enabled); int ret =3D 0; =20 if (shared) { @@ -1488,7 +1488,7 @@ static bool tdp_mmu_need_write_protect(struct kvm_mmu= _page *sp) * from level, so it is valid to key off any shadow page to determine if * write protection is needed for an entire tree. */ - return kvm_mmu_page_ad_need_write_protect(sp) || !kvm_ad_enabled(); + return kvm_mmu_page_ad_need_write_protect(sp) || !kvm_ad_enabled; } =20 static bool clear_dirty_gfn_range(struct kvm *kvm, struct kvm_mmu_page *ro= ot, --=20 2.46.0.rc1.232.g9752f9e123-goog