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[37.119.36.202]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-428e6e7d615sm1802005e9.29.2024.08.01.09.10.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Aug 2024 09:10:09 -0700 (PDT) From: Alessandro Zanni To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, skhan@linuxfoundation.org Cc: Alessandro Zanni , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3] dt-bindings: edac: Add Altera SOCFPGA SDRAM EDAC binding Date: Thu, 1 Aug 2024 18:10:02 +0200 Message-ID: <20240801161005.120111-1-alessandro.zanni87@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert the device tree bindings for the Altera PCIe MSI controller Signed-off-by: Alessandro Zanni --- Notes: v3: moved yaml file from arm/altera to the edac folder, removed items k= eys, added general node names .../arm/altera/socfpga-sdram-edac.txt | 15 ------- .../bindings/edac/altr,sdram-edac.yaml | 44 +++++++++++++++++++ 2 files changed, 44 insertions(+), 15 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-sd= ram-edac.txt create mode 100644 Documentation/devicetree/bindings/edac/altr,sdram-edac.= yaml diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-eda= c.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt deleted file mode 100644 index f5ad0ff69fae..000000000000 --- a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt +++ /dev/null @@ -1,15 +0,0 @@ -Altera SOCFPGA SDRAM Error Detection & Correction [EDAC] -The EDAC accesses a range of registers in the SDRAM controller. - -Required properties: -- compatible : should contain "altr,sdram-edac" or "altr,sdram-edac-a10" -- altr,sdr-syscon : phandle of the sdr module -- interrupts : Should contain the SDRAM ECC IRQ in the - appropriate format for the IRQ controller. - -Example: - sdramedac { - compatible =3D "altr,sdram-edac"; - altr,sdr-syscon =3D <&sdr>; - interrupts =3D <0 39 4>; - }; diff --git a/Documentation/devicetree/bindings/edac/altr,sdram-edac.yaml b/= Documentation/devicetree/bindings/edac/altr,sdram-edac.yaml new file mode 100644 index 000000000000..31bcee4274fa --- /dev/null +++ b/Documentation/devicetree/bindings/edac/altr,sdram-edac.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/edac/altr,sdram-edac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera SOCFPGA SDRAM Error Detection & Correction [EDAC] + +maintainers: + - Dinh Nguyen + +description: + The EDAC accesses a range of registers in the SDRAM controller. + +properties: + compatible: + enum: + - altr,sdram-edac + - altr,sdram-edac-a10 + + altr,sdr-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description:=20 + Phandle of the sdr module + + interrupts: + maxItems: 1 + +required: + - compatible + - altr,sdr-syscon + - interrupts + +additionalProperties: false + +examples: + - | + memory-controller { + compatible =3D "altr,sdram-edac"; + altr,sdr-syscon =3D <&sdr>; + interrupts =3D <0 39 4>; + }; + +... --=20 2.43.0