From nobody Sun Feb 8 11:59:39 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 063D214C58E for ; Thu, 1 Aug 2024 05:44:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722491090; cv=none; b=dygYFkFDxJbOYG+IivU8IYhZPP3EYL0Xd48CToBIs69ePMXPwp7V7RxV8GpEaCmS4hwX6yEu01LY5e62cKIjVUCxB96AFQbspnT/doVxzeBEO4GbFywpepPc19zYXUDAKqwvBNRK+hpRuPP7w/cZsh3UKNe8YjBXYhTa5MPmhZM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722491090; c=relaxed/simple; bh=0lZftV0DbhSmGhAjLNzyFgVYbeGgP5GK8F7XjXp8ch4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=pNJE3CXXk3geQvCMk7C4NqGshUekQnnI7UnSVX6s30S0nwA6EKBQA7Ql+7AVFRpsYLW4Y2/y4lBmO1EmxcWFboHg5LVw/hQTg/hRPnX6Q/L02O3xi1TpHlgUIWDwO0fjx/IvPWSnsJRBAqzJPkbM1ZMqzztPjAyIse2J7PQuFeE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C08351063; Wed, 31 Jul 2024 22:45:12 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.56.112]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id CE2443F5A1; Wed, 31 Jul 2024 22:44:44 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Mark Brown , linux-kernel@vger.kernel.org Subject: [PATCH 1/1] arm64/tools/sysreg: Add Sysreg128/SysregFields128 Date: Thu, 1 Aug 2024 11:14:36 +0530 Message-Id: <20240801054436.612024-2-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240801054436.612024-1-anshuman.khandual@arm.com> References: <20240801054436.612024-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" FEAT_SYSREG128 enables 128 bit wide system registers which also need to be defined in (arch/arm64/toos/sysreg) for auto mask generation. This adds two new field types i.e Sysreg128 and SysregFields128 for that same purpose. It utilizes recently added macro GENMASK_U128() while also adding some helpers such as define_field_128() and parse_bitdef_128(). Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/gen-sysreg.awk | 231 ++++++++++++++++++++++++++++++++ 1 file changed, 231 insertions(+) diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.= awk index d1254a056114..a1571881d1c3 100755 --- a/arch/arm64/tools/gen-sysreg.awk +++ b/arch/arm64/tools/gen-sysreg.awk @@ -56,6 +56,13 @@ function define_field(reg, field, msb, lsb) { define(reg "_" field "_WIDTH", msb - lsb + 1) } =20 +function define_field_128(reg, field, msb, lsb) { + define(reg "_" field, "GENMASK_U128(" msb ", " lsb ")") + define(reg "_" field "_MASK", "GENMASK_U128(" msb ", " lsb ")") + define(reg "_" field "_SHIFT", lsb) + define(reg "_" field "_WIDTH", msb - lsb + 1) +} + # Print a field _SIGNED definition for a field function define_field_sign(reg, field, sign) { define(reg "_" field "_SIGNED", sign) @@ -89,6 +96,33 @@ function parse_bitdef(reg, field, bitdef, _bits) next_bit =3D lsb - 1 } =20 +function parse_bitdef_128(reg, field, bitdef, _bits) +{ + if (bitdef ~ /^[0-9]+$/) { + msb =3D bitdef + lsb =3D bitdef + } else if (split(bitdef, _bits, ":") =3D=3D 2) { + msb =3D _bits[1] + lsb =3D _bits[2] + } else { + fatal("invalid bit-range definition '" bitdef "'") + } + + + if (msb !=3D next_bit) + fatal(reg "." field " starts at " msb " not " next_bit) + if (127 < msb || msb < 0) + fatal(reg "." field " invalid high bit in '" bitdef "'") + if (127 < lsb || lsb < 0) + fatal(reg "." field " invalid low bit in '" bitdef "'") + if (msb < lsb) + fatal(reg "." field " invalid bit-range '" bitdef "'") + if (low > high) + fatal(reg "." field " has invalid range " high "-" low) + + next_bit =3D lsb - 1 +} + BEGIN { print "#ifndef __ASM_SYSREG_DEFS_H" print "#define __ASM_SYSREG_DEFS_H" @@ -111,6 +145,99 @@ END { /^$/ { next } /^[\t ]*#/ { next } =20 +/^SysregFields128/ && block_current() =3D=3D "Root" { + block_push("SysregFields128") + + expect_fields(2) + + reg =3D $2 + + res0 =3D "UL(0)" + res1 =3D "UL(0)" + unkn =3D "UL(0)" + + next_bit =3D 127 + + next +} + +/^EndSysregFields128/ && block_current() =3D=3D "SysregFields128" { + if (next_bit > 0) + fatal("Unspecified bits in " reg) + + define(reg "_RES0", "(" res0 ")") + define(reg "_RES1", "(" res1 ")") + define(reg "_UNKN", "(" unkn ")") + print "" + + reg =3D null + res0 =3D null + res1 =3D null + unkn =3D null + + block_pop() + next +} + +/^Sysreg128/ && block_current() =3D=3D "Root" { + block_push("Sysreg128") + + expect_fields(7) + + reg =3D $2 + op0 =3D $3 + op1 =3D $4 + crn =3D $5 + crm =3D $6 + op2 =3D $7 + + res0 =3D "UL(0)" + res1 =3D "UL(0)" + unkn =3D "UL(0)" + + define("REG_" reg, "S" op0 "_" op1 "_C" crn "_C" crm "_" op2) + define("SYS_" reg, "sys_reg(" op0 ", " op1 ", " crn ", " crm ", " op2 ")") + + define("SYS_" reg "_Op0", op0) + define("SYS_" reg "_Op1", op1) + define("SYS_" reg "_CRn", crn) + define("SYS_" reg "_CRm", crm) + define("SYS_" reg "_Op2", op2) + + print "" + + next_bit =3D 127 + + next +} + +/^EndSysreg128/ && block_current() =3D=3D "Sysreg128" { + if (next_bit > 0) + fatal("Unspecified bits in " reg) + + if (res0 !=3D null) + define(reg "_RES0", "(" res0 ")") + if (res1 !=3D null) + define(reg "_RES1", "(" res1 ")") + if (unkn !=3D null) + define(reg "_UNKN", "(" unkn ")") + if (res0 !=3D null || res1 !=3D null || unkn !=3D null) + print "" + + reg =3D null + op0 =3D null + op1 =3D null + crn =3D null + crm =3D null + op2 =3D null + res0 =3D null + res1 =3D null + unkn =3D null + + block_pop() + next +} + /^SysregFields/ && block_current() =3D=3D "Root" { block_push("SysregFields") =20 @@ -223,6 +350,22 @@ END { next } =20 +/^Fields/ && block_current() =3D=3D "Sysreg128" { + expect_fields(2) + + if (next_bit !=3D 127) + fatal("Some fields already defined for " reg) + + print "/* For " reg " fields see " $2 " */" + print "" + + next_bit =3D 0 + res0 =3D null + res1 =3D null + unkn =3D null + + next +} =20 /^Res0/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sys= regFields") { expect_fields(2) @@ -234,6 +377,16 @@ END { next } =20 +/^Res0/ && (block_current() =3D=3D "Sysreg128" || block_current() =3D=3D "= SysregFields128") { + expect_fields(2) + parse_bitdef_128(reg, "RES0", $2) + field =3D "RES0_" msb "_" lsb + + res0 =3D res0 " | GENMASK_U128(" msb ", " lsb ")" + + next +} + /^Res1/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sys= regFields") { expect_fields(2) parse_bitdef(reg, "RES1", $2) @@ -244,6 +397,16 @@ END { next } =20 +/^Res1/ && (block_current() =3D=3D "Sysreg128" || block_current() =3D=3D "= SysregFields128") { + expect_fields(2) + parse_bitdef_128(reg, "RES1", $2) + field =3D "RES1_" msb "_" lsb + + res1 =3D res1 " | GENMASK_U128(" msb ", " lsb ")" + + next +} + /^Unkn/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sys= regFields") { expect_fields(2) parse_bitdef(reg, "UNKN", $2) @@ -254,6 +417,16 @@ END { next } =20 +/^Unkn/ && (block_current() =3D=3D "Sysreg128" || block_current() =3D=3D "= SysregFields128") { + expect_fields(2) + parse_bitdef_128(reg, "UNKN", $2) + field =3D "UNKN_" msb "_" lsb + + unkn =3D unkn " | GENMASK_U128(" msb ", " lsb ")" + + next +} + /^Field/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sy= sregFields") { expect_fields(3) field =3D $3 @@ -265,6 +438,17 @@ END { next } =20 +/^Field/ && (block_current() =3D=3D "Sysreg128" || block_current() =3D=3D = "SysregFields128") { + expect_fields(3) + field =3D $3 + parse_bitdef_128(reg, field, $2) + + define_field_128(reg, field, msb, lsb) + print "" + + next +} + /^Raz/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sysr= egFields") { expect_fields(2) parse_bitdef(reg, field, $2) @@ -272,6 +456,14 @@ END { next } =20 +/^Raz/ && (block_current() =3D=3D "Sysreg128" || block_current() =3D=3D "S= ysregFields128") { + expect_fields(2) + parse_bitdef_128(reg, field, $2) + + next +} + + /^SignedEnum/ && (block_current() =3D=3D "Sysreg" || block_current() =3D= =3D "SysregFields") { block_push("Enum") =20 @@ -285,6 +477,19 @@ END { next } =20 +/^SignedEnum/ && (block_current() =3D=3D "Sysreg128" || block_current() = =3D=3D "SysregFields128") { + block_push("Enum") + + expect_fields(3) + field =3D $3 + parse_bitdef_128(reg, field, $2) + + define_field_128(reg, field, msb, lsb) + define_field_sign(reg, field, "true") + + next +} + /^UnsignedEnum/ && (block_current() =3D=3D "Sysreg" || block_current() =3D= =3D "SysregFields") { block_push("Enum") =20 @@ -298,6 +503,20 @@ END { next } =20 +/^UnsignedEnum/ && (block_current() =3D=3D "Sysreg128" || block_current() = =3D=3D "SysregFields128") { + block_push("Enum") + + expect_fields(3) + field =3D $3 + parse_bitdef_128(reg, field, $2) + + define_field_128(reg, field, msb, lsb) + define_field_sign(reg, field, "false") + + next +} + + /^Enum/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sys= regFields") { block_push("Enum") =20 @@ -310,6 +529,18 @@ END { next } =20 +/^Enum/ && (block_current() =3D=3D "Sysreg128" || block_current() =3D=3D "= SysregFields128") { + block_push("Enum") + + expect_fields(3) + field =3D $3 + parse_bitdef_128(reg, field, $2) + + define_field_128(reg, field, msb, lsb) + + next +} + /^EndEnum/ && block_current() =3D=3D "Enum" { =20 field =3D null --=20 2.30.2