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a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 From: Drew Fustini Add clock property to TH1520 gpio controller nodes. These clock gates refer to corresponding enable bits in the peripheral clock gate control register. Refer to register PERI_CLK_CFG in section 4.4.2.2.52 of the TH1520 System User Manual. Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/d= ocs Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index 6ea5cabbcf60..5f4f94ca9cc7 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -327,6 +327,7 @@ gpio2: gpio@ffe7f34000 { reg =3D <0xff 0xe7f34000 0x0 0x1000>; #address-cells =3D <1>; #size-cells =3D <0>; + clocks =3D <&clk CLK_GPIO2>; =20 portc: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; @@ -345,6 +346,7 @@ gpio3: gpio@ffe7f38000 { reg =3D <0xff 0xe7f38000 0x0 0x1000>; #address-cells =3D <1>; #size-cells =3D <0>; + clocks =3D <&clk CLK_GPIO3>; =20 portd: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; @@ -363,6 +365,7 @@ gpio0: gpio@ffec005000 { reg =3D <0xff 0xec005000 0x0 0x1000>; #address-cells =3D <1>; #size-cells =3D <0>; + clocks =3D <&clk CLK_GPIO0>; =20 porta: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; @@ -381,6 +384,7 @@ gpio1: gpio@ffec006000 { reg =3D <0xff 0xec006000 0x0 0x1000>; #address-cells =3D <1>; #size-cells =3D <0>; + clocks =3D <&clk CLK_GPIO1>; =20 portb: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; --=20 2.34.1