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a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 From: Drew Fustini Change the clock property in TH1520 uart nodes to a clock provided by AP_SUBSYS clock controller. Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/d= ocs Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 4 ---- .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ---- arch/riscv/boot/dts/thead/th1520.dtsi | 24 +++++++++++-------= ---- 3 files changed, 12 insertions(+), 20 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/risc= v/boot/dts/thead/th1520-beaglev-ahead.dts index b4d2e1d69bdb..90585883b059 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -57,10 +57,6 @@ &spi_clk { clock-frequency =3D <396000000>; }; =20 -&uart_sclk { - clock-frequency =3D <100000000>; -}; - &dmac0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/= riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index 6939bd36560c..1c5c7075ae17 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -37,10 +37,6 @@ &spi_clk { clock-frequency =3D <396000000>; }; =20 -&uart_sclk { - clock-frequency =3D <100000000>; -}; - &dmac0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index 25ef5ee729e6..a543be8d6e37 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -228,12 +228,6 @@ spi_clk: spi-clock { #clock-cells =3D <0>; }; =20 - uart_sclk: uart-sclk-clock { - compatible =3D "fixed-clock"; - clock-output-names =3D "uart_sclk"; - #clock-cells =3D <0>; - }; - sdhci_clk: sdhci-clock { compatible =3D "fixed-clock"; clock-frequency =3D <198000000>; @@ -285,7 +279,8 @@ uart0: serial@ffe7014000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xe7014000 0x0 0x100>; interrupts =3D <36 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&uart_sclk>; + clocks =3D <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>; + clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; status =3D "disabled"; @@ -322,7 +317,8 @@ uart1: serial@ffe7f00000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xe7f00000 0x0 0x100>; interrupts =3D <37 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&uart_sclk>; + clocks =3D <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>; + clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; status =3D "disabled"; @@ -332,7 +328,8 @@ uart3: serial@ffe7f04000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xe7f04000 0x0 0x100>; interrupts =3D <39 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&uart_sclk>; + clocks =3D <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>; + clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; status =3D "disabled"; @@ -414,7 +411,8 @@ uart2: serial@ffec010000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xec010000 0x0 0x4000>; interrupts =3D <38 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&uart_sclk>; + clocks =3D <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>; + clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; status =3D "disabled"; @@ -483,7 +481,8 @@ uart4: serial@fff7f08000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xf7f08000 0x0 0x4000>; interrupts =3D <40 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&uart_sclk>; + clocks =3D <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>; + clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; status =3D "disabled"; @@ -493,7 +492,8 @@ uart5: serial@fff7f0c000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xf7f0c000 0x0 0x4000>; interrupts =3D <41 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&uart_sclk>; + clocks =3D <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>; + clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; status =3D "disabled"; --=20 2.34.1