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a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 From: Drew Fustini Add node for the AP_SUBSYS clock controller on the T-Head TH1520 SoC. Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/T= H1520%20System%20User%20Manual.pdf Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/d= ocs Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index aa703da30fc3..25ef5ee729e6 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -5,6 +5,7 @@ */ =20 #include +#include =20 / { compatible =3D "thead,th1520"; @@ -419,6 +420,13 @@ uart2: serial@ffec010000 { status =3D "disabled"; }; =20 + clk: clock-controller@ffef010000 { + compatible =3D "thead,th1520-clk-ap"; + reg =3D <0xff 0xef010000 0x0 0x1000>; + clocks =3D <&osc>; + #clock-cells =3D <1>; + }; + dmac0: dma-controller@ffefc00000 { compatible =3D "snps,axi-dma-1.01a"; reg =3D <0xff 0xefc00000 0x0 0x1000>; --=20 2.34.1 From nobody Wed Oct 30 22:17:05 2024 Received: from mail-pj1-f45.google.com (mail-pj1-f45.google.com [209.85.216.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95B831494A5 for ; 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Thu, 01 Aug 2024 11:38:22 -0700 (PDT) Received: from [127.0.1.1] ([2601:1c2:1802:170:dfa1:41a7:9478:9d47]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2cffaf69d54sm279728a91.12.2024.08.01.11.38.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Aug 2024 11:38:22 -0700 (PDT) From: Drew Fustini Date: Thu, 01 Aug 2024 11:38:06 -0700 Subject: [PATCH 2/6] riscv: dts: thead: change TH1520 uart nodes to use clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240801-th1520-clk-dts-v1-2-71077a0614b8@pdp7.com> References: <20240801-th1520-clk-dts-v1-0-71077a0614b8@pdp7.com> In-Reply-To: <20240801-th1520-clk-dts-v1-0-71077a0614b8@pdp7.com> To: Emil Renner Berthing , Thomas Bonnefille , Kanak Shilledar , Jisheng Zhang , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini , Drew Fustini X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=4182; i=drew@pdp7.com; h=from:subject:message-id; bh=LEB/O6tBSHji0s/zln825HKghg4t/13zO0aXBDRHXqQ=; b=owGbwMvMwCF2+43O4ZsaG3kYT6slMaStviaZeERijtv6qz7z2/z/rPigN7lo4YKFez7k3JLUK ryo0rlEuaOUhUGMg0FWTJFl04e8C0u8Qr8umP9iG8wcViaQIQxcnAIwkeoARoaD2dO2L3a+auaj s4PrEOPPgImWnjZTtuk+FXy3Pj7+2TYpRoZV3Cncj1zzeR/3h2iprfFh4v01W6lRScSvr0cxpuI dBxcA X-Developer-Key: i=drew@pdp7.com; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 From: Drew Fustini Change the clock property in TH1520 uart nodes to a clock provided by AP_SUBSYS clock controller. Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/d= ocs Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 4 ---- .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ---- arch/riscv/boot/dts/thead/th1520.dtsi | 24 +++++++++++-------= ---- 3 files changed, 12 insertions(+), 20 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/risc= v/boot/dts/thead/th1520-beaglev-ahead.dts index b4d2e1d69bdb..90585883b059 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -57,10 +57,6 @@ &spi_clk { clock-frequency =3D <396000000>; }; =20 -&uart_sclk { - clock-frequency =3D <100000000>; -}; - &dmac0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/= riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index 6939bd36560c..1c5c7075ae17 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -37,10 +37,6 @@ &spi_clk { clock-frequency =3D <396000000>; }; =20 -&uart_sclk { - clock-frequency =3D <100000000>; -}; - &dmac0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index 25ef5ee729e6..a543be8d6e37 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -228,12 +228,6 @@ spi_clk: spi-clock { #clock-cells =3D <0>; }; =20 - uart_sclk: uart-sclk-clock { - compatible =3D "fixed-clock"; - clock-output-names =3D "uart_sclk"; - #clock-cells =3D <0>; - }; - sdhci_clk: sdhci-clock { compatible =3D "fixed-clock"; clock-frequency =3D <198000000>; @@ -285,7 +279,8 @@ uart0: serial@ffe7014000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xe7014000 0x0 0x100>; interrupts =3D <36 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&uart_sclk>; + clocks =3D <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>; + clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; status =3D "disabled"; @@ -322,7 +317,8 @@ uart1: serial@ffe7f00000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xe7f00000 0x0 0x100>; interrupts =3D <37 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&uart_sclk>; + clocks =3D <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>; + clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; status =3D "disabled"; @@ -332,7 +328,8 @@ uart3: serial@ffe7f04000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xe7f04000 0x0 0x100>; interrupts =3D <39 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&uart_sclk>; + clocks =3D <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>; + clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; status =3D "disabled"; @@ -414,7 +411,8 @@ uart2: serial@ffec010000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xec010000 0x0 0x4000>; interrupts =3D <38 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&uart_sclk>; + clocks =3D <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>; + clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; status =3D "disabled"; @@ -483,7 +481,8 @@ uart4: serial@fff7f08000 { compatible =3D "snps,dw-apb-uart"; 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Thu, 01 Aug 2024 11:38:24 -0700 (PDT) Received: from [127.0.1.1] ([2601:1c2:1802:170:dfa1:41a7:9478:9d47]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2cffaf69d54sm279728a91.12.2024.08.01.11.38.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Aug 2024 11:38:23 -0700 (PDT) From: Drew Fustini Date: Thu, 01 Aug 2024 11:38:07 -0700 Subject: [PATCH 3/6] riscv: dts: thead: change TH1520 mmc nodes to use clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240801-th1520-clk-dts-v1-3-71077a0614b8@pdp7.com> References: <20240801-th1520-clk-dts-v1-0-71077a0614b8@pdp7.com> In-Reply-To: <20240801-th1520-clk-dts-v1-0-71077a0614b8@pdp7.com> To: Emil Renner Berthing , Thomas Bonnefille , Kanak Shilledar , Jisheng Zhang , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini , Drew Fustini X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2960; i=drew@pdp7.com; h=from:subject:message-id; bh=YuaP04LUjcDqw71tzI0qnQ5/4oo5IjakGbRJi9B2Yv4=; b=owGbwMvMwCF2+43O4ZsaG3kYT6slMaStviZ1I9lFu9CO7WBeRnGBVKrm0Y9916xmHWGReh7Id 6nPZP73jlIWBjEOBlkxRZZNH/IuLPEK/bpg/ottMHNYmUCGMHBxCsBN/sPwz0xuy+PMhQ1l6W71 jO9XvvXYtOXHY+0HO3QlfZcHnOiPvsLIcLiy+63V0+SL+zbsVv56y8lpzozTpXksd34mfg348iI 6gBkA X-Developer-Key: i=drew@pdp7.com; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 From: Drew Fustini Change the clock property in the TH1520 mmc controller nodes to a clock provided by AP_SYS clock controller. Remove sdhci fixed clock reference from BeagleV Ahead and LPI4a dts. Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/d= ocs Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 4 ---- arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ---- arch/riscv/boot/dts/thead/th1520.dtsi | 13 +++---------- 3 files changed, 3 insertions(+), 18 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/risc= v/boot/dts/thead/th1520-beaglev-ahead.dts index 90585883b059..5169a718f79c 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -49,10 +49,6 @@ &apb_clk { clock-frequency =3D <62500000>; }; =20 -&sdhci_clk { - clock-frequency =3D <198000000>; -}; - &spi_clk { clock-frequency =3D <396000000>; }; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/= riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index 1c5c7075ae17..be982a3ac18c 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -29,10 +29,6 @@ &apb_clk { clock-frequency =3D <62500000>; }; =20 -&sdhci_clk { - clock-frequency =3D <198000000>; -}; - &spi_clk { clock-frequency =3D <396000000>; }; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index a543be8d6e37..f3b2f8236096 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -228,13 +228,6 @@ spi_clk: spi-clock { #clock-cells =3D <0>; }; =20 - sdhci_clk: sdhci-clock { - compatible =3D "fixed-clock"; - clock-frequency =3D <198000000>; - clock-output-names =3D "sdhci_clk"; - #clock-cells =3D <0>; - }; - soc { compatible =3D "simple-bus"; interrupt-parent =3D <&plic>; @@ -290,7 +283,7 @@ emmc: mmc@ffe7080000 { compatible =3D "thead,th1520-dwcmshc"; reg =3D <0xff 0xe7080000 0x0 0x10000>; interrupts =3D <62 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&sdhci_clk>; + clocks =3D <&clk CLK_EMMC_SDIO>; clock-names =3D "core"; status =3D "disabled"; }; @@ -299,7 +292,7 @@ sdio0: mmc@ffe7090000 { compatible =3D "thead,th1520-dwcmshc"; reg =3D <0xff 0xe7090000 0x0 0x10000>; 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Thu, 01 Aug 2024 11:38:25 -0700 (PDT) From: Drew Fustini Date: Thu, 01 Aug 2024 11:38:08 -0700 Subject: [PATCH 4/6] riscv: dts: thead: update TH1520 dma and timer nodes to use clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240801-th1520-clk-dts-v1-4-71077a0614b8@pdp7.com> References: <20240801-th1520-clk-dts-v1-0-71077a0614b8@pdp7.com> In-Reply-To: <20240801-th1520-clk-dts-v1-0-71077a0614b8@pdp7.com> To: Emil Renner Berthing , Thomas Bonnefille , Kanak Shilledar , Jisheng Zhang , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini , Drew Fustini X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=4983; i=drew@pdp7.com; h=from:subject:message-id; bh=39TQlbKslvMloaaNbMx3AO4nAgflfRVN9+VBBv24ZBA=; b=owGbwMvMwCF2+43O4ZsaG3kYT6slMaStvia16RHD6S/rDnRVlqTz7fDvXp9k9J1hy4n7t2vuK QQlB4XbdpSyMIhxMMiKKbJs+pB3YYlX6NcF819sg5nDygQyhIGLUwAm8o2R4Z9Cq69huxxjfUzY 1fWfhHK+RT5MWRQ3qeiBUeAmTVa5XUqMDP/3ssi+7hHInB+81v7t0jifv99+f2PNV/o368VBjWr jczwA X-Developer-Key: i=drew@pdp7.com; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 From: Drew Fustini Change the dma-controller and timer nodes to use the APB clock provided by the AP_SUBSYS clock controller. Remove apb_clk reference from BeagleV Ahead and LPI4a dts. Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/d= ocs Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 4 ---- .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ---- arch/riscv/boot/dts/thead/th1520.dtsi | 24 ++++++++----------= ---- 3 files changed, 9 insertions(+), 23 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/risc= v/boot/dts/thead/th1520-beaglev-ahead.dts index 5169a718f79c..425f07d73b32 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -45,10 +45,6 @@ &osc_32k { clock-frequency =3D <32768>; }; =20 -&apb_clk { - clock-frequency =3D <62500000>; -}; - &spi_clk { clock-frequency =3D <396000000>; }; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/= riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index be982a3ac18c..077dbbe4abb6 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -25,10 +25,6 @@ &osc_32k { clock-frequency =3D <32768>; }; =20 -&apb_clk { - clock-frequency =3D <62500000>; -}; - &spi_clk { clock-frequency =3D <396000000>; }; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index f3b2f8236096..6ea5cabbcf60 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -216,12 +216,6 @@ osc_32k: 32k-oscillator { #clock-cells =3D <0>; }; =20 - apb_clk: apb-clk-clock { - compatible =3D "fixed-clock"; - clock-output-names =3D "apb_clk"; - #clock-cells =3D <0>; - }; - spi_clk: spi-clock { compatible =3D "fixed-clock"; clock-output-names =3D "spi_clk"; @@ -422,7 +416,7 @@ dmac0: dma-controller@ffefc00000 { compatible =3D "snps,axi-dma-1.01a"; reg =3D <0xff 0xefc00000 0x0 0x1000>; interrupts =3D <27 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&apb_clk>, <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>, <&clk CLK_PERI_APB_PCLK>; clock-names =3D "core-clk", "cfgr-clk"; #dma-cells =3D <1>; dma-channels =3D <4>; @@ -437,7 +431,7 @@ dmac0: dma-controller@ffefc00000 { timer0: timer@ffefc32000 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xefc32000 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -446,7 +440,7 @@ timer0: timer@ffefc32000 { timer1: timer@ffefc32014 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xefc32014 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <17 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -455,7 +449,7 @@ timer1: timer@ffefc32014 { timer2: timer@ffefc32028 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xefc32028 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <18 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -464,7 +458,7 @@ timer2: timer@ffefc32028 { timer3: timer@ffefc3203c { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xefc3203c 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <19 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -495,7 +489,7 @@ uart5: serial@fff7f0c000 { timer4: timer@ffffc33000 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xffc33000 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <20 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -504,7 +498,7 @@ timer4: timer@ffffc33000 { timer5: timer@ffffc33014 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xffc33014 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <21 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -513,7 +507,7 @@ timer5: timer@ffffc33014 { timer6: timer@ffffc33028 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xffc33028 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <22 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -522,7 +516,7 @@ timer6: timer@ffffc33028 { timer7: timer@ffffc3303c { compatible =3D "snps,dw-apb-timer"; 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Thu, 01 Aug 2024 11:38:26 -0700 (PDT) From: Drew Fustini Date: Thu, 01 Aug 2024 11:38:09 -0700 Subject: [PATCH 5/6] riscv: dts: thead: add clock to TH1520 gpio nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240801-th1520-clk-dts-v1-5-71077a0614b8@pdp7.com> References: <20240801-th1520-clk-dts-v1-0-71077a0614b8@pdp7.com> In-Reply-To: <20240801-th1520-clk-dts-v1-0-71077a0614b8@pdp7.com> To: Emil Renner Berthing , Thomas Bonnefille , Kanak Shilledar , Jisheng Zhang , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini , Drew Fustini X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1705; i=drew@pdp7.com; h=from:subject:message-id; bh=L05YOZ6P7b77yQdqua1ed/hLSCwatc60q8wYDB+6T9E=; b=owGbwMvMwCF2+43O4ZsaG3kYT6slMaStviZ1Nn7JpyPK8uce7rlh2D/xSpjfu91qh5hX7lsU/ 7R145otCR2lLAxiHAyyYoosmz7kXVjiFfp1wfwX22DmsDKBDGHg4hSAiahMZPif9uS1ncGMoE3s NtuM37J+MtSfJrjra44Ss9GDmMDzly2BKrwjy5qyfr+boZahwBBQdXrqnff1u7dqNH75PlfiUaL 6a1YA X-Developer-Key: i=drew@pdp7.com; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 From: Drew Fustini Add clock property to TH1520 gpio controller nodes. These clock gates refer to corresponding enable bits in the peripheral clock gate control register. Refer to register PERI_CLK_CFG in section 4.4.2.2.52 of the TH1520 System User Manual. Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/d= ocs Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index 6ea5cabbcf60..5f4f94ca9cc7 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -327,6 +327,7 @@ gpio2: gpio@ffe7f34000 { reg =3D <0xff 0xe7f34000 0x0 0x1000>; #address-cells =3D <1>; #size-cells =3D <0>; + clocks =3D <&clk CLK_GPIO2>; =20 portc: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; @@ -345,6 +346,7 @@ gpio3: gpio@ffe7f38000 { reg =3D <0xff 0xe7f38000 0x0 0x1000>; #address-cells =3D <1>; #size-cells =3D <0>; + clocks =3D <&clk CLK_GPIO3>; =20 portd: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; @@ -363,6 +365,7 @@ gpio0: gpio@ffec005000 { reg =3D <0xff 0xec005000 0x0 0x1000>; #address-cells =3D <1>; #size-cells =3D <0>; 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Thu, 01 Aug 2024 11:38:27 -0700 (PDT) From: Drew Fustini Date: Thu, 01 Aug 2024 11:38:10 -0700 Subject: [PATCH 6/6] riscv: dts: thead: change TH1520 SPI node to use clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240801-th1520-clk-dts-v1-6-71077a0614b8@pdp7.com> References: <20240801-th1520-clk-dts-v1-0-71077a0614b8@pdp7.com> In-Reply-To: <20240801-th1520-clk-dts-v1-0-71077a0614b8@pdp7.com> To: Emil Renner Berthing , Thomas Bonnefille , Kanak Shilledar , Jisheng Zhang , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini , Drew Fustini X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2303; i=drew@pdp7.com; h=from:subject:message-id; bh=GEkmEzaBBCWW5dvp0uJoNHGIioeJZ823d7ZJt1ChQBI=; b=owGbwMvMwCF2+43O4ZsaG3kYT6slMaStvibFWr3h3cwewfTJzWvni31U2PSlSjEs/s+V9QuVA u9svnPmW0cpC4MYB4OsmCLLpg95F5Z4hX5dMP/FNpg5rEwgQxi4OAVgItc6GRl2PzSIMtz8ppXt /dRsHlW5y+9/nrgXM/Gl8X2zvlIB09QnjAy3hfVYV025nBKU4268Y9LKjvjFFRc3OrW/kBd5fir tVjg3AA== X-Developer-Key: i=drew@pdp7.com; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 From: Drew Fustini Change the clock property in the TH1520 SPI controller node to a clock provided by AP_SYS clock controller. Remove spi_clk fixed clock reference from BeagleV Ahead and LPI4a dts. Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/d= ocs Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 4 ---- arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ---- arch/riscv/boot/dts/thead/th1520.dtsi | 8 +------- 3 files changed, 1 insertion(+), 15 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/risc= v/boot/dts/thead/th1520-beaglev-ahead.dts index 425f07d73b32..497d961456f3 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -45,10 +45,6 @@ &osc_32k { clock-frequency =3D <32768>; }; =20 -&spi_clk { - clock-frequency =3D <396000000>; -}; - &dmac0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/= riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index 077dbbe4abb6..78977bdbbe3d 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -25,10 +25,6 @@ &osc_32k { clock-frequency =3D <32768>; }; =20 -&spi_clk { - clock-frequency =3D <396000000>; -}; - &dmac0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index 5f4f94ca9cc7..6992060e6a54 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -216,12 +216,6 @@ osc_32k: 32k-oscillator { #clock-cells =3D <0>; }; =20 - spi_clk: spi-clock { - compatible =3D "fixed-clock"; - clock-output-names =3D "spi_clk"; - #clock-cells =3D <0>; - }; - soc { compatible =3D "simple-bus"; interrupt-parent =3D <&plic>; @@ -256,7 +250,7 @@ spi0: spi@ffe700c000 { compatible =3D "thead,th1520-spi", "snps,dw-apb-ssi"; reg =3D <0xff 0xe700c000 0x0 0x1000>; interrupts =3D <54 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&spi_clk>; + clocks =3D <&clk CLK_SPI>; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; --=20 2.34.1