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Wed, 31 Jul 2024 15:28:40 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-44fe8416c80sm62359181cf.96.2024.07.31.15.28.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jul 2024 15:28:39 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Philipp Zabel , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 04/12] PCI: brcmstb: Use bridge reset if available Date: Wed, 31 Jul 2024 18:28:18 -0400 Message-Id: <20240731222831.14895-5-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240731222831.14895-1-james.quinlan@broadcom.com> References: <20240731222831.14895-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The 7712 SOC has a bridge reset which can be described in the device tree. Use it if present. Otherwise, continue to use the legacy method to reset the bridge. Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/pcie-brcmstb.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 7595e7009192..4d68fe318178 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -265,6 +265,7 @@ struct brcm_pcie { enum pcie_type type; struct reset_control *rescal; struct reset_control *perst_reset; + struct reset_control *bridge_reset; int num_memc; u64 memc_size[PCIE_BRCM_MAX_MEMC]; u32 hw_rev; @@ -732,12 +733,19 @@ static void __iomem *brcm7425_pcie_map_bus(struct pci= _bus *bus, =20 static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u= 32 val) { - u32 tmp, mask =3D RGR1_SW_INIT_1_INIT_GENERIC_MASK; - u32 shift =3D RGR1_SW_INIT_1_INIT_GENERIC_SHIFT; + if (val) + reset_control_assert(pcie->bridge_reset); + else + reset_control_deassert(pcie->bridge_reset); =20 - tmp =3D readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); - tmp =3D (tmp & ~mask) | ((val << shift) & mask); - writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); + if (!pcie->bridge_reset) { + u32 tmp, mask =3D RGR1_SW_INIT_1_INIT_GENERIC_MASK; + u32 shift =3D RGR1_SW_INIT_1_INIT_GENERIC_SHIFT; + + tmp =3D readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); + tmp =3D (tmp & ~mask) | ((val << shift) & mask); + writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); + } } =20 static void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 = val) @@ -1621,10 +1629,16 @@ static int brcm_pcie_probe(struct platform_device *= pdev) if (IS_ERR(pcie->perst_reset)) return PTR_ERR(pcie->perst_reset); =20 + pcie->bridge_reset =3D devm_reset_control_get_optional_exclusive(&pdev->d= ev, "bridge"); + if (IS_ERR(pcie->bridge_reset)) + return PTR_ERR(pcie->bridge_reset); + ret =3D clk_prepare_enable(pcie->clk); if (ret) return dev_err_probe(&pdev->dev, ret, "could not enable clock\n"); =20 + pcie->bridge_sw_init_set(pcie, 0); + ret =3D reset_control_reset(pcie->rescal); if (dev_err_probe(&pdev->dev, ret, "failed to deassert 'rescal'\n")) goto clk_disable_unprepare; --=20 2.17.1