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Wed, 31 Jul 2024 15:28:49 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-44fe8416c80sm62359181cf.96.2024.07.31.15.28.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jul 2024 15:28:48 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Philipp Zabel , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 10/12] PCI: brcmstb: Check return value of all reset_control_xxx calls Date: Wed, 31 Jul 2024 18:28:24 -0400 Message-Id: <20240731222831.14895-11-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240731222831.14895-1-james.quinlan@broadcom.com> References: <20240731222831.14895-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Always check the return value for invocations of reset_control_xxx() and propagate the error to the next level. Although the current functions in reset-brcmstb.c cannot fail, this may someday change. Signed-off-by: Jim Quinlan Reviewed-by: Stanimir Varbanov Reviewed-by: Florian Fainelli Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/pcie-brcmstb.c | 102 ++++++++++++++++++-------- 1 file changed, 73 insertions(+), 29 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 0ecca3d9576f..c4ceb1823a79 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -239,8 +239,8 @@ struct pcie_cfg_data { const enum pcie_type type; const bool has_phy; unsigned int num_inbound_wins; - void (*perst_set)(struct brcm_pcie *pcie, u32 val); - void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); + int (*perst_set)(struct brcm_pcie *pcie, u32 val); + int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); }; =20 struct subdev_regulators { @@ -285,8 +285,8 @@ struct brcm_pcie { int num_memc; u64 memc_size[PCIE_BRCM_MAX_MEMC]; u32 hw_rev; - void (*perst_set)(struct brcm_pcie *pcie, u32 val); - void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); + int (*perst_set)(struct brcm_pcie *pcie, u32 val); + int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); struct subdev_regulators *sr; bool ep_wakeup_capable; bool has_phy; @@ -749,12 +749,18 @@ static void __iomem *brcm7425_pcie_map_bus(struct pci= _bus *bus, return base + DATA_ADDR(pcie); } =20 -static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u= 32 val) +static int brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u3= 2 val) { + int ret =3D 0; + if (val) - reset_control_assert(pcie->bridge_reset); + ret =3D reset_control_assert(pcie->bridge_reset); else - reset_control_deassert(pcie->bridge_reset); + ret =3D reset_control_deassert(pcie->bridge_reset); + + if (ret) + dev_err(pcie->dev, "failed to %s 'bridge' reset, err=3D%d\n", + val ? "assert" : "deassert", ret); =20 if (!pcie->bridge_reset) { u32 tmp, mask =3D RGR1_SW_INIT_1_INIT_GENERIC_MASK; @@ -764,9 +770,11 @@ static void brcm_pcie_bridge_sw_init_set_generic(struc= t brcm_pcie *pcie, u32 val tmp =3D (tmp & ~mask) | ((val << shift) & mask); writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); } + + return ret; } =20 -static void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 = val) +static int brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 v= al) { u32 tmp, mask =3D RGR1_SW_INIT_1_INIT_7278_MASK; u32 shift =3D RGR1_SW_INIT_1_INIT_7278_SHIFT; @@ -774,20 +782,29 @@ static void brcm_pcie_bridge_sw_init_set_7278(struct = brcm_pcie *pcie, u32 val) tmp =3D readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); tmp =3D (tmp & ~mask) | ((val << shift) & mask); writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); + + return 0; } =20 -static void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val) +static int brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val) { + int ret; + if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n")) - return; + return -EINVAL; =20 if (val) - reset_control_assert(pcie->perst_reset); + ret =3D reset_control_assert(pcie->perst_reset); else - reset_control_deassert(pcie->perst_reset); + ret =3D reset_control_deassert(pcie->perst_reset); + + if (ret) + dev_err(pcie->dev, "failed to %s 'perst' reset, err=3D%d\n", + val ? "assert" : "deassert", ret); + return ret; } =20 -static void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val) +static int brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val) { u32 tmp; =20 @@ -795,15 +812,19 @@ static void brcm_pcie_perst_set_7278(struct brcm_pcie= *pcie, u32 val) tmp =3D readl(pcie->base + PCIE_MISC_PCIE_CTRL); u32p_replace_bits(&tmp, !val, PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK); writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); + + return 0; } =20 -static void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) +static int brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) { u32 tmp; =20 tmp =3D readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK); writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); + + return 0; } =20 static inline void set_bar(struct inbound_win *b, int *count, u64 size, @@ -1016,19 +1037,28 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) struct resource_entry *entry; u32 tmp, burst, aspm_support; int num_out_wins =3D 0, num_rc_bars =3D 0; - int memc; + int memc, ret; =20 /* Reset the bridge */ - pcie->bridge_sw_init_set(pcie, 1); + ret =3D pcie->bridge_sw_init_set(pcie, 1); + if (ret) + return ret; =20 /* Ensure that PERST# is asserted; some bootloaders may deassert it. */ - if (pcie->type =3D=3D BCM2711) - pcie->perst_set(pcie, 1); + if (pcie->type =3D=3D BCM2711) { + ret =3D pcie->perst_set(pcie, 1); + if (ret) { + pcie->bridge_sw_init_set(pcie, 0); + return ret; + } + } =20 usleep_range(100, 200); =20 /* Take the bridge out of reset */ - pcie->bridge_sw_init_set(pcie, 0); + ret =3D pcie->bridge_sw_init_set(pcie, 0); + if (ret) + return ret; =20 tmp =3D readl(base + HARD_DEBUG(pcie)); if (is_bmips(pcie)) @@ -1247,7 +1277,9 @@ static int brcm_pcie_start_link(struct brcm_pcie *pci= e) int ret, i; =20 /* Unassert the fundamental reset */ - pcie->perst_set(pcie, 0); + ret =3D pcie->perst_set(pcie, 0); + if (ret) + return ret; =20 /* * Wait for 100ms after PERST# deassertion; see PCIe CEM specification @@ -1439,15 +1471,17 @@ static inline int brcm_phy_stop(struct brcm_pcie *p= cie) return pcie->has_phy ? brcm_phy_cntl(pcie, 0) : 0; } =20 -static void brcm_pcie_turn_off(struct brcm_pcie *pcie) +static int brcm_pcie_turn_off(struct brcm_pcie *pcie) { void __iomem *base =3D pcie->base; - int tmp; + int tmp, ret; =20 if (brcm_pcie_link_up(pcie)) brcm_pcie_enter_l23(pcie); /* Assert fundamental reset */ - pcie->perst_set(pcie, 1); + ret =3D pcie->perst_set(pcie, 1); + if (ret) + return ret; =20 /* Deassert request for L23 in case it was asserted */ tmp =3D readl(base + PCIE_MISC_PCIE_CTRL); @@ -1460,7 +1494,9 @@ static void brcm_pcie_turn_off(struct brcm_pcie *pcie) writel(tmp, base + HARD_DEBUG(pcie)); =20 /* Shutdown PCIe bridge */ - pcie->bridge_sw_init_set(pcie, 1); + ret =3D pcie->bridge_sw_init_set(pcie, 1); + + return ret; } =20 static int pci_dev_may_wakeup(struct pci_dev *dev, void *data) @@ -1478,9 +1514,12 @@ static int brcm_pcie_suspend_noirq(struct device *de= v) { struct brcm_pcie *pcie =3D dev_get_drvdata(dev); struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(pcie); - int ret; + int ret, rret; + + ret =3D brcm_pcie_turn_off(pcie); + if (ret) + return ret; =20 - brcm_pcie_turn_off(pcie); /* * If brcm_phy_stop() returns an error, just dev_err(). If we * return the error it will cause the suspend to fail and this is a @@ -1509,7 +1548,10 @@ static int brcm_pcie_suspend_noirq(struct device *de= v) pcie->sr->supplies); if (ret) { dev_err(dev, "Could not turn off regulators\n"); - reset_control_reset(pcie->rescal); + rret =3D reset_control_reset(pcie->rescal); + if (rret) + dev_err(dev, "failed to reset 'rascal' controller ret=3D%d\n", + rret); return ret; } } @@ -1524,7 +1566,7 @@ static int brcm_pcie_resume_noirq(struct device *dev) struct brcm_pcie *pcie =3D dev_get_drvdata(dev); void __iomem *base; u32 tmp; - int ret; + int ret, rret; =20 base =3D pcie->base; ret =3D clk_prepare_enable(pcie->clk); @@ -1586,7 +1628,9 @@ static int brcm_pcie_resume_noirq(struct device *dev) if (pcie->sr) regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies); err_reset: - reset_control_rearm(pcie->rescal); + rret =3D reset_control_rearm(pcie->rescal); + if (rret) + dev_err(pcie->dev, "failed to rearm 'rescal' reset, err=3D%d\n", rret); err_disable_clk: clk_disable_unprepare(pcie->clk); return ret; --=20 2.17.1