From nobody Sat Feb 7 16:26:36 2026 Received: from mail-qt1-f170.google.com (mail-qt1-f170.google.com [209.85.160.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C542A16D4E4 for ; Wed, 31 Jul 2024 22:28:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722464918; cv=none; b=hjOpJJcZAFA2Os3c0aFfYGb5IkuRdvpWGVD2HLESWdz4YseGv1Lhc9pVOWkt4VJKQdAsCP1iUGPXy00gM4rLEVNtz6YY7zXxNlfVVWL5FNrV4m8f4jrkj97W16VuKLJcj5Clb8l+2P5d1RuyEhnUuHWIobLyaqa/DttZUJxowXQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722464918; c=relaxed/simple; bh=xOGWNuaAupIgwPdS/rgbsjpjtqFXk6aLgk37BeHc+W8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=D+NC5YLFPvdurSwE2JClAulhbjb1SYDNYaCB98o6WHNu5JgUyyKQck7yuipknONScpT7yHbNYmVfRSZeS9HQ9dNruzjLHSiAOjFp8VcRagXi581iXYWdQXGVQLgyQSOkYL5MQLUMOaaQcP//8RFcHwsfgXWS17bBxnAu+EgCQfU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=DcfzGJv2; arc=none smtp.client-ip=209.85.160.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="DcfzGJv2" Received: by mail-qt1-f170.google.com with SMTP id d75a77b69052e-44fded90c41so33524341cf.3 for ; Wed, 31 Jul 2024 15:28:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1722464916; x=1723069716; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=b8cbkrXOvR65c0gzParSa3KyQFx/V1Yolb4QWEqbLeU=; b=DcfzGJv2t5cjo2d/zEOlWrQFvfvyOeBRtZqIE1mlPnGStKWv6fKIVgIdRgJt8A7/Tg s6XfO1X1q+9LUP0BZvCdnJUNN1Wj44F4QqHCnGKF6Rm/UV45KJmZ/iJ0au+ZyAJjRtZO 5g8dwXbfGvSWFcklB+l0k/axfboqnNeFn/b/c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722464916; x=1723069716; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=b8cbkrXOvR65c0gzParSa3KyQFx/V1Yolb4QWEqbLeU=; b=NWI830AVT7QPslu0CPD1f/AV5tj/a7e6p1D0sbUuMw6eirL/bWt1M3CUBlsmnaD/fA 2QVN7WT3Wvjy2lNb2AL78+PRIV7YDky76y7qkSlqH4pHnljP2S7jGU2OVIUUvBvuHcwQ GDgq5e1YFrxu/j/r9ux/uWdaITVbMncX03eEKTEhDXk4NnH/jj81Qenh3XhwsRBmv5iZ nClHDZD0AcMnV9huXEkoFofMzkzXkPEJVSER6AqODYTJA6K2mjbH9LC1GOcpCFTRrMvL a/pAEApSMpnbMdwI9JqHrz/VedrRLr+lHo/QSCNsH2k0zeP/+mIEoZJTFm9UvEOrRk+e H5KA== X-Forwarded-Encrypted: i=1; AJvYcCXfbaW3Ehwe066T0l3mNUvo87Uw7VosB+BBEgig59uTcXc4Dffv7IQldJ3cjXkKyVG7zHWoeK6wy038fls6GqEn6Quz+/8XY0vLhGik X-Gm-Message-State: AOJu0YwiQ1mkQ14UEWWckGq0aIqMzD9sDF/4r4uJvZeHPYyXxHiMfkCl q6kdRMfVrSU0+Hl1m599I/ta1CjcTXXC3n0ddl7CfXSRnNE7B66tXY0z4D0LBQ== X-Google-Smtp-Source: AGHT+IEZ5zlpgTPjR0UxwHUMdNEmwri4DDnsPSxdW+UrsEfbtq1R2jA2OMG2gatPXhIqCCj0RHIJBQ== X-Received: by 2002:a05:622a:548c:b0:44f:dcd2:613a with SMTP id d75a77b69052e-45167d0eaabmr7880061cf.41.1722464915714; Wed, 31 Jul 2024 15:28:35 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-44fe8416c80sm62359181cf.96.2024.07.31.15.28.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jul 2024 15:28:35 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE), linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 01/12] dt-bindings: PCI: Cleanup of brcmstb YAML and add 7712 SoC Date: Wed, 31 Jul 2024 18:28:15 -0400 Message-Id: <20240731222831.14895-2-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240731222831.14895-1-james.quinlan@broadcom.com> References: <20240731222831.14895-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" o Change order of the compatible strings to be alphabetical o Use "maxItems" where needed. o Change maintainer: Nicolas has not been active for a while. It also makes sense for a Broadcom employee to be the maintainer as many of the details are privy to Broadcom. Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli --- .../devicetree/bindings/pci/brcm,stb-pcie.yaml | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Doc= umentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index 11f8ea33240c..7d2552192153 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Brcmstb PCIe Host Controller =20 maintainers: - - Nicolas Saenz Julienne + - Jim Quinlan =20 properties: compatible: @@ -16,11 +16,11 @@ properties: - brcm,bcm2711-pcie # The Raspberry Pi 4 - brcm,bcm4908-pcie - brcm,bcm7211-pcie # Broadcom STB version of RPi4 - - brcm,bcm7278-pcie # Broadcom 7278 Arm - brcm,bcm7216-pcie # Broadcom 7216 Arm - - brcm,bcm7445-pcie # Broadcom 7445 Arm + - brcm,bcm7278-pcie # Broadcom 7278 Arm - brcm,bcm7425-pcie # Broadcom 7425 MIPs - brcm,bcm7435-pcie # Broadcom 7435 MIPs + - brcm,bcm7445-pcie # Broadcom 7445 Arm =20 reg: maxItems: 1 @@ -95,6 +95,12 @@ properties: minItems: 1 maxItems: 3 =20 + resets: + maxItems: 1 + + reset-names: + maxItems: 1 + required: - compatible - reg @@ -118,8 +124,7 @@ allOf: then: properties: resets: - items: - - description: reset controller handling the PERST# signal + maxItems: 1 =20 reset-names: items: @@ -136,8 +141,7 @@ allOf: then: properties: resets: - items: - - description: phandle pointing to the RESCAL reset controller + maxItems: 1 =20 reset-names: items: --=20 2.17.1 From nobody Sat Feb 7 16:26:36 2026 Received: from mail-ot1-f49.google.com (mail-ot1-f49.google.com [209.85.210.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 436D316D9BD for ; Wed, 31 Jul 2024 22:28:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722464919; cv=none; b=CpT33AxE0sb5So8bpUZEMXMFb06xghGnEoVxrr2IBSznyW4/OQcBzolB5x1Yd2vIMB3TrYjSEh48VfjvaAKf1jZkNj+k7TP5zVM6pTI3GsZmKGNk9oJay25nKmt5ga5V4OhYPvxkW1IzRn9tsvd6AAjMW4YzOk1qQYV348lvTmk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722464919; c=relaxed/simple; bh=mAoM+jm0P713mKZxMhykPOMr8VcVpW3lJ0JPpibSWzM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=d3U/DYEvy1+gu3G3e8aMd3MM+HHEb31/FxjPKkl3XxlyaaRAgkeEJ96tjAHsUKrONwxd9ipcwVnjRbJixJfIh7cYdT55VLJb1mLd8lggfAkEHIPZuqeVVjVmvjacHxNrElc5/DwlbuCTZccShbC7CoNmcFRP6i6LrjRbyIxpnkQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=RXeyd7CV; arc=none smtp.client-ip=209.85.210.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="RXeyd7CV" Received: by mail-ot1-f49.google.com with SMTP id 46e09a7af769-70940c9657dso3214268a34.1 for ; Wed, 31 Jul 2024 15:28:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1722464917; x=1723069717; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=MEzSqlnsH2j9tRB5+9ly7frUJhXv2tJmhe1jZ23vhJ0=; b=RXeyd7CVF82M+8IeZtSpbzFhBrQKqFvVlxy9Mt4trRy1ahUJugA0vBwBxA+MKjbCIa N3hv3utV370A59jTjbrn0Mlt+IeHJQTQhBvXgIh/fizqbJO4kB2FAYcVA+/jSnNvRLeM tuJOKgIIXoo1+vsjtMXVSMJZCFLZQWDBXifQY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722464917; x=1723069717; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=MEzSqlnsH2j9tRB5+9ly7frUJhXv2tJmhe1jZ23vhJ0=; b=S8nZpcpHMsKGxDDOwlJ/6wHXVXEiESlaWJJqJ6QzuRQU/VSpozve4QhGkgoxW/PU5Z pwyk9hivEC0SuL5kqw2cT4uJ9yRct1F7AlUXT1uhOILb6UfzaLBOuvVW8kzi7EhlV7z5 tnkvuhMPZ0jNmkWUDpkgnaue65MmirUR/Pr1ukbMiOwpIM9O8Pq4OwY8GHMHC8hlUSDP Vb2ciSaUx9wflCPew9t000xF1Xz7bJP5jEKOAM6uBaURx4DClZGXwLlMJ1mfV5+OWNQ9 vswF6c7PIAmsKKB6bB1/aVlRm0xizWn1GkM8A8tOyU2FGaGNotrzNReizAtQbrp26leN Pdgw== X-Forwarded-Encrypted: i=1; AJvYcCVdlDcXjaOflZA3X29MwW8ASDTeFHtJT+NeifD7Buf8AEb499h+NZ0wg2zvwnN973bq6MbGSVgS0Rp6IiSv63Yh1LN0KeLC3ASW588+ X-Gm-Message-State: AOJu0YzT1uSI7hpZhFyLB512cdLiasenq5JVj4Aw/KNjuVL+eGezQx7e fm6SPFIJpMZmF/X20F5mMKwY4iznroLCMFm0aQ2+rZo/VPAGh3dernqLKt9g7Q== X-Google-Smtp-Source: AGHT+IHhsa4xXStr5djydA447oqZ0eywB6dQmFgO7T5029BQXALrAgyEhVKlX9qDw4OJNWb9FlBZHQ== X-Received: by 2002:a05:6830:dc2:b0:709:441a:351b with SMTP id 46e09a7af769-7096b7da64cmr506886a34.8.1722464917301; Wed, 31 Jul 2024 15:28:37 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-44fe8416c80sm62359181cf.96.2024.07.31.15.28.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jul 2024 15:28:36 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE), linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 02/12] dt-bindings: PCI: brcmstb: Add 7712 SoC description Date: Wed, 31 Jul 2024 18:28:16 -0400 Message-Id: <20240731222831.14895-3-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240731222831.14895-1-james.quinlan@broadcom.com> References: <20240731222831.14895-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add description for the 7712 SoC, a Broadcom STB sibling chip of the RPi 5. The 7712 uses three reset controllers: rescal, for phy reset calibration; bridge, for the bridge between the PCIe bus and the memory bus; and swinit, which is a "soft" initialization of the PCIe HW. Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli Reviewed-by: Krzysztof Kozlowski --- .../bindings/pci/brcm,stb-pcie.yaml | 28 +++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Doc= umentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index 7d2552192153..0925c520195a 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -21,6 +21,7 @@ properties: - brcm,bcm7425-pcie # Broadcom 7425 MIPs - brcm,bcm7435-pcie # Broadcom 7435 MIPs - brcm,bcm7445-pcie # Broadcom 7445 Arm + - brcm,bcm7712-pcie # Broadcom STB sibling of Rpi 5 =20 reg: maxItems: 1 @@ -96,10 +97,12 @@ properties: maxItems: 3 =20 resets: - maxItems: 1 + minItems: 1 + maxItems: 3 =20 reset-names: - maxItems: 1 + minItems: 1 + maxItems: 3 =20 required: - compatible @@ -151,6 +154,27 @@ allOf: - resets - reset-names =20 + - if: + properties: + compatible: + contains: + const: brcm,bcm7712-pcie + then: + properties: + resets: + minItems: 3 + maxItems: 3 + + reset-names: + items: + - const: rescal + - const: bridge + - const: swinit + + required: + - resets + - reset-names + unevaluatedProperties: false =20 examples: --=20 2.17.1 From nobody Sat Feb 7 16:26:36 2026 Received: from mail-ot1-f46.google.com (mail-ot1-f46.google.com [209.85.210.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B46EE16DC1F for ; Wed, 31 Jul 2024 22:28:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722464921; cv=none; b=gicFP/rit9JDqUjisD79TzgdpVx75q7bKbiHaK+G4Gz7LaQB1yuR0t4u9x8lS6tGNCWEWXywrmK7/2uZEsQs/vZltY/G+JYSN2mRk+1QTtyuTArLJpH688g0wzcAvAQG2c6HDyPtVl8ijx371+0bTM6P2XQjmmdhF/f200Mb9kI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722464921; c=relaxed/simple; bh=tXTAjZtcWhewtsJ5mnN9e2cBSHCNX3dQ2tHxYaPUuhA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=Z1/Gyfs6deYvnMk+NSizRW4v8IHVgaYNlRy62XzkXYLGXdEhOuSqjWosIIneTOuGOsEIJNoRgqZ45uY1p9i5RZrssmscM13lAY3gzz22KjWjOllTDvq2jIQ19KX3B91a3Lj/KXZopBXc4pNw8iOg3Hkz5KhEziCTvm4J6D0bBuY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=hruA2eJ+; arc=none smtp.client-ip=209.85.210.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="hruA2eJ+" Received: by mail-ot1-f46.google.com with SMTP id 46e09a7af769-7094468d392so2585824a34.0 for ; Wed, 31 Jul 2024 15:28:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1722464919; x=1723069719; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=J83Zv5BEREvIAUqofWicGKSSTCWUlV2zoywp7ximAEQ=; b=hruA2eJ+kRepZRi+HwCoZdNH6HaXyhU+vNCyXqnWvpQ5cT1C3a1OtG6BjgeRblHmjL Hw8PSNAKBIm4emrjNcMKw/kHY6qv6eE6xJ174TWfy+4NWQjHADrxHYJCczEQ5nV7O7fp X7ILbI6rqPp4u7A+le2dh+JqvryGxO1t4ObBA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722464919; x=1723069719; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=J83Zv5BEREvIAUqofWicGKSSTCWUlV2zoywp7ximAEQ=; b=TSHQxT8ajavrP+E24K8Hb7oXglQ2mzajnEO7D7o6hFNou1o1ENc7qTClsKfKpBPkX5 0kHe+Gzs2wTsyrEy/9sWnUrppywfVbKFRkAlG+JCy3fOowNDCS4K0oSVEeIgzTeBl6cz k+5vZQV3685P2YWkdsmQORWw10bw2At2nOBmPalqpSiG5P92ZWSbXPNwJguVZBwfEPO4 eWI50+p4rThiT5luHxcVjbO1wrDrV+Hz0H3Nt5WzpyGth/BqCNMETlM90bDcHX+fpcdA JDikbzgONYecZkLujMNRKyMjEdneEvCjHNLR82t9a35/enZJ+AxiiVkJyG+C4mtZGA+6 3Oog== X-Forwarded-Encrypted: i=1; AJvYcCVsoP6tzjFageDPtmEUb+e5GqPXnK+oA+Q/Mn79+E5HQwd0ZG5Iuu4oLPqmI0B+AZEMkmPgCBDw/71FpvbDoik7AfH4SfW/6lASlnR7 X-Gm-Message-State: AOJu0Ywu2hRS5lQYVSm9bwTf7tba+ZzrEYxhEPzkiLWdfsP1n2ZHkhXv YeWcr2UbZFH4/bMuq2MqpNx47PQ9NTI6O661ncJYVFrHlODxUIMv3xyF3fhpWQ== X-Google-Smtp-Source: AGHT+IHIP5WdHy/ihYegTa0DgMvLcOxm3pAjIV58KNh8m6EZyfzcAcqiHesM2kvbR33Jn8f0UeLyNA== X-Received: by 2002:a05:6830:6c0e:b0:709:44dc:dde7 with SMTP id 46e09a7af769-7096b8054afmr717661a34.9.1722464918795; Wed, 31 Jul 2024 15:28:38 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-44fe8416c80sm62359181cf.96.2024.07.31.15.28.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jul 2024 15:28:38 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Philipp Zabel , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 03/12] PCI: brcmstb: Use common error handling code in brcm_pcie_probe() Date: Wed, 31 Jul 2024 18:28:17 -0400 Message-Id: <20240731222831.14895-4-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240731222831.14895-1-james.quinlan@broadcom.com> References: <20240731222831.14895-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" o Move the clk_prepare_enable() below the resource allocations. o Move the clk_prepare_enable() out of __brcm_pcie_remove() but add it to the end of brcm_pcie_remove(). o Add a jump target (clk_disable_unprepare) so that a bit of exception handling can be better reused at the end of this function implementation. o Use dev_err_probe() where it makes sense. Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 34 ++++++++++++--------------- 1 file changed, 15 insertions(+), 19 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index c08683febdd4..7595e7009192 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -1473,7 +1473,6 @@ static void __brcm_pcie_remove(struct brcm_pcie *pcie) dev_err(pcie->dev, "Could not stop phy\n"); if (reset_control_rearm(pcie->rescal)) dev_err(pcie->dev, "Could not rearm rescal reset\n"); - clk_disable_unprepare(pcie->clk); } =20 static void brcm_pcie_remove(struct platform_device *pdev) @@ -1484,6 +1483,7 @@ static void brcm_pcie_remove(struct platform_device *= pdev) pci_stop_root_bus(bridge->bus); pci_remove_root_bus(bridge->bus); __brcm_pcie_remove(pcie); + clk_disable_unprepare(pcie->clk); } =20 static const int pcie_offsets[] =3D { @@ -1613,31 +1613,26 @@ static int brcm_pcie_probe(struct platform_device *= pdev) =20 pcie->ssc =3D of_property_read_bool(np, "brcm,enable-ssc"); =20 - ret =3D clk_prepare_enable(pcie->clk); - if (ret) { - dev_err(&pdev->dev, "could not enable clock\n"); - return ret; - } pcie->rescal =3D devm_reset_control_get_optional_shared(&pdev->dev, "resc= al"); - if (IS_ERR(pcie->rescal)) { - clk_disable_unprepare(pcie->clk); + if (IS_ERR(pcie->rescal)) return PTR_ERR(pcie->rescal); - } + pcie->perst_reset =3D devm_reset_control_get_optional_exclusive(&pdev->de= v, "perst"); - if (IS_ERR(pcie->perst_reset)) { - clk_disable_unprepare(pcie->clk); + if (IS_ERR(pcie->perst_reset)) return PTR_ERR(pcie->perst_reset); - } =20 - ret =3D reset_control_reset(pcie->rescal); + ret =3D clk_prepare_enable(pcie->clk); if (ret) - dev_err(&pdev->dev, "failed to deassert 'rescal'\n"); + return dev_err_probe(&pdev->dev, ret, "could not enable clock\n"); + + ret =3D reset_control_reset(pcie->rescal); + if (dev_err_probe(&pdev->dev, ret, "failed to deassert 'rescal'\n")) + goto clk_disable_unprepare; =20 ret =3D brcm_phy_start(pcie); if (ret) { reset_control_rearm(pcie->rescal); - clk_disable_unprepare(pcie->clk); - return ret; + goto clk_disable_unprepare; } =20 ret =3D brcm_pcie_setup(pcie); @@ -1654,10 +1649,8 @@ static int brcm_pcie_probe(struct platform_device *p= dev) msi_np =3D of_parse_phandle(pcie->np, "msi-parent", 0); if (pci_msi_enabled() && msi_np =3D=3D pcie->np) { ret =3D brcm_pcie_enable_msi(pcie); - if (ret) { - dev_err(pcie->dev, "probe of internal MSI failed"); + if (dev_err_probe(pcie->dev, ret, "probe of internal MSI failed")) goto fail; - } } =20 bridge->ops =3D pcie->type =3D=3D BCM7425 ? &brcm7425_pcie_ops : &brcm_pc= ie_ops; @@ -1678,6 +1671,9 @@ static int brcm_pcie_probe(struct platform_device *pd= ev) =20 fail: __brcm_pcie_remove(pcie); +clk_disable_unprepare: + clk_disable_unprepare(pcie->clk); + return ret; } =20 --=20 2.17.1 From nobody Sat Feb 7 16:26:36 2026 Received: from mail-qt1-f171.google.com (mail-qt1-f171.google.com [209.85.160.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E1ED16DECD for ; Wed, 31 Jul 2024 22:28:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722464923; cv=none; b=bR6hRNAX78d+LiSh8cC3y3J1DUdoAmlyg2i/TVypVONRDs+pHOSPbnnETKIQsoCQrdcxlvcMt+v3PMNQdjt6R84my9FlbIGz3PjnKF2BtPpXWMj/+vLXPD88XhDdRtClwx49gZC8I0lu76+VHwUmQXWKtMqjpfZ8YAmKcGNP6Kg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722464923; c=relaxed/simple; bh=XABkIvkgFRWEK75ywChcUI9iJgm62PnlqcP6SvDCSlo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=m1NCaMU2rHGREZ85MUqI85rNNudCd/4mP6HSWLLJoKXI7iE1fhfe9RAX1OLv5Z1KS7yr3atlIfaHwfFYWG2O4It0BSFkN/0lpDX1vIkQz900IVBMl6fvTKVriisLDsCpsY//ON7se9iwNmqNc82zv1Bws9c1LFjTmQ14gxTGMUs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=OgdIVUvz; arc=none smtp.client-ip=209.85.160.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="OgdIVUvz" Received: by mail-qt1-f171.google.com with SMTP id d75a77b69052e-44ff7bdb5a6so31924441cf.3 for ; Wed, 31 Jul 2024 15:28:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1722464920; x=1723069720; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=WKU/C7t+A6Qxg3BQxfQdxyrXxjr78aUecg8SreaTGI0=; b=OgdIVUvzdU2pYRGnMoDJ0qGRxCUD0uOwAWzxPu3546VAp+QQPAd3fLp/rDuWAepoe9 7qMeUI2cVt79bcp3gVNpONehYCHaF8JpFj877JgzoIiwFw1mumeP/WP3SY+CUnjL0MZl yZiDm3yPabrfn/WxyM6ik8zN3KcX8p6JzJCXs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722464920; x=1723069720; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=WKU/C7t+A6Qxg3BQxfQdxyrXxjr78aUecg8SreaTGI0=; b=o00dX/P7Pit+wEc2652JyyWLyVaOitKKvJ3PfdCm5X4AM/RLznFnlsX8pC1FKQWs0+ GNSiOpxXQNd0hcyGRTOd9LBUze7pVBR6y6omIeawTK6x2N3Mje+NY6OoSWwEmuKT448r z/h/TrNRXL74jirTPediKq86ZcBo6o930ILOTZSlB/rUH9yugzsnWLncXc7BHFSIPF6j wxf2f6oLrMUwufLKk2Nj4QemNb+euT+UoUUl6S3qC+Zt55lVUwaFq2SPHLEZlexnz9vq i5JVRfoe73wst2ubICKqn7ZB+mM//e5Ou4GF1PZGP1f9xOYuVo4zfHSNxoqddJVgpKoS Exuw== X-Forwarded-Encrypted: i=1; AJvYcCVBl/e2HYCb/If4psZDDGqOn+5XJ/qOCN/a2UP6kjCS/tqd4NLrGUgb4oxNNKq5VxNXpg8eGdRfRpQ6LKKNFJ4PEfoqV8f6XQfmqDej X-Gm-Message-State: AOJu0YzBL/I/y1RDbGYmFEW/WF9uqgH61dVpTqiolXIFGrMFqrEy0Tsn /uK1ofxRT8iD/+5TfbCYprywx4sBs8xEMfnVeYin0mWHe4QocE3ckSAGuDtQqL/Gzzj/iQN5nZw = X-Google-Smtp-Source: AGHT+IH5WIAKBTNzHOk2cOY6cbJUFfh9InV6VDCil+I8iLVSY6sNMvSKIX+eU+Wup3PUxdLc/xIMzQ== X-Received: by 2002:ac8:7f8d:0:b0:445:2e9:330e with SMTP id d75a77b69052e-4514f9a2ea4mr8919321cf.37.1722464920281; Wed, 31 Jul 2024 15:28:40 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-44fe8416c80sm62359181cf.96.2024.07.31.15.28.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jul 2024 15:28:39 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Philipp Zabel , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 04/12] PCI: brcmstb: Use bridge reset if available Date: Wed, 31 Jul 2024 18:28:18 -0400 Message-Id: <20240731222831.14895-5-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240731222831.14895-1-james.quinlan@broadcom.com> References: <20240731222831.14895-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The 7712 SOC has a bridge reset which can be described in the device tree. Use it if present. Otherwise, continue to use the legacy method to reset the bridge. Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/pcie-brcmstb.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 7595e7009192..4d68fe318178 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -265,6 +265,7 @@ struct brcm_pcie { enum pcie_type type; struct reset_control *rescal; struct reset_control *perst_reset; + struct reset_control *bridge_reset; int num_memc; u64 memc_size[PCIE_BRCM_MAX_MEMC]; u32 hw_rev; @@ -732,12 +733,19 @@ static void __iomem *brcm7425_pcie_map_bus(struct pci= _bus *bus, =20 static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u= 32 val) { - u32 tmp, mask =3D RGR1_SW_INIT_1_INIT_GENERIC_MASK; - u32 shift =3D RGR1_SW_INIT_1_INIT_GENERIC_SHIFT; + if (val) + reset_control_assert(pcie->bridge_reset); + else + reset_control_deassert(pcie->bridge_reset); =20 - tmp =3D readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); - tmp =3D (tmp & ~mask) | ((val << shift) & mask); - writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); + if (!pcie->bridge_reset) { + u32 tmp, mask =3D RGR1_SW_INIT_1_INIT_GENERIC_MASK; + u32 shift =3D RGR1_SW_INIT_1_INIT_GENERIC_SHIFT; + + tmp =3D readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); + tmp =3D (tmp & ~mask) | ((val << shift) & mask); + writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); + } } =20 static void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 = val) @@ -1621,10 +1629,16 @@ static int brcm_pcie_probe(struct platform_device *= pdev) if (IS_ERR(pcie->perst_reset)) return PTR_ERR(pcie->perst_reset); =20 + pcie->bridge_reset =3D devm_reset_control_get_optional_exclusive(&pdev->d= ev, "bridge"); + if (IS_ERR(pcie->bridge_reset)) + return PTR_ERR(pcie->bridge_reset); + ret =3D clk_prepare_enable(pcie->clk); if (ret) return dev_err_probe(&pdev->dev, ret, "could not enable clock\n"); =20 + pcie->bridge_sw_init_set(pcie, 0); + ret =3D reset_control_reset(pcie->rescal); if (dev_err_probe(&pdev->dev, ret, "failed to deassert 'rescal'\n")) goto clk_disable_unprepare; --=20 2.17.1 From nobody Sat Feb 7 16:26:36 2026 Received: from mail-qt1-f182.google.com (mail-qt1-f182.google.com [209.85.160.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2BBD16E88C for ; Wed, 31 Jul 2024 22:28:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722464924; cv=none; b=K2l1kATXY8naab2ElL0FrLm6eH30zeBtwlHcwpyB0bzcHp2QIwy6+wNViKeECVspe11msYzZHq/R5XNMPUA3fyV+M+CulBChzIn3y4QG9em9AsH6j4V21iSrsnDz1z4YXSSLeASppWrDt4M3Dfa3goCeIwOoKTwLwLxfIdmsb1Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722464924; c=relaxed/simple; bh=ohxTxIMDhY1ATcgdpM1JyttNCDtL0q2lDi0qmnU6oPc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=RFYcwRPSKcMES6BTqotocAgtW1gJxFIRxNiAEf8/Kxc8y21kkDhwH28/GpJP/IOi1rYjedq/tXM7UT4Gvhzibc5FhEdmHfCy+ARo6eYhA0TFJc5GWJ0y50hkva7iFcbB+0HOuC75xbKKwpowJl6dR2ASTZ9IGhAjPYzcrdQJJ/U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=gekSnrla; arc=none smtp.client-ip=209.85.160.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="gekSnrla" Received: by mail-qt1-f182.google.com with SMTP id d75a77b69052e-44ff6f3c427so29086921cf.1 for ; Wed, 31 Jul 2024 15:28:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1722464922; x=1723069722; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=BvkPsLOG5fUE2ytDC/96EogS/1H6a6HtgvVDjzytUG8=; b=gekSnrlaIcBasVelXAtPu0R+aEG5i5alx1+igVCPdMmZxNeQr95zRQy8HeESR51x+C 4oRS8Lnh1Jf5aiK5+a8HZuc1kK/+0Tom0vyCTrwg64zF+xO5COMFIEltT5WJi6qsJOV7 QQjT36VRLsRepI7Y7bz2SykaE2q//W+4lqPew= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722464922; x=1723069722; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=BvkPsLOG5fUE2ytDC/96EogS/1H6a6HtgvVDjzytUG8=; b=g7dAZP8YrBZ5jackY9WL8s/H6MIc6vtBGTGwQ0zqavV7jmygnRFSCIomDxFmGf4lz3 scEl3+0wwQDP21OZuFiqQZb65Gtwa97icUVl+di50P8v8nB2s7iKNZPX+unWDOKnkluh I4i9r0YLuDou955aTb52Z7dbOWJtGpqddGKdWAqtazBsc/AmYRYNR7uMh1OFZT4fAoeQ eBPLQDQy/b3CoKgc7wLjqG9MmW55ZaDXn6yQy+ZbjH2oD+CGcQspKBt9HLKGGlccVy8i sCWwB2RBe+6YZ8g96i3QhATxU7OFJRGx5hlC4XQfVApJyzM4JXGkkG6cBU4+RJQLkbu7 1hDg== X-Forwarded-Encrypted: i=1; AJvYcCXcTGeTbB0hFtOrICuOqenej6JJgGJsvh3Wux/oEshnQ5qHSczJvxBIoNHvFLu/afo+OtIl50a5uMOoxMw=@vger.kernel.org X-Gm-Message-State: AOJu0YzT6QnjYbYYvNRF26yAgeiqeTXLJFKbUI1pfPeYJWUJa5nlF/72 xgP5+sr59cB/2622WSlQO5DQAV6HysIlGLOMt+hl6ziEYIuMpwL0pD0JpELKEA== X-Google-Smtp-Source: AGHT+IFBtq3zfvlVDpCsnHiydXJF3wP25FYPP/JkCKWE8phEA2Y4P9A5CFNfuo6bGZRLAirUY+0/bA== X-Received: by 2002:ac8:7f87:0:b0:447:e542:ab00 with SMTP id d75a77b69052e-451567a84b4mr8510471cf.50.1722464921783; Wed, 31 Jul 2024 15:28:41 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-44fe8416c80sm62359181cf.96.2024.07.31.15.28.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jul 2024 15:28:41 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Philipp Zabel , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 05/12] PCI: brcmstb: Use swinit reset if available Date: Wed, 31 Jul 2024 18:28:19 -0400 Message-Id: <20240731222831.14895-6-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240731222831.14895-1-james.quinlan@broadcom.com> References: <20240731222831.14895-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The 7712 SOC adds a software init reset device for the PCIe HW. If found in the DT node, use it. Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 4d68fe318178..948fd4d176bc 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -266,6 +266,7 @@ struct brcm_pcie { struct reset_control *rescal; struct reset_control *perst_reset; struct reset_control *bridge_reset; + struct reset_control *swinit_reset; int num_memc; u64 memc_size[PCIE_BRCM_MAX_MEMC]; u32 hw_rev; @@ -1633,12 +1634,30 @@ static int brcm_pcie_probe(struct platform_device *= pdev) if (IS_ERR(pcie->bridge_reset)) return PTR_ERR(pcie->bridge_reset); =20 + pcie->swinit_reset =3D devm_reset_control_get_optional_exclusive(&pdev->d= ev, "swinit"); + if (IS_ERR(pcie->swinit_reset)) + return PTR_ERR(pcie->swinit_reset); + ret =3D clk_prepare_enable(pcie->clk); if (ret) return dev_err_probe(&pdev->dev, ret, "could not enable clock\n"); =20 pcie->bridge_sw_init_set(pcie, 0); =20 + if (pcie->swinit_reset) { + ret =3D reset_control_assert(pcie->swinit_reset); + if (dev_err_probe(&pdev->dev, ret, "could not assert reset 'swinit'\n")) + goto clk_disable_unprepare; + + /* HW team recommends 1us for proper sync and propagation of reset */ + udelay(1); + + ret =3D reset_control_deassert(pcie->swinit_reset); + if (dev_err_probe(&pdev->dev, ret, + "could not de-assert reset 'swinit' after asserting\n")) + goto clk_disable_unprepare; + } + ret =3D reset_control_reset(pcie->rescal); if (dev_err_probe(&pdev->dev, ret, "failed to deassert 'rescal'\n")) goto clk_disable_unprepare; --=20 2.17.1 From nobody Sat Feb 7 16:26:36 2026 Received: from mail-qt1-f180.google.com (mail-qt1-f180.google.com [209.85.160.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C17F16EB5C for ; Wed, 31 Jul 2024 22:28:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722464926; cv=none; b=tRXTpQqce3ASFue6u1dIDWMljeDo7pupEfYteAFbR8P1t6dGpUAXHoAL4+0nRzukCW8avLwKwSaNI4ZFV+lgNdkagLbeGJIQBJR/KztAcPK4LaUx+pLkVFN7TUttAnZs/8PX3YAaN0iuVGZoYedhZa/fZspif53KPdaziQgiGEI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722464926; c=relaxed/simple; bh=s1fh7f0lmM/Iaphg/fT8tq7g+OZlQdDIO9Songz0MXU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=jAduLfV7Cy157+W4SLUwyfxOJYcshNbfIO82CSmlWfO0YC93nCwJknwR1amljO3r6aaTxSBd23Po05cZfneo81LoZmjoWAT1paM/wjHKV1OPx9Nu6vNdQtMN1P5+SVDzCYUROQfLp121qYDXkLBItIpSFbHWYbY8d2rL4440BIo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=ZY+mXoHr; arc=none smtp.client-ip=209.85.160.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="ZY+mXoHr" Received: by mail-qt1-f180.google.com with SMTP id d75a77b69052e-44fe11dedb3so28446871cf.1 for ; Wed, 31 Jul 2024 15:28:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1722464923; x=1723069723; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=MXnrW2wZh+02qVnTjCR225qdcoHcBT0cTq9H5uoC8Ts=; b=ZY+mXoHrSXeHp0GzmeIWzokvVKBtogAdmHRqfq6lCVUqTG1v+zC+D6E3CeBVvQDl0v uN24Ejydde1Kr5nYfNtbl6wbzTp8+wBA0H95LxFFnaPnTZYf35gEI//x/2bSY3BwpEYH E7UNKWgy3ppdtBKID0QvdswtxX7+gH+1YxYu4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722464923; x=1723069723; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=MXnrW2wZh+02qVnTjCR225qdcoHcBT0cTq9H5uoC8Ts=; b=OfNbe0RwO8+LYiqPaL6mj8w+mAS0iMWKj53Gs1yODbM6R8o/qOsGHEJnG9vxCsQgjI Os4McoetK9EUo3dUncdqQzTtSZHyoCclruYKWAs8ku/inK7jwlf5YIztWFZjpAMiblHV /T1BJ3NGobW8Wc90nlOqLOrE//hR1GXhSgDPYDW+pjCkDs+B8IyHa9lNHBQQYrEdL/MX vPCDMT09y96pXvQlLjPgsR/MSSgf7hGxkE34gDoMIVB70seSGRGAaiA+v2BS2qR1JYXt /gOrkQ595oRFDzrEphZzFgUnMJ0RLq+yRnG3ngpavRywUvsRSS71o4PQ8qCBDeZi+C/o KjSA== X-Forwarded-Encrypted: i=1; AJvYcCXiLdOjSZChe0fSptWWDpe/BhY3hKpLYl7MVN+yw9NK60QQS4i1BswW3MqpCY2TYM+kTcu7i6f+7ofNDIur5/MEZrj/XLUUUG1eSxzg X-Gm-Message-State: AOJu0YxCFzn3sXooupNnppOaLbz9DPVhpdcsq438m2jzzET2ufmLgXFk ZuEe4CC7jSzIWZVsqZVoL/RM319xmBD/EYedpj6+KeNYtQW14Ipyf9MpsJ2WCw== X-Google-Smtp-Source: AGHT+IGpqHg8M4yPN3SsdyZANWJHE4R2f7s83hYUJdBqpCyFA+T5oHK7zAIU12me/Z/Bj/nc/ABqzQ== X-Received: by 2002:ac8:7dc6:0:b0:44f:fb58:8c3e with SMTP id d75a77b69052e-4514f9b69b1mr8004891cf.46.1722464923324; Wed, 31 Jul 2024 15:28:43 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-44fe8416c80sm62359181cf.96.2024.07.31.15.28.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jul 2024 15:28:42 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 06/12] PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG, INTR2_CPU_BASE offsets SoC-specific Date: Wed, 31 Jul 2024 18:28:20 -0400 Message-Id: <20240731222831.14895-7-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240731222831.14895-1-james.quinlan@broadcom.com> References: <20240731222831.14895-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Do prepatory work for the 7712 SoC, which is introduced in a future commit. Our HW design has changed two register offsets for the 7712, where previously it was a common value for all Broadcom SOCs with PCIe cores. Specifically, the two offsets are to the registers HARD_DEBUG and INTR2_CPU_BASE. Signed-off-by: Jim Quinlan Reviewed-by: Stanimir Varbanov Reviewed-by: Florian Fainelli Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/pcie-brcmstb.c | 39 ++++++++++++++++----------- 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 948fd4d176bc..9fa1500b8eee 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -122,7 +122,6 @@ #define PCIE_MEM_WIN0_LIMIT_HI(win) \ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8) =20 -#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK 0x200000 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 @@ -131,9 +130,9 @@ (PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK | \ PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK) =20 -#define PCIE_INTR2_CPU_BASE 0x4300 #define PCIE_MSI_INTR2_BASE 0x4500 -/* Offsets from PCIE_INTR2_CPU_BASE and PCIE_MSI_INTR2_BASE */ + +/* Offsets from INTR2_CPU and MSI_INTR2 BASE offsets */ #define MSI_INT_STATUS 0x0 #define MSI_INT_CLR 0x8 #define MSI_INT_MASK_SET 0x10 @@ -184,9 +183,11 @@ #define SSC_STATUS_PLL_LOCK_MASK 0x800 #define PCIE_BRCM_MAX_MEMC 3 =20 -#define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX]) -#define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA]) -#define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1]) +#define IDX_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_INDEX]) +#define DATA_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_DATA]) +#define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->reg_offsets[RGR1_SW_INIT_1]) +#define HARD_DEBUG(pcie) ((pcie)->reg_offsets[PCIE_HARD_DEBUG]) +#define INTR2_CPU_BASE(pcie) ((pcie)->reg_offsets[PCIE_INTR2_CPU_BASE]) =20 /* Rescal registers */ #define PCIE_DVT_PMU_PCIE_PHY_CTRL 0xc700 @@ -205,6 +206,8 @@ enum { RGR1_SW_INIT_1, EXT_CFG_INDEX, EXT_CFG_DATA, + PCIE_HARD_DEBUG, + PCIE_INTR2_CPU_BASE, }; =20 enum { @@ -651,7 +654,7 @@ static int brcm_pcie_enable_msi(struct brcm_pcie *pcie) BUILD_BUG_ON(BRCM_INT_PCI_MSI_LEGACY_NR > BRCM_INT_PCI_MSI_NR); =20 if (msi->legacy) { - msi->intr_base =3D msi->base + PCIE_INTR2_CPU_BASE; + msi->intr_base =3D msi->base + INTR2_CPU_BASE(pcie); msi->nr =3D BRCM_INT_PCI_MSI_LEGACY_NR; msi->legacy_shift =3D 24; } else { @@ -898,12 +901,12 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) /* Take the bridge out of reset */ pcie->bridge_sw_init_set(pcie, 0); =20 - tmp =3D readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + tmp =3D readl(base + HARD_DEBUG(pcie)); if (is_bmips(pcie)) tmp &=3D ~PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK; else tmp &=3D ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK; - writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + writel(tmp, base + HARD_DEBUG(pcie)); /* Wait for SerDes to be stable */ usleep_range(100, 200); =20 @@ -1072,7 +1075,7 @@ static void brcm_config_clkreq(struct brcm_pcie *pcie) } =20 /* Start out assuming safe mode (both mode bits cleared) */ - clkreq_cntl =3D readl(pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + clkreq_cntl =3D readl(pcie->base + HARD_DEBUG(pcie)); clkreq_cntl &=3D ~PCIE_CLKREQ_MASK; =20 if (strcmp(mode, "no-l1ss") =3D=3D 0) { @@ -1115,7 +1118,7 @@ static void brcm_config_clkreq(struct brcm_pcie *pcie) dev_err(pcie->dev, err_msg); mode =3D "safe"; } - writel(clkreq_cntl, pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + writel(clkreq_cntl, pcie->base + HARD_DEBUG(pcie)); =20 dev_info(pcie->dev, "clkreq-mode set to %s\n", mode); } @@ -1337,9 +1340,9 @@ static void brcm_pcie_turn_off(struct brcm_pcie *pcie) writel(tmp, base + PCIE_MISC_PCIE_CTRL); =20 /* Turn off SerDes */ - tmp =3D readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + tmp =3D readl(base + HARD_DEBUG(pcie)); u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MAS= K); - writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + writel(tmp, base + HARD_DEBUG(pcie)); =20 /* Shutdown PCIe bridge */ pcie->bridge_sw_init_set(pcie, 1); @@ -1425,9 +1428,9 @@ static int brcm_pcie_resume_noirq(struct device *dev) pcie->bridge_sw_init_set(pcie, 0); =20 /* SERDES_IDDQ =3D 0 */ - tmp =3D readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + tmp =3D readl(base + HARD_DEBUG(pcie)); u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MAS= K); - writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + writel(tmp, base + HARD_DEBUG(pcie)); =20 /* wait for serdes to be stable */ udelay(100); @@ -1499,12 +1502,16 @@ static const int pcie_offsets[] =3D { [RGR1_SW_INIT_1] =3D 0x9210, [EXT_CFG_INDEX] =3D 0x9000, [EXT_CFG_DATA] =3D 0x9004, + [PCIE_HARD_DEBUG] =3D 0x4204, + [PCIE_INTR2_CPU_BASE] =3D 0x4300, }; =20 static const int pcie_offsets_bmips_7425[] =3D { [RGR1_SW_INIT_1] =3D 0x8010, [EXT_CFG_INDEX] =3D 0x8300, [EXT_CFG_DATA] =3D 0x8304, + [PCIE_HARD_DEBUG] =3D 0x4204, + [PCIE_INTR2_CPU_BASE] =3D 0x4300, }; =20 static const struct pcie_cfg_data generic_cfg =3D { @@ -1539,6 +1546,8 @@ static const int pcie_offset_bcm7278[] =3D { [RGR1_SW_INIT_1] =3D 0xc010, [EXT_CFG_INDEX] =3D 0x9000, [EXT_CFG_DATA] =3D 0x9004, + [PCIE_HARD_DEBUG] =3D 0x4204, + [PCIE_INTR2_CPU_BASE] =3D 0x4300, }; =20 static const struct pcie_cfg_data bcm7278_cfg =3D { --=20 2.17.1 From nobody Sat Feb 7 16:26:36 2026 Received: from mail-qt1-f172.google.com (mail-qt1-f172.google.com [209.85.160.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE4EE16EBED for ; Wed, 31 Jul 2024 22:28:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722464927; cv=none; b=Aws0WljNoaLVQPRH/8Pn6jrx7hPvPZ/rmmTDqmY39YriJN+N1afjS8OvX9y6K9DFWuw2XtF5rc/OxugqZAdeACP6F4L9Ozi1V9hhjhEGYqPeZT9SBvq982hZOUvaOhiQ/mGu7N/ywXg6xsd+DH4hywIJ1iEDo18s+MWxIutUBgI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722464927; c=relaxed/simple; bh=Axler9r52aj1s9GK2m+ZS5HEzmaURax/pBU9GtjX+YU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=Ql074CbaxRBHlzrAy9WNuTFjTtD7RN7ov7IdHM4hzhVeD5Ndtgof3Uk+BNaOe7w0LqT58kyMvRZDtloTC9JaSxk2kFEArCAANOEWRqBc6vWvoJ7Gkl6icWr7kSEdJVp9jmUtCnWlTnvK4DJfY+lOfuYIGDkDE9Z+PjUfST21kVs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=ZIjnoSEW; arc=none smtp.client-ip=209.85.160.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="ZIjnoSEW" Received: by mail-qt1-f172.google.com with SMTP id d75a77b69052e-44fe106616eso34150491cf.1 for ; Wed, 31 Jul 2024 15:28:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1722464925; x=1723069725; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=tJc8HBYFIKOYZ9CyZ9IbVGyaBM2QRYS+Mj0ZBsZxAaw=; b=ZIjnoSEWyf8tibkylAARjhWmCx8QJN0arOi04w4k8lPCPag3vBA9raSgQbIynXI8u+ vqN6zYudvWciuWdwGOiyOd+IE2REt1anYcJ43VYlGxCDeOnKkAo/XicBXbkqqdvizaTR I0u3SbRybEN38mDfYbo96LaaR9LuHiD7bk4mQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722464925; x=1723069725; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=tJc8HBYFIKOYZ9CyZ9IbVGyaBM2QRYS+Mj0ZBsZxAaw=; b=Tx+9wZPzHz4QZML5zeWJjF3J6Uovk4Oa2VjQLCAFw0CcGfTFp0Nikq/sKV8EG1IP0L R6gNP1UBtwgGSr2XfLM0DeIWKFBKSsqHlDOEFbqB1E90YTj0dfdFyUzukpKtwL9zvNwl bf4np0skltvHRTIcj8VPLvI4l/IOK95xmB65E3KIHsUbhcS2t6EHNWFoqpvq9lxD4lty xL9J6sfHGH3hglPJnC7uvxqbOyrSysRQ6biUn2jEND5nAbg5KnerQraAPYKgyHpXapo8 eLtekyxfuywfN1V2uJW0U+F8PbhgsoORkOZ9tzZU2EqNsi0s+ilGGU7Pz9xTiIzOSPaP f2uQ== X-Forwarded-Encrypted: i=1; AJvYcCW90vB5INDcotOcvUBQ+iOU/A2CG39IQyCoFVE8wB1DRhlWO3HCmW2ajwwb8dxF/2GrX8tgbeq1yHp6s7bBAqI2trujgT5kCCneCnMh X-Gm-Message-State: AOJu0YzWzTaDLrwgClD6QleCiXZiFtZDIU+D8vWevR5iwQx1WtFkLXLN 6qzHjYvYbspXIJm/fhde0tGcBrwyyFKPwHIshW+t5X7W1GSJKarPc5fHowZ6oQ== X-Google-Smtp-Source: AGHT+IGWS8XJqJxSeAH/l9U2iSnwykrx+/R/UPoZ2dJMSXMMtQONEAADXPeWL2Ey1+sfyHjCoQX+JQ== X-Received: by 2002:a05:622a:1922:b0:44d:6627:4b16 with SMTP id d75a77b69052e-4514f9bdc74mr7720561cf.1.1722464924732; Wed, 31 Jul 2024 15:28:44 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-44fe8416c80sm62359181cf.96.2024.07.31.15.28.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jul 2024 15:28:44 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 07/12] PCI: brcmstb: Remove two unused constants from driver Date: Wed, 31 Jul 2024 18:28:21 -0400 Message-Id: <20240731222831.14895-8-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240731222831.14895-1-james.quinlan@broadcom.com> References: <20240731222831.14895-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Remove two constants in the driver which are no longer used: RGR1_SW_INIT_1_INIT_MASK and RGR1_SW_INIT_1_INIT_SHIFT. Signed-off-by: Jim Quinlan Reviewed-by: Stanimir Varbanov Reviewed-by: Florian Fainelli Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/pcie-brcmstb.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 9fa1500b8eee..1ae66c639186 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -210,11 +210,6 @@ enum { PCIE_INTR2_CPU_BASE, }; =20 -enum { - RGR1_SW_INIT_1_INIT_MASK, - RGR1_SW_INIT_1_INIT_SHIFT, -}; - enum pcie_type { GENERIC, BCM7425, --=20 2.17.1 From nobody Sat Feb 7 16:26:36 2026 Received: from mail-qt1-f169.google.com (mail-qt1-f169.google.com [209.85.160.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B6B316F0C6 for ; Wed, 31 Jul 2024 22:28:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722464928; cv=none; b=YbMqX8H9vKrKDvqLokv5lXdlZVEh3dmSaPzjUhvUtJRyu/Xd/EjRMbXe7uVXFw4qLgjNLjjqGilbhjrVSYCuIzAvw5uWcdnQNzdVmfYhBBaksXWGI+ZOhISsR0DKKkDo5o6VoeXgREuldaMb4DWaeB2/ej1k2u1bJr0FdAdTN0Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722464928; c=relaxed/simple; bh=y4hjFNKfNrZAXib/tvA7NVNsQrFiOMDnP+KgXAPJWNE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=uvZmz8jXpOqZmM7/e+OeB9L6yofXImMEeFJUlewGWywyCiPeaA0aBz1cQtShRVKjAWjZjehxRrRLPcoBn2aobB0P6P318MRMNyKmOaI+uUrxewruwI7VlrXMQ17bKnB77ZJfYU5e6Z2VJEXbgX/CJGuroj/ItDjD5os7T7kuKVI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=fYK4yan/; arc=none smtp.client-ip=209.85.160.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="fYK4yan/" Received: by mail-qt1-f169.google.com with SMTP id d75a77b69052e-44fea44f725so13269151cf.1 for ; Wed, 31 Jul 2024 15:28:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1722464926; x=1723069726; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=Bv0ulUw6sT8Iayb14UqZxCz07Sx/8FXvzTyd8OjlUtI=; b=fYK4yan/eHVFlukjIxgLOOy6nlVRU2tBavQ6Hbdgj8gY6M4ZF9tbOXWDzsU50irc6N m940ekCSz0EjaxX2xU4ZuiQCXAsR+l15TxqofhTYew+lsqYdyz3QY/FPo/+VGOI0jMxW EVIWXHqBVjNY9YWH11Y3//guLyK4qcF71w2uE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722464926; x=1723069726; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Bv0ulUw6sT8Iayb14UqZxCz07Sx/8FXvzTyd8OjlUtI=; b=UQyWcnyY7risBkMAPE86eRTlCis8tqphUw4KE4lmy+A8IcE6wZY/nARd+7QquKXEkr WxrmkFPQ/dZFlMjr6zumzcZ4bAFIePlTKrD5t393VFxTgbrMRl9yT5O8Ff/MYRo+YZOn N41FiCmYLHoTDYk8/Xc+anG+C38//Pd2Npie2HGjz+uTYjXvXB27qGWjh2dhAUkMG0rs FnMVQLhji9fYwysr2AD0AxPV3U1uVHnin1FnUCFDx7XHp6ubtWVe7bTb0hBTO5K8OMas 5WZlhfiLII4HzYsVqn633lgwfSffNrvgMdYNqVyZu3J2VybRf11FMHdDU/H2HSpXRXKn DBGQ== X-Forwarded-Encrypted: i=1; AJvYcCX3kxSUimYvpf+/oTbc/GbpUxFsOsBvuRzMA7MKwW0sb0hqLx5bHyxT4LSLg3+SOL0lAV0sLMKXG2DKuZo=@vger.kernel.org X-Gm-Message-State: AOJu0YzHGdq6UO+kUDd2z8djFtuvqjhomiMKMOAlMk++lF4EndRqGjzF aRvp+oci3CstIDD7WyTLOjqvDURq2E0gR56y+nUoXSOOGi4MF2KZxcH9MlgHwA== X-Google-Smtp-Source: AGHT+IEc1bug40GUkbPlSsJIRank943JPZR+j1XlzEMEL1N3IsMC7w+8rJGmsbIu3BEy1N2Ib6H+1A== X-Received: by 2002:a05:622a:587:b0:446:5b56:989 with SMTP id d75a77b69052e-4517ee9eb96mr12185401cf.6.1722464926160; Wed, 31 Jul 2024 15:28:46 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-44fe8416c80sm62359181cf.96.2024.07.31.15.28.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jul 2024 15:28:45 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 08/12] PCI: brcmstb: Don't conflate the reset rescal with phy ctrl Date: Wed, 31 Jul 2024 18:28:22 -0400 Message-Id: <20240731222831.14895-9-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240731222831.14895-1-james.quinlan@broadcom.com> References: <20240731222831.14895-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add a "has_phy" field indicating that the internal phy has SW control that requires configuration. Some previous chips only required the firing of the "rescal" reset controller. This change requires us to give the 7216 SoC its own cfg_data structure. Signed-off-by: Jim Quinlan Reviewed-by: Stanimir Varbanov Reviewed-by: Florian Fainelli Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/pcie-brcmstb.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 1ae66c639186..4659208ae8da 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -222,6 +222,7 @@ enum pcie_type { struct pcie_cfg_data { const int *offsets; const enum pcie_type type; + const bool has_phy; void (*perst_set)(struct brcm_pcie *pcie, u32 val); void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); }; @@ -272,6 +273,7 @@ struct brcm_pcie { void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); struct subdev_regulators *sr; bool ep_wakeup_capable; + bool has_phy; }; =20 static inline bool is_bmips(const struct brcm_pcie *pcie) @@ -1311,12 +1313,12 @@ static int brcm_phy_cntl(struct brcm_pcie *pcie, co= nst int start) =20 static inline int brcm_phy_start(struct brcm_pcie *pcie) { - return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0; + return pcie->has_phy ? brcm_phy_cntl(pcie, 1) : 0; } =20 static inline int brcm_phy_stop(struct brcm_pcie *pcie) { - return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0; + return pcie->has_phy ? brcm_phy_cntl(pcie, 0) : 0; } =20 static void brcm_pcie_turn_off(struct brcm_pcie *pcie) @@ -1559,12 +1561,20 @@ static const struct pcie_cfg_data bcm2711_cfg =3D { .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, }; =20 +static const struct pcie_cfg_data bcm7216_cfg =3D { + .offsets =3D pcie_offset_bcm7278, + .type =3D BCM7278, + .perst_set =3D brcm_pcie_perst_set_7278, + .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_7278, + .has_phy =3D true, +}; + static const struct of_device_id brcm_pcie_match[] =3D { { .compatible =3D "brcm,bcm2711-pcie", .data =3D &bcm2711_cfg }, { .compatible =3D "brcm,bcm4908-pcie", .data =3D &bcm4908_cfg }, { .compatible =3D "brcm,bcm7211-pcie", .data =3D &generic_cfg }, { .compatible =3D "brcm,bcm7278-pcie", .data =3D &bcm7278_cfg }, - { .compatible =3D "brcm,bcm7216-pcie", .data =3D &bcm7278_cfg }, + { .compatible =3D "brcm,bcm7216-pcie", .data =3D &bcm7216_cfg }, { .compatible =3D "brcm,bcm7445-pcie", .data =3D &generic_cfg }, { .compatible =3D "brcm,bcm7435-pcie", .data =3D &bcm7435_cfg }, { .compatible =3D "brcm,bcm7425-pcie", .data =3D &bcm7425_cfg }, @@ -1612,6 +1622,7 @@ static int brcm_pcie_probe(struct platform_device *pd= ev) pcie->type =3D data->type; pcie->perst_set =3D data->perst_set; pcie->bridge_sw_init_set =3D data->bridge_sw_init_set; + pcie->has_phy =3D data->has_phy; =20 pcie->base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pcie->base)) --=20 2.17.1 From nobody Sat Feb 7 16:26:36 2026 Received: from mail-qt1-f169.google.com (mail-qt1-f169.google.com [209.85.160.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E00C16F907 for ; Wed, 31 Jul 2024 22:28:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722464931; cv=none; b=lXTb2VzSORDTlIgB5cbjaMuhn/tfZpur8KIjjMR0TAF7IskENsGBSfrD8NlxCzf8ilxsIpx4CDZNWENJ2XBuPKbQsaHfZiKNC9XC00u7MieecBZsdN9y+kcxaOE+J3GE7l3IaCqPJg5B8VvQFbJvkYAhVd9XRUtQFdGsvre5dVQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722464931; c=relaxed/simple; bh=50hNICu5I0cQ1dc8e6sKALzLgxa4Aa4k1WXKXjZo4o8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=FRpm685WtnQvlhS5Rr104oLWY1ath5a3IvkjglIEn4fJviKow0BpDW5MIetxHcVzMn1Uc1X4tTtYpRxetkimQNrxVIKoUwMuVHRXxXrjGO6Q3UF8S8rhkfu+gd4ZEHCxjwNFicT/GiVlJ0Kf8umPwPcdm8wkiDSu+nbq0NSEtEk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=TbfFuTwI; arc=none smtp.client-ip=209.85.160.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="TbfFuTwI" Received: by mail-qt1-f169.google.com with SMTP id d75a77b69052e-44ff6dd158cso38691271cf.3 for ; Wed, 31 Jul 2024 15:28:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1722464928; x=1723069728; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=5pfZmRNKdTMWf2ZqvAr4Qq8R0KQvMMl+ZjRL68UJXeA=; b=TbfFuTwIcFZ8aXqpry3bIst/7IwaYoLavYxeh4K69qOdKMUfweGDUmkYh83p2sk5wM SB1BWY1ym5vN5pyt0o/ZMDXyDwUv0lJtBiRPqn62oSYzhUD3wCPzueuhO/OTMClZ4uEQ 4U1XDKboymrJM41KTUvUVNsQ9JjJ0KLTA0b9I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722464928; x=1723069728; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=5pfZmRNKdTMWf2ZqvAr4Qq8R0KQvMMl+ZjRL68UJXeA=; b=oADC9cFznaUBd1eLMWqAYR/NxHHOwmJzQXZG9nVQIWIkDZAHNPP+uS24Ho5OUVsESv TFWZrY2idmjXWhZ4h6D2q32rsCbrtvhO+fG9YB0naSapoxZtbFPGHSevjtbHnpccWYj5 mUDopoXsXjc4HQz4Toqze2AHNVDgB8oMXECXkw5YZBoScROTrx7J6qeF52z48Fw4RrQo z6ZNKmS/S0eCYtwj19C3gIJPCLSWq2HGJQj/YfWDjUCYLVxdjJkKghSSg/MUCEXvAw8P QpuIQN7coHx2MvIcnH5upAhQzjBBHz8r+lABGAahw83bLtgIZSNk6E/ULZRcxDDeOMRd ZIow== X-Forwarded-Encrypted: i=1; AJvYcCUd9+thqfNr3Ux4qCnCQgqUDc0qPvczecgxCWMgGg3QfhCmTMPI2BNAgH6mhDxkUkf7ZvwugzxGjUSD3qg=@vger.kernel.org X-Gm-Message-State: AOJu0YxzvdMCcnyFit2QQLaiu4bOEB79EIulQUp/pByVwVCr+KlDBeaj 1UahSRCgB/SjRh5wFPjYCMQrFzgWWrhSYdxBiWRFgDi/uZ9pKhSlAuCYK8JgyQ== X-Google-Smtp-Source: AGHT+IHBBkmfHuYFGI148IzJz1GuxHa/aa+gI22Rh/rpjLFTRKmigH5kniWSfAx/Gc1Jo5Fg2Wy6fQ== X-Received: by 2002:ac8:7dc6:0:b0:44f:fb58:8c3e with SMTP id d75a77b69052e-4514f9b69b1mr8006651cf.46.1722464927837; Wed, 31 Jul 2024 15:28:47 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-44fe8416c80sm62359181cf.96.2024.07.31.15.28.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jul 2024 15:28:47 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 09/12] PCI: brcmstb: Refactor for chips with many regular inbound windows Date: Wed, 31 Jul 2024 18:28:23 -0400 Message-Id: <20240731222831.14895-10-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240731222831.14895-1-james.quinlan@broadcom.com> References: <20240731222831.14895-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Provide support for new chips with multiple inbound windows while keeping the legacy support for the older chips. In existing chips there are three inbound windows with fixed purposes: the first was for mapping SoC internal registers, the second was for memory, and the third was for memory but with the endian swapped. Typically, only one window was used. Complicating the inbound window usage was the fact that the PCIe HW would do a baroque internal mapping of system memory, and concatenate the regions of multiple memory controllers. Newer chips such as the 7712 and Cable Modem SOCs take a step forward and drop the internal mapping while providing for multiple inbound windows. This works in concert with the dma-ranges property, where each provided range becomes an inbound window. Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli Reviewed-by: Stanimir Varbanov --- drivers/pci/controller/pcie-brcmstb.c | 228 ++++++++++++++++++++------ 1 file changed, 177 insertions(+), 51 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 4659208ae8da..0ecca3d9576f 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -75,15 +75,19 @@ #define PCIE_MEM_WIN0_HI(win) \ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8) =20 +/* + * NOTE: You may see the term "BAR" in a number of register names used by + * this driver. The term is an artifact of when the HW core was an + * endpoint device (EP). Now it is a root complex (RC) and anywhere a + * register has the term "BAR" it is related to an inbound window. + */ + +#define PCIE_BRCM_MAX_INBOUND_WINS 16 #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c #define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f =20 -#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034 -#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f -#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 +#define PCIE_MISC_RC_BAR4_CONFIG_LO 0x40d4 =20 -#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c -#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f =20 #define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044 #define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048 @@ -130,6 +134,10 @@ (PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK | \ PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK) =20 +#define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP 0x40ac +#define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_MASK BIT(0) +#define PCIE_MISC_UBUS_BAR4_CONFIG_REMAP 0x410c + #define PCIE_MSI_INTR2_BASE 0x4500 =20 /* Offsets from INTR2_CPU and MSI_INTR2 BASE offsets */ @@ -217,12 +225,20 @@ enum pcie_type { BCM4908, BCM7278, BCM2711, + BCM7712, +}; + +struct inbound_win { + u64 size; + u64 pci_offset; + u64 cpu_addr; }; =20 struct pcie_cfg_data { const int *offsets; const enum pcie_type type; const bool has_phy; + unsigned int num_inbound_wins; void (*perst_set)(struct brcm_pcie *pcie, u32 val); void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); }; @@ -274,6 +290,7 @@ struct brcm_pcie { struct subdev_regulators *sr; bool ep_wakeup_capable; bool has_phy; + int num_inbound_wins; }; =20 static inline bool is_bmips(const struct brcm_pcie *pcie) @@ -789,23 +806,61 @@ static void brcm_pcie_perst_set_generic(struct brcm_p= cie *pcie, u32 val) writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); } =20 -static int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie, - u64 *rc_bar2_size, - u64 *rc_bar2_offset) +static inline void set_bar(struct inbound_win *b, int *count, u64 size, + u64 cpu_addr, u64 pci_offset) +{ + b->size =3D size; + b->cpu_addr =3D cpu_addr; + b->pci_offset =3D pci_offset; + (*count)++; +} + +static int brcm_pcie_get_inbound_wins(struct brcm_pcie *pcie, + struct inbound_win inbound_wins[]) { struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(pcie); + u64 pci_offset, cpu_addr, size =3D 0, tot_size =3D 0; struct resource_entry *entry; struct device *dev =3D pcie->dev; u64 lowest_pcie_addr =3D ~(u64)0; - int ret, i =3D 0; - u64 size =3D 0; + int ret, i =3D 0, n =3D 0; + + /* + * The HW registers (and PCIe) use order-1 numbering for BARs. As + * such, we have inbound_wins[0] unused and BAR1 starts at inbound_wins[1= ]. + */ + struct inbound_win *b_begin =3D &inbound_wins[1]; + struct inbound_win *b =3D b_begin; + + /* + * STB chips beside 7712 disable the first inbound window default. + * Rather being mapped to system memory it is mapped to the + * internal registers of the SoC. This feature is deprecated, has + * security considerations, and is not implemented in our modern + * SoCs. + */ + if (pcie->type !=3D BCM7712) + set_bar(b++, &n, 0, 0, 0); =20 resource_list_for_each_entry(entry, &bridge->dma_ranges) { u64 pcie_beg =3D entry->res->start - entry->offset; + u64 cpu_beg =3D entry->res->start; =20 - size +=3D entry->res->end - entry->res->start + 1; + size =3D resource_size(entry->res); + tot_size +=3D size; if (pcie_beg < lowest_pcie_addr) lowest_pcie_addr =3D pcie_beg; + /* + * 7712 and newer chips may have many BARs, with each + * offering a non-overlapping viewport to system memory. + * That being said, each BARs size must still be a power of + * two. + */ + if (pcie->type =3D=3D BCM7712) + set_bar(b++, &n, size, cpu_beg, pcie_beg); + + if (n > pcie->num_inbound_wins) + break; } =20 if (lowest_pcie_addr =3D=3D ~(u64)0) { @@ -813,13 +868,20 @@ static int brcm_pcie_get_rc_bar2_size_and_offset(stru= ct brcm_pcie *pcie, return -EINVAL; } =20 + /* + * 7712 and newer chips do not have an internal memory mapping system + * that enables multiple memory controllers. As such, it can return + * now w/o doing special configuration. + */ + if (pcie->type =3D=3D BCM7712) + return n; + ret =3D of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", p= cie->memc_size, 1, PCIE_BRCM_MAX_MEMC); - if (ret <=3D 0) { /* Make an educated guess */ pcie->num_memc =3D 1; - pcie->memc_size[0] =3D 1ULL << fls64(size - 1); + pcie->memc_size[0] =3D 1ULL << fls64(tot_size - 1); } else { pcie->num_memc =3D ret; } @@ -828,10 +890,15 @@ static int brcm_pcie_get_rc_bar2_size_and_offset(stru= ct brcm_pcie *pcie, for (i =3D 0, size =3D 0; i < pcie->num_memc; i++) size +=3D pcie->memc_size[i]; =20 - /* System memory starts at this address in PCIe-space */ - *rc_bar2_offset =3D lowest_pcie_addr; - /* The sum of all memc views must also be a power of 2 */ - *rc_bar2_size =3D 1ULL << fls64(size - 1); + /* Our HW mandates that the window size must be a power of 2 */ + size =3D 1ULL << fls64(size - 1); + + /* + * For STB chips, the BAR2 cpu_addr is hardwired to the start + * of system memory, so we set it to 0. + */ + cpu_addr =3D 0; + pci_offset =3D lowest_pcie_addr; =20 /* * We validate the inbound memory view even though we should trust @@ -866,25 +933,90 @@ static int brcm_pcie_get_rc_bar2_size_and_offset(stru= ct brcm_pcie *pcie, * outbound memory @ 3GB). So instead it will start at the 1x * multiple of its size */ - if (!*rc_bar2_size || (*rc_bar2_offset & (*rc_bar2_size - 1)) || - (*rc_bar2_offset < SZ_4G && *rc_bar2_offset > SZ_2G)) { - dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n", - *rc_bar2_size, *rc_bar2_offset); + if (!size || (pci_offset & (size - 1)) || + (pci_offset < SZ_4G && pci_offset > SZ_2G)) { + dev_err(dev, "Invalid inbound_win2_offset/size: size 0x%llx, off 0x%llx\= n", + size, pci_offset); return -EINVAL; } =20 - return 0; + /* Enable inbound window 2, the main inbound window for STB chips */ + set_bar(b++, &n, size, cpu_addr, pci_offset); + + /* + * Disable inbound window 3. On some chips presents the same + * window as #2 but the data appears in a settable endianness. + */ + set_bar(b++, &n, 0, 0, 0); + + return n; +} + +static u32 brcm_bar_reg_offset(int bar) +{ + if (bar <=3D 3) + return PCIE_MISC_RC_BAR1_CONFIG_LO + 8 * (bar - 1); + else + return PCIE_MISC_RC_BAR4_CONFIG_LO + 8 * (bar - 4); +} + +static u32 brcm_ubus_reg_offset(int bar) +{ + if (bar <=3D 3) + return PCIE_MISC_UBUS_BAR1_CONFIG_REMAP + 8 * (bar - 1); + else + return PCIE_MISC_UBUS_BAR4_CONFIG_REMAP + 8 * (bar - 4); +} + +static void set_inbound_win_registers(struct brcm_pcie *pcie, + const struct inbound_win *inbound_wins, + int num_inbound_wins) +{ + void __iomem *base =3D pcie->base; + int i; + + for (i =3D 1; i <=3D num_inbound_wins; i++) { + u64 pci_offset =3D inbound_wins[i].pci_offset; + u64 cpu_addr =3D inbound_wins[i].cpu_addr; + u64 size =3D inbound_wins[i].size; + u32 reg_offset =3D brcm_bar_reg_offset(i); + u32 tmp =3D lower_32_bits(pci_offset); + + u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(size), + PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK); + + /* Write low */ + writel(tmp, base + reg_offset); + /* Write high */ + writel(upper_32_bits(pci_offset), base + reg_offset + 4); + + /* + * Most STB chips: + * Do nothing. + * 7712: + * All of their BARs need to be set. + */ + if (pcie->type =3D=3D BCM7712) { + /* BUS remap register settings */ + reg_offset =3D brcm_ubus_reg_offset(i); + tmp =3D lower_32_bits(cpu_addr) & ~0xfff; + tmp |=3D PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_MASK; + writel(tmp, base + reg_offset); + tmp =3D upper_32_bits(cpu_addr); + writel(tmp, base + reg_offset + 4); + } + } } =20 static int brcm_pcie_setup(struct brcm_pcie *pcie) { - u64 rc_bar2_offset, rc_bar2_size; + struct inbound_win inbound_wins[PCIE_BRCM_MAX_INBOUND_WINS]; void __iomem *base =3D pcie->base; struct pci_host_bridge *bridge; struct resource_entry *entry; u32 tmp, burst, aspm_support; - int num_out_wins =3D 0; - int ret, memc; + int num_out_wins =3D 0, num_rc_bars =3D 0; + int memc; =20 /* Reset the bridge */ pcie->bridge_sw_init_set(pcie, 1); @@ -933,17 +1065,16 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK); writel(tmp, base + PCIE_MISC_MISC_CTRL); =20 - ret =3D brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size, - &rc_bar2_offset); - if (ret) - return ret; + num_rc_bars =3D brcm_pcie_get_inbound_wins(pcie, inbound_wins); + if (num_rc_bars < 0) + return num_rc_bars; + + set_inbound_win_registers(pcie, inbound_wins, num_rc_bars); =20 - tmp =3D lower_32_bits(rc_bar2_offset); - u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size), - PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK); - writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO); - writel(upper_32_bits(rc_bar2_offset), - base + PCIE_MISC_RC_BAR2_CONFIG_HI); + if (!brcm_pcie_rc_mode(pcie)) { + dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n"); + return -EINVAL; + } =20 tmp =3D readl(base + PCIE_MISC_MISC_CTRL); for (memc =3D 0; memc < pcie->num_memc; memc++) { @@ -965,25 +1096,12 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) * 4GB or when the inbound area is smaller than 4GB (taking into * account the rounding-up we're forced to perform). */ - if (rc_bar2_offset >=3D SZ_4G || (rc_bar2_size + rc_bar2_offset) < SZ_4G) + if (inbound_wins[2].pci_offset >=3D SZ_4G || + (inbound_wins[2].size + inbound_wins[2].pci_offset) < SZ_4G) pcie->msi_target_addr =3D BRCM_MSI_TARGET_ADDR_LT_4GB; else pcie->msi_target_addr =3D BRCM_MSI_TARGET_ADDR_GT_4GB; =20 - if (!brcm_pcie_rc_mode(pcie)) { - dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n"); - return -EINVAL; - } - - /* disable the PCIe->GISB memory window (RC_BAR1) */ - tmp =3D readl(base + PCIE_MISC_RC_BAR1_CONFIG_LO); - tmp &=3D ~PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK; - writel(tmp, base + PCIE_MISC_RC_BAR1_CONFIG_LO); - - /* disable the PCIe->SCB memory window (RC_BAR3) */ - tmp =3D readl(base + PCIE_MISC_RC_BAR3_CONFIG_LO); - tmp &=3D ~PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK; - writel(tmp, base + PCIE_MISC_RC_BAR3_CONFIG_LO); =20 /* Don't advertise L0s capability if 'aspm-no-l0s' */ aspm_support =3D PCIE_LINK_STATE_L1; @@ -1034,7 +1152,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) num_out_wins++; } =20 - /* PCIe->SCB endian mode for BAR */ + /* PCIe->SCB endian mode for inbound window */ tmp =3D readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN, PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK); @@ -1516,6 +1634,7 @@ static const struct pcie_cfg_data generic_cfg =3D { .type =3D GENERIC, .perst_set =3D brcm_pcie_perst_set_generic, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, + .num_inbound_wins =3D 3, }; =20 static const struct pcie_cfg_data bcm7425_cfg =3D { @@ -1523,6 +1642,7 @@ static const struct pcie_cfg_data bcm7425_cfg =3D { .type =3D BCM7425, .perst_set =3D brcm_pcie_perst_set_generic, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, + .num_inbound_wins =3D 3, }; =20 static const struct pcie_cfg_data bcm7435_cfg =3D { @@ -1530,6 +1650,7 @@ static const struct pcie_cfg_data bcm7435_cfg =3D { .type =3D BCM7435, .perst_set =3D brcm_pcie_perst_set_generic, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, + .num_inbound_wins =3D 3, }; =20 static const struct pcie_cfg_data bcm4908_cfg =3D { @@ -1537,6 +1658,7 @@ static const struct pcie_cfg_data bcm4908_cfg =3D { .type =3D BCM4908, .perst_set =3D brcm_pcie_perst_set_4908, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, + .num_inbound_wins =3D 3, }; =20 static const int pcie_offset_bcm7278[] =3D { @@ -1552,6 +1674,7 @@ static const struct pcie_cfg_data bcm7278_cfg =3D { .type =3D BCM7278, .perst_set =3D brcm_pcie_perst_set_7278, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_7278, + .num_inbound_wins =3D 3, }; =20 static const struct pcie_cfg_data bcm2711_cfg =3D { @@ -1559,6 +1682,7 @@ static const struct pcie_cfg_data bcm2711_cfg =3D { .type =3D BCM2711, .perst_set =3D brcm_pcie_perst_set_generic, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, + .num_inbound_wins =3D 3, }; =20 static const struct pcie_cfg_data bcm7216_cfg =3D { @@ -1567,6 +1691,7 @@ static const struct pcie_cfg_data bcm7216_cfg =3D { .perst_set =3D brcm_pcie_perst_set_7278, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_7278, .has_phy =3D true, + .num_inbound_wins =3D 3, }; =20 static const struct of_device_id brcm_pcie_match[] =3D { @@ -1623,6 +1748,7 @@ static int brcm_pcie_probe(struct platform_device *pd= ev) pcie->perst_set =3D data->perst_set; pcie->bridge_sw_init_set =3D data->bridge_sw_init_set; pcie->has_phy =3D data->has_phy; + pcie->num_inbound_wins =3D data->num_inbound_wins; =20 pcie->base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pcie->base)) --=20 2.17.1 From nobody Sat Feb 7 16:26:36 2026 Received: from mail-qt1-f169.google.com (mail-qt1-f169.google.com [209.85.160.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B87AC16D9CB for ; Wed, 31 Jul 2024 22:28:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722464932; cv=none; b=bBZlp4VujZJ3syMtjqUDN+HmDAItZrZeBIeUg8TCFGnNFQWbPIuheS8wcFJIFn9Gk5SzJQ68QOA5X8kjchNYAMu0eufAphXUbG/rWmfIz5ayWx1MdtH6n3vuxeEtSY57F3fBPW9AFl26sCDWZY3aGE1MzQCMZNztW1lv7tQAUM8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722464932; c=relaxed/simple; bh=m8Yb5XC7EBKDcQqhey6p9ZpidQ1IqDx4NiWP2Ahl+bY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=VwBYbh5mQ4l54tuoKI3CnQGwFzF1lPZu3hZ5KFpkVTWJiAwn/0yqgKB23B1Mm0xsQdBApMMLQKHqsf7q4B+RVQYdpksV/5uB4DPoYDcbm9WtoOjzSJb6qwQYcOJBX9nUZHhgbxCkG1a3IlXugfFN2FVEWuOrkAll3gLsNqPfops= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=IBpxp6Ix; arc=none smtp.client-ip=209.85.160.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="IBpxp6Ix" Received: by mail-qt1-f169.google.com with SMTP id d75a77b69052e-44ff6f3c427so29087281cf.1 for ; Wed, 31 Jul 2024 15:28:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1722464929; x=1723069729; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=5hMN9hd5R2EuxrKDlmPrY0rWJepmZzVZcJJrxjFbWRw=; b=IBpxp6IxzOPulOg8KOf23BKPUNZW8C5mbRmh1zFpxjq+4kMapy74N9x1L6VsAoVzMq xw6iXbD2S1JQp8OGnEc4mcR1XVw2DqClGCfjchyU67oAbdIxkh/W5z6m3CrtkJ2aisT0 33g/v9Ui06SnE9U/xjuH3ijJuIB+t9uyh+geY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722464929; x=1723069729; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=5hMN9hd5R2EuxrKDlmPrY0rWJepmZzVZcJJrxjFbWRw=; b=ki+IGLFGWPoasN/30c1tM/7WvuUJQoczZD9l77I1sEOvXVVzlllI7eabPaHbBIlzcY RA6oPTkEQn2Vjped6QNE4H+/V+U2UutmPWxGoa7Jaj8bfVTSLe2YOWzhLXxdUne6UuPe yLWtzKiWLLB41AB1guO4BAEPPMAV07aA/W1unRm9xbUhWqSpU2CSiq/pCrDsgGahsXwy tfaGP9pUY8Fop8P4w2+NB4j7Pb7qiJC/OmsqOvnrhWVXTLRlfyG9YBDzeq79vCThpI5Y hnMgyAB9Yupp47oMtftTwYnY0CqutnV8+iKIdzXLzA+tc90pVX7MHmHQu1yqrA9ra8fS /p0w== X-Forwarded-Encrypted: i=1; AJvYcCXbT85JALZRpNPQdr7MUA/9bAbAaehgDq0aHGTcZ6fFCf1+voXo2D4yOW/yWZZ1cDjbDLZw92AUSgu64V4=@vger.kernel.org X-Gm-Message-State: AOJu0Ywqx6u3mUt7Xbbp0iT+SXWFxTcjDkVGUYT+L6KPXqT8oLzDNX30 uHBQsAW2BO3gj8rEXOyD3V6YiZHMAS0je9rRq3AIsarDFGQ6hkwxh1R6PtRn9A== X-Google-Smtp-Source: AGHT+IHb4s3V73+ztQ4zJoX+XZ9jOaCR5frA7+yF6G8XoMSBIJbRurH1mjZU8SRenbvMvCHRsNTPoQ== X-Received: by 2002:ac8:5914:0:b0:447:e046:8482 with SMTP id d75a77b69052e-4514f98bdb3mr7983191cf.23.1722464929441; Wed, 31 Jul 2024 15:28:49 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-44fe8416c80sm62359181cf.96.2024.07.31.15.28.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jul 2024 15:28:48 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Philipp Zabel , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 10/12] PCI: brcmstb: Check return value of all reset_control_xxx calls Date: Wed, 31 Jul 2024 18:28:24 -0400 Message-Id: <20240731222831.14895-11-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240731222831.14895-1-james.quinlan@broadcom.com> References: <20240731222831.14895-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Always check the return value for invocations of reset_control_xxx() and propagate the error to the next level. Although the current functions in reset-brcmstb.c cannot fail, this may someday change. Signed-off-by: Jim Quinlan Reviewed-by: Stanimir Varbanov Reviewed-by: Florian Fainelli Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/pcie-brcmstb.c | 102 ++++++++++++++++++-------- 1 file changed, 73 insertions(+), 29 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 0ecca3d9576f..c4ceb1823a79 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -239,8 +239,8 @@ struct pcie_cfg_data { const enum pcie_type type; const bool has_phy; unsigned int num_inbound_wins; - void (*perst_set)(struct brcm_pcie *pcie, u32 val); - void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); + int (*perst_set)(struct brcm_pcie *pcie, u32 val); + int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); }; =20 struct subdev_regulators { @@ -285,8 +285,8 @@ struct brcm_pcie { int num_memc; u64 memc_size[PCIE_BRCM_MAX_MEMC]; u32 hw_rev; - void (*perst_set)(struct brcm_pcie *pcie, u32 val); - void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); + int (*perst_set)(struct brcm_pcie *pcie, u32 val); + int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); struct subdev_regulators *sr; bool ep_wakeup_capable; bool has_phy; @@ -749,12 +749,18 @@ static void __iomem *brcm7425_pcie_map_bus(struct pci= _bus *bus, return base + DATA_ADDR(pcie); } =20 -static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u= 32 val) +static int brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u3= 2 val) { + int ret =3D 0; + if (val) - reset_control_assert(pcie->bridge_reset); + ret =3D reset_control_assert(pcie->bridge_reset); else - reset_control_deassert(pcie->bridge_reset); + ret =3D reset_control_deassert(pcie->bridge_reset); + + if (ret) + dev_err(pcie->dev, "failed to %s 'bridge' reset, err=3D%d\n", + val ? "assert" : "deassert", ret); =20 if (!pcie->bridge_reset) { u32 tmp, mask =3D RGR1_SW_INIT_1_INIT_GENERIC_MASK; @@ -764,9 +770,11 @@ static void brcm_pcie_bridge_sw_init_set_generic(struc= t brcm_pcie *pcie, u32 val tmp =3D (tmp & ~mask) | ((val << shift) & mask); writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); } + + return ret; } =20 -static void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 = val) +static int brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 v= al) { u32 tmp, mask =3D RGR1_SW_INIT_1_INIT_7278_MASK; u32 shift =3D RGR1_SW_INIT_1_INIT_7278_SHIFT; @@ -774,20 +782,29 @@ static void brcm_pcie_bridge_sw_init_set_7278(struct = brcm_pcie *pcie, u32 val) tmp =3D readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); tmp =3D (tmp & ~mask) | ((val << shift) & mask); writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); + + return 0; } =20 -static void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val) +static int brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val) { + int ret; + if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n")) - return; + return -EINVAL; =20 if (val) - reset_control_assert(pcie->perst_reset); + ret =3D reset_control_assert(pcie->perst_reset); else - reset_control_deassert(pcie->perst_reset); + ret =3D reset_control_deassert(pcie->perst_reset); + + if (ret) + dev_err(pcie->dev, "failed to %s 'perst' reset, err=3D%d\n", + val ? "assert" : "deassert", ret); + return ret; } =20 -static void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val) +static int brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val) { u32 tmp; =20 @@ -795,15 +812,19 @@ static void brcm_pcie_perst_set_7278(struct brcm_pcie= *pcie, u32 val) tmp =3D readl(pcie->base + PCIE_MISC_PCIE_CTRL); u32p_replace_bits(&tmp, !val, PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK); writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); + + return 0; } =20 -static void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) +static int brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) { u32 tmp; =20 tmp =3D readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK); writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); + + return 0; } =20 static inline void set_bar(struct inbound_win *b, int *count, u64 size, @@ -1016,19 +1037,28 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) struct resource_entry *entry; u32 tmp, burst, aspm_support; int num_out_wins =3D 0, num_rc_bars =3D 0; - int memc; + int memc, ret; =20 /* Reset the bridge */ - pcie->bridge_sw_init_set(pcie, 1); + ret =3D pcie->bridge_sw_init_set(pcie, 1); + if (ret) + return ret; =20 /* Ensure that PERST# is asserted; some bootloaders may deassert it. */ - if (pcie->type =3D=3D BCM2711) - pcie->perst_set(pcie, 1); + if (pcie->type =3D=3D BCM2711) { + ret =3D pcie->perst_set(pcie, 1); + if (ret) { + pcie->bridge_sw_init_set(pcie, 0); + return ret; + } + } =20 usleep_range(100, 200); =20 /* Take the bridge out of reset */ - pcie->bridge_sw_init_set(pcie, 0); + ret =3D pcie->bridge_sw_init_set(pcie, 0); + if (ret) + return ret; =20 tmp =3D readl(base + HARD_DEBUG(pcie)); if (is_bmips(pcie)) @@ -1247,7 +1277,9 @@ static int brcm_pcie_start_link(struct brcm_pcie *pci= e) int ret, i; =20 /* Unassert the fundamental reset */ - pcie->perst_set(pcie, 0); + ret =3D pcie->perst_set(pcie, 0); + if (ret) + return ret; =20 /* * Wait for 100ms after PERST# deassertion; see PCIe CEM specification @@ -1439,15 +1471,17 @@ static inline int brcm_phy_stop(struct brcm_pcie *p= cie) return pcie->has_phy ? brcm_phy_cntl(pcie, 0) : 0; } =20 -static void brcm_pcie_turn_off(struct brcm_pcie *pcie) +static int brcm_pcie_turn_off(struct brcm_pcie *pcie) { void __iomem *base =3D pcie->base; - int tmp; + int tmp, ret; =20 if (brcm_pcie_link_up(pcie)) brcm_pcie_enter_l23(pcie); /* Assert fundamental reset */ - pcie->perst_set(pcie, 1); + ret =3D pcie->perst_set(pcie, 1); + if (ret) + return ret; =20 /* Deassert request for L23 in case it was asserted */ tmp =3D readl(base + PCIE_MISC_PCIE_CTRL); @@ -1460,7 +1494,9 @@ static void brcm_pcie_turn_off(struct brcm_pcie *pcie) writel(tmp, base + HARD_DEBUG(pcie)); =20 /* Shutdown PCIe bridge */ - pcie->bridge_sw_init_set(pcie, 1); + ret =3D pcie->bridge_sw_init_set(pcie, 1); + + return ret; } =20 static int pci_dev_may_wakeup(struct pci_dev *dev, void *data) @@ -1478,9 +1514,12 @@ static int brcm_pcie_suspend_noirq(struct device *de= v) { struct brcm_pcie *pcie =3D dev_get_drvdata(dev); struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(pcie); - int ret; + int ret, rret; + + ret =3D brcm_pcie_turn_off(pcie); + if (ret) + return ret; =20 - brcm_pcie_turn_off(pcie); /* * If brcm_phy_stop() returns an error, just dev_err(). If we * return the error it will cause the suspend to fail and this is a @@ -1509,7 +1548,10 @@ static int brcm_pcie_suspend_noirq(struct device *de= v) pcie->sr->supplies); if (ret) { dev_err(dev, "Could not turn off regulators\n"); - reset_control_reset(pcie->rescal); + rret =3D reset_control_reset(pcie->rescal); + if (rret) + dev_err(dev, "failed to reset 'rascal' controller ret=3D%d\n", + rret); return ret; } } @@ -1524,7 +1566,7 @@ static int brcm_pcie_resume_noirq(struct device *dev) struct brcm_pcie *pcie =3D dev_get_drvdata(dev); void __iomem *base; u32 tmp; - int ret; + int ret, rret; =20 base =3D pcie->base; ret =3D clk_prepare_enable(pcie->clk); @@ -1586,7 +1628,9 @@ static int brcm_pcie_resume_noirq(struct device *dev) if (pcie->sr) regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies); err_reset: - reset_control_rearm(pcie->rescal); + rret =3D reset_control_rearm(pcie->rescal); + if (rret) + dev_err(pcie->dev, "failed to rearm 'rescal' reset, err=3D%d\n", rret); err_disable_clk: clk_disable_unprepare(pcie->clk); return ret; --=20 2.17.1 From nobody Sat Feb 7 16:26:36 2026 Received: from mail-qk1-f171.google.com (mail-qk1-f171.google.com [209.85.222.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8F68171E7C for ; Wed, 31 Jul 2024 22:28:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.222.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722464936; cv=none; b=aH+RTXId2mRCOHlPd+I/dIzkl8XRHpyrUIqf7m/fm532u5TGqwL6HSqYTYfYywnt8hrKyEq10eoEuIw6U01h7qiD++7kz1fomG0Xr9OGLNucuwxeRTvXlmjtlveTKmGeFQoegSyiG148Dqw5rNiv0hSyJMo6rIXwNMr8mNBr0kk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722464936; c=relaxed/simple; bh=KnEfs6HZv31jHNJ3+N/UsBfCm6ko0napd6s47uUx07M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=dH+oo7dHo/jNqiIJ/7w8dZqIJHLO9fAZ8nhtoygidDMLi5goKsbRjPGRUdQ+Uk8mku+woGUQKpjsE9uj76JwDXniYlkwi5tzK4DGXgvo8FPNJK3wCA0Ly2615cS6ClkcYLOdDszXRUmFW2mxkrBQNiBwYo2Kxfr089hBs9i/B+g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=S3veJwj8; arc=none smtp.client-ip=209.85.222.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="S3veJwj8" Received: by mail-qk1-f171.google.com with SMTP id af79cd13be357-7a20b8fa6dcso78131685a.3 for ; Wed, 31 Jul 2024 15:28:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1722464931; x=1723069731; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=YZm55XuvS5TsIWPd2I5O2BqV2wZK6adjRKLxKY6gWyA=; b=S3veJwj8DmWvGkvDU5YFTnGO2tNvBEpirW9qM/S8u9pdoYBRksK0sZ2gFWH7BApaQL IKRwNO1yrNCH6qLJ0Ia0YFEZA04/dFSLspvrcRjK/PgPYqRLL6FwVS1xNbA3H9PvjFFs jNGG46V0lWZsj1+1d0Law2AR3+NIpLRRVyCk4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722464931; x=1723069731; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=YZm55XuvS5TsIWPd2I5O2BqV2wZK6adjRKLxKY6gWyA=; b=N79Tk7Ww6iUCtpXhMJCHkxjsOAFbhyJOkPbxnqseY/En0xU0kiqbm4BIgIoAcBd/vK RXBZ9DRPiFuE+yHfAyfVYPLoOGjNJQFbjFPbSHDhx3cL0fJ7nf3MLxhFRahLGPoHOTOb spatzCcn2Hom0DgNbEK28C2iatgR3gLWUkJc2hcRHUEmQ08mi71DfcFa07SPmQp505XF RfhSb4mAKfkGXdJJai+8ciOHpmF/PmAWwp/nbmGLzgT58Tij9qxXQEGuW5bXLu5AT/Yh vnjgasHdXJdJ2QH+MQ5gsPK70sKhBxdhe6MPpXGUfekSrJ7WXqaXmMUxPFdpq57HZlam m1Ww== X-Forwarded-Encrypted: i=1; AJvYcCWksUz68c+ah+urQyXSC+tKb/nJGd31xiNbMnBz+HxZQu9REE4KKVWrembV63qe7HTZMZmForX3urYJmARdWF/WK9AL6GbhskNx2xK0 X-Gm-Message-State: AOJu0Yxf+kOd8iDcE+4J5/tck7uKTcQNKMJed6QcVAYuIzv+F3EC7JiJ Zij9lsegqZdjksgPnd2GXFYDqaSfYggImbBjKxiFg0It2Ap1tPfj0bHzSrwgwg== X-Google-Smtp-Source: AGHT+IEndjov11wcEzjulUpPn9DsM2Y3SCKwPkMcrsPJUtiLRsQRjQ/eaIW0tsU5qan9kt+FiHASmw== X-Received: by 2002:a05:620a:450b:b0:7a2:d63:4cc6 with SMTP id af79cd13be357-7a30c67f324mr66945185a.39.1722464931517; Wed, 31 Jul 2024 15:28:51 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-44fe8416c80sm62359181cf.96.2024.07.31.15.28.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jul 2024 15:28:50 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 11/12] PCI: brcmstb: Change field name from 'type' to 'soc_base' Date: Wed, 31 Jul 2024 18:28:25 -0400 Message-Id: <20240731222831.14895-12-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240731222831.14895-1-james.quinlan@broadcom.com> References: <20240731222831.14895-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The 'type' field used in the driver to discern SoC differences is confusing; change it to the more apt 'soc_base'. The 'base' is because some SoCs have the same characteristics as previous SoCs so it is convenient to classify them in the same group. Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 42 +++++++++++++-------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index c4ceb1823a79..4623b70f9ad8 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -218,7 +218,7 @@ enum { PCIE_INTR2_CPU_BASE, }; =20 -enum pcie_type { +enum pcie_soc_base { GENERIC, BCM7425, BCM7435, @@ -236,7 +236,7 @@ struct inbound_win { =20 struct pcie_cfg_data { const int *offsets; - const enum pcie_type type; + const enum pcie_soc_base soc_base; const bool has_phy; unsigned int num_inbound_wins; int (*perst_set)(struct brcm_pcie *pcie, u32 val); @@ -277,7 +277,7 @@ struct brcm_pcie { u64 msi_target_addr; struct brcm_msi *msi; const int *reg_offsets; - enum pcie_type type; + enum pcie_soc_base soc_base; struct reset_control *rescal; struct reset_control *perst_reset; struct reset_control *bridge_reset; @@ -295,7 +295,7 @@ struct brcm_pcie { =20 static inline bool is_bmips(const struct brcm_pcie *pcie) { - return pcie->type =3D=3D BCM7435 || pcie->type =3D=3D BCM7425; + return pcie->soc_base =3D=3D BCM7435 || pcie->soc_base =3D=3D BCM7425; } =20 /* @@ -860,7 +860,7 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pcie = *pcie, * security considerations, and is not implemented in our modern * SoCs. */ - if (pcie->type !=3D BCM7712) + if (pcie->soc_base !=3D BCM7712) set_bar(b++, &n, 0, 0, 0); =20 resource_list_for_each_entry(entry, &bridge->dma_ranges) { @@ -877,7 +877,7 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pcie = *pcie, * That being said, each BARs size must still be a power of * two. */ - if (pcie->type =3D=3D BCM7712) + if (pcie->soc_base =3D=3D BCM7712) set_bar(b++, &n, size, cpu_beg, pcie_beg); =20 if (n > pcie->num_inbound_wins) @@ -894,7 +894,7 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pcie = *pcie, * that enables multiple memory controllers. As such, it can return * now w/o doing special configuration. */ - if (pcie->type =3D=3D BCM7712) + if (pcie->soc_base =3D=3D BCM7712) return n; =20 ret =3D of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", p= cie->memc_size, 1, @@ -1017,7 +1017,7 @@ static void set_inbound_win_registers(struct brcm_pci= e *pcie, * 7712: * All of their BARs need to be set. */ - if (pcie->type =3D=3D BCM7712) { + if (pcie->soc_base =3D=3D BCM7712) { /* BUS remap register settings */ reg_offset =3D brcm_ubus_reg_offset(i); tmp =3D lower_32_bits(cpu_addr) & ~0xfff; @@ -1045,7 +1045,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) return ret; =20 /* Ensure that PERST# is asserted; some bootloaders may deassert it. */ - if (pcie->type =3D=3D BCM2711) { + if (pcie->soc_base =3D=3D BCM2711) { ret =3D pcie->perst_set(pcie, 1); if (ret) { pcie->bridge_sw_init_set(pcie, 0); @@ -1076,9 +1076,9 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) */ if (is_bmips(pcie)) burst =3D 0x1; /* 256 bytes */ - else if (pcie->type =3D=3D BCM2711) + else if (pcie->soc_base =3D=3D BCM2711) burst =3D 0x0; /* 128 bytes */ - else if (pcie->type =3D=3D BCM7278) + else if (pcie->soc_base =3D=3D BCM7278) burst =3D 0x3; /* 512 bytes */ else burst =3D 0x2; /* 512 bytes */ @@ -1675,7 +1675,7 @@ static const int pcie_offsets_bmips_7425[] =3D { =20 static const struct pcie_cfg_data generic_cfg =3D { .offsets =3D pcie_offsets, - .type =3D GENERIC, + .soc_base =3D GENERIC, .perst_set =3D brcm_pcie_perst_set_generic, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, .num_inbound_wins =3D 3, @@ -1683,7 +1683,7 @@ static const struct pcie_cfg_data generic_cfg =3D { =20 static const struct pcie_cfg_data bcm7425_cfg =3D { .offsets =3D pcie_offsets_bmips_7425, - .type =3D BCM7425, + .soc_base =3D BCM7425, .perst_set =3D brcm_pcie_perst_set_generic, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, .num_inbound_wins =3D 3, @@ -1691,7 +1691,7 @@ static const struct pcie_cfg_data bcm7425_cfg =3D { =20 static const struct pcie_cfg_data bcm7435_cfg =3D { .offsets =3D pcie_offsets, - .type =3D BCM7435, + .soc_base =3D BCM7435, .perst_set =3D brcm_pcie_perst_set_generic, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, .num_inbound_wins =3D 3, @@ -1699,7 +1699,7 @@ static const struct pcie_cfg_data bcm7435_cfg =3D { =20 static const struct pcie_cfg_data bcm4908_cfg =3D { .offsets =3D pcie_offsets, - .type =3D BCM4908, + .soc_base =3D BCM4908, .perst_set =3D brcm_pcie_perst_set_4908, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, .num_inbound_wins =3D 3, @@ -1715,7 +1715,7 @@ static const int pcie_offset_bcm7278[] =3D { =20 static const struct pcie_cfg_data bcm7278_cfg =3D { .offsets =3D pcie_offset_bcm7278, - .type =3D BCM7278, + .soc_base =3D BCM7278, .perst_set =3D brcm_pcie_perst_set_7278, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_7278, .num_inbound_wins =3D 3, @@ -1723,7 +1723,7 @@ static const struct pcie_cfg_data bcm7278_cfg =3D { =20 static const struct pcie_cfg_data bcm2711_cfg =3D { .offsets =3D pcie_offsets, - .type =3D BCM2711, + .soc_base =3D BCM2711, .perst_set =3D brcm_pcie_perst_set_generic, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, .num_inbound_wins =3D 3, @@ -1731,7 +1731,7 @@ static const struct pcie_cfg_data bcm2711_cfg =3D { =20 static const struct pcie_cfg_data bcm7216_cfg =3D { .offsets =3D pcie_offset_bcm7278, - .type =3D BCM7278, + .soc_base =3D BCM7278, .perst_set =3D brcm_pcie_perst_set_7278, .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_7278, .has_phy =3D true, @@ -1788,7 +1788,7 @@ static int brcm_pcie_probe(struct platform_device *pd= ev) pcie->dev =3D &pdev->dev; pcie->np =3D np; pcie->reg_offsets =3D data->offsets; - pcie->type =3D data->type; + pcie->soc_base =3D data->soc_base; pcie->perst_set =3D data->perst_set; pcie->bridge_sw_init_set =3D data->bridge_sw_init_set; pcie->has_phy =3D data->has_phy; @@ -1858,7 +1858,7 @@ static int brcm_pcie_probe(struct platform_device *pd= ev) goto fail; =20 pcie->hw_rev =3D readl(pcie->base + PCIE_MISC_REVISION); - if (pcie->type =3D=3D BCM4908 && pcie->hw_rev >=3D BRCM_PCIE_HW_REV_3_20)= { + if (pcie->soc_base =3D=3D BCM4908 && pcie->hw_rev >=3D BRCM_PCIE_HW_REV_3= _20) { dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n"); ret =3D -ENODEV; goto fail; @@ -1871,7 +1871,7 @@ static int brcm_pcie_probe(struct platform_device *pd= ev) goto fail; } =20 - bridge->ops =3D pcie->type =3D=3D BCM7425 ? &brcm7425_pcie_ops : &brcm_pc= ie_ops; + bridge->ops =3D pcie->soc_base =3D=3D BCM7425 ? &brcm7425_pcie_ops : &brc= m_pcie_ops; bridge->sysdata =3D pcie; =20 platform_set_drvdata(pdev, pcie); --=20 2.17.1 From nobody Sat Feb 7 16:26:36 2026 Received: from mail-ot1-f43.google.com (mail-ot1-f43.google.com [209.85.210.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CAB116D9DF for ; Wed, 31 Jul 2024 22:28:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722464935; cv=none; b=MqiYgpD58zhIukUrr4RCdziWcgs+OzVs9yMjBdMmrbIuf38J2h9X6W2E7W1J7ktwaunbmhOUoXiBCAEneKm06R737ZwLaGzMIiqA5OL6DAJu86bDY/V9u/xyxRp7o0oSGukNjqas2is+GtsGUL/HSt/Y2rGKroZlfu36BUB1cTU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722464935; c=relaxed/simple; bh=vMmafbjGGptgOc928LWw3HzijtKQn7umoBI3Z8nrrhU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=IJ+Odmg5p1i4yk8JKlkSonY2PILcETTWL9TRosO42Eet1nQt6NgXaBaDE7W5G2e6B+qazo6KzVePsSWsLYSL83VcmW08ViEZgsf7L3T4lm3uKYi+jqLH31XIiXOutykyhZAGBPW1Lx/vv/NEp9ogOA5hrzAZsOf0OFVWtTPfk6M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=P4Nt85ZW; arc=none smtp.client-ip=209.85.210.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="P4Nt85ZW" Received: by mail-ot1-f43.google.com with SMTP id 46e09a7af769-709485aca4bso2649488a34.1 for ; Wed, 31 Jul 2024 15:28:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1722464933; x=1723069733; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=48kNXVxTxIS1qqb8DRwWYkv7S1xxdo30DtPId8NrWW4=; b=P4Nt85ZWFaJw34g5bso1bpAimKBVe4hcNGUKvo/9+HYteosKysA5dquwMKR3TlFTzn BScVbS5K1Cs0rNo0iKKhvLlV8+AfeLGTsHzraNshYzlDOStnOw32ttJ7Xlj1AGQVTsyv oLf/odzRidX6mkfPmUDZL86/BOTqKTCPNcVjw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722464933; x=1723069733; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=48kNXVxTxIS1qqb8DRwWYkv7S1xxdo30DtPId8NrWW4=; b=bK0igTDVOe5Nz8kVJBRkBw+3Jrsg+9XMNfBxsjC5FGjdNuw9WBwzfK2IcIh/gZE5ef qyFdF5N0vF/LUH3TpVMLfLbRpfzkBA4//1TIddWuD3NyaJDLsz7pblXvRFUvxj/NLfMg 3QN/dFrSP65fqFRvjCGvyJiuc37gbm9q651wsD26k7vFgA3K72JZ79d+Ho1u3/kNlRvq ALAHJiirC8hlnXODNjFT/wehMPAab43q8BAl6dz9tau6RN0F5M9nyyoGGOSoCpikiVgR EfihYGoU3Jw8QwATG3/zFn9+7O2yp5DqQ7qqff8CXY8j3JiYLyTl9TxzX/GJQcEjopgh jHAQ== X-Forwarded-Encrypted: i=1; AJvYcCU+1DDruE0sWj68hVyN2W4u0N1ciCwlqfi2VUcqQpEhDaAG7q4+hESY/rKhEYlLbqpa0H+9HZk0FjrxZUNup6EyxIENLCRN5mRAGt5o X-Gm-Message-State: AOJu0YyEDWNAob6GVA3ep77a8OYzqiJtGF2i7t/+WVNfUh0pwCF5QvsI 75BgSt7FO554Hm131zGWonxRNyGFYQNqdnmRwXmW9vMT2pBIdJpeOw2AFEAWTQ== X-Google-Smtp-Source: AGHT+IG0HTaGPAQVkMi4hiaQmCdPYjlys/O4jVp+HDfUjEJVYYKtUw47a6LfeJvzWSfPWDUXJnJ9nw== X-Received: by 2002:a05:6830:2a8d:b0:704:3fea:5354 with SMTP id 46e09a7af769-7096b80ab4fmr546436a34.10.1722464933013; Wed, 31 Jul 2024 15:28:53 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-44fe8416c80sm62359181cf.96.2024.07.31.15.28.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jul 2024 15:28:52 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 12/12] PCI: brcmstb: Enable 7712 SOCs Date: Wed, 31 Jul 2024 18:28:26 -0400 Message-Id: <20240731222831.14895-13-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240731222831.14895-1-james.quinlan@broadcom.com> References: <20240731222831.14895-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The Broadcom STB 7712 is the sibling chip of the RPi 5 (2712). It has one PCIe controller with a single port, supports gen2 and one lane only. The current revision of the chip is "C0" or "C1". Signed-off-by: Jim Quinlan Reviewed-by: Stanimir Varbanov Reviewed-by: Florian Fainelli Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/pcie-brcmstb.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 4623b70f9ad8..44b323a13357 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -1202,6 +1202,10 @@ static void brcm_extend_rbus_timeout(struct brcm_pci= e *pcie) const unsigned int REG_OFFSET =3D PCIE_RGR1_SW_INIT_1(pcie) - 8; u32 timeout_us =3D 4000000; /* 4 seconds, our setting for L1SS */ =20 + /* 7712 does not have this (RGR1) timer */ + if (pcie->soc_base =3D=3D BCM7712) + return; + /* Each unit in timeout register is 1/216,000,000 seconds */ writel(216 * timeout_us, pcie->base + REG_OFFSET); } @@ -1673,6 +1677,13 @@ static const int pcie_offsets_bmips_7425[] =3D { [PCIE_INTR2_CPU_BASE] =3D 0x4300, }; =20 +static const int pcie_offset_bcm7712[] =3D { + [EXT_CFG_INDEX] =3D 0x9000, + [EXT_CFG_DATA] =3D 0x9004, + [PCIE_HARD_DEBUG] =3D 0x4304, + [PCIE_INTR2_CPU_BASE] =3D 0x4400, +}; + static const struct pcie_cfg_data generic_cfg =3D { .offsets =3D pcie_offsets, .soc_base =3D GENERIC, @@ -1738,6 +1749,14 @@ static const struct pcie_cfg_data bcm7216_cfg =3D { .num_inbound_wins =3D 3, }; =20 +static const struct pcie_cfg_data bcm7712_cfg =3D { + .offsets =3D pcie_offset_bcm7712, + .perst_set =3D brcm_pcie_perst_set_7278, + .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, + .soc_base =3D BCM7712, + .num_inbound_wins =3D 10, +}; + static const struct of_device_id brcm_pcie_match[] =3D { { .compatible =3D "brcm,bcm2711-pcie", .data =3D &bcm2711_cfg }, { .compatible =3D "brcm,bcm4908-pcie", .data =3D &bcm4908_cfg }, @@ -1747,6 +1766,7 @@ static const struct of_device_id brcm_pcie_match[] = =3D { { .compatible =3D "brcm,bcm7445-pcie", .data =3D &generic_cfg }, { .compatible =3D "brcm,bcm7435-pcie", .data =3D &bcm7435_cfg }, { .compatible =3D "brcm,bcm7425-pcie", .data =3D &bcm7425_cfg }, + { .compatible =3D "brcm,bcm7712-pcie", .data =3D &bcm7712_cfg }, {}, }; =20 --=20 2.17.1