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[2a03:2880:30ff:4::face:b00c]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5ac631b0395sm8918585a12.20.2024.07.31.08.47.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jul 2024 08:47:05 -0700 (PDT) From: Breno Leitao To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , Thomas Gleixner , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" Cc: leit@meta.com, "Paul E . McKenney" , Sandipan Das , linux-perf-users@vger.kernel.org (open list:PERFORMANCE EVENTS SUBSYSTEM), linux-kernel@vger.kernel.org (open list:PERFORMANCE EVENTS SUBSYSTEM) Subject: [PATCH v2] perf/x86/amd: Warn only on new bits set Date: Wed, 31 Jul 2024 08:46:51 -0700 Message-ID: <20240731154651.1555511-1-leitao@debian.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Warning at every leaking bits can cause a flood of message, triggering vairous stall-warning mechanisms to fire, including CSD locks, which makes the machine to be unusable. Track the bits that are being leaked, and only warn when a new bit is set. That said, this patch will help with the following issues: 1) It will tell us which bits are being set, so, it is easy to communicate it back to vendor, and to do a root-cause analyzes. 2) It avoid the machine to be unusable, because, worst case scenario, the user gets less than 60 WARNs (one per unhandled bit). Suggested-by: Paul E. McKenney Reviewed-by: Sandipan Das Signed-off-by: Breno Leitao --- Changelog: v2: * Improved the patch description, getting the benefits in words. v1: * https://lore.kernel.org/all/20240524141021.3889002-1-leitao@debian.org/ arch/x86/events/amd/core.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c index 920e3a640cad..577158d0c324 100644 --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -943,11 +943,12 @@ static int amd_pmu_v2_snapshot_branch_stack(struct pe= rf_branch_entry *entries, u static int amd_pmu_v2_handle_irq(struct pt_regs *regs) { struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); + static atomic64_t status_warned =3D ATOMIC64_INIT(0); + u64 reserved, status, mask, new_bits; struct perf_sample_data data; struct hw_perf_event *hwc; struct perf_event *event; int handled =3D 0, idx; - u64 reserved, status, mask; bool pmu_enabled; =20 /* @@ -1012,7 +1013,11 @@ static int amd_pmu_v2_handle_irq(struct pt_regs *reg= s) * the corresponding PMCs are expected to be inactive according to the * active_mask */ - WARN_ON(status > 0); + if (status > 0) { + new_bits =3D atomic64_fetch_or(status, &status_warned) ^ atomic64_read(&= status_warned); + // A new bit was set for the very first time. + WARN(new_bits, "New overflows for inactive PMCs: %llx\n", new_bits); + } =20 /* Clear overflow and freeze bits */ amd_pmu_ack_global_status(~status); --=20 2.43.0