From nobody Tue Feb 10 01:59:24 2026 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1947B1BE227; Wed, 31 Jul 2024 17:11:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722445876; cv=none; b=QRluBDox4/oH2Y2vZoCRPJxvqpj7jjWYvW1TOOHlXHdzmJ8H/KtPqKkQoDRFWVMVlbJGXB2ZrfN8/hd+4JCqPht3MX9VrX0ety6Hw98YovT3xcFb6Ybv4V5BqPkrVmDvACorwhpxBPjGV2j2bXAZ9vITlGNxlS2nsYOM5PVdndU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722445876; c=relaxed/simple; bh=bLKIStg32CKaj6+VtwdHIZvNTmLrFgAVJyIBzHe+KWc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=ZqzvUV9kfD7A/Yb6KrbMsCRYWZy/efiB3rjZtIvOA7990vrhlm+EjAswBMuqR94YjatgLdEKk3tt5EJ6oLCqcvGLWstTJ+c/7VSs4ZbK6+2bcScOqIE++/gMfM2LWep7cpgSSn09LK2fLGNb5NlC0VUzR5rHU3NpshNaWYbtnLg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=jViwoHkM; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="jViwoHkM" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 46VHB9l3117367; Wed, 31 Jul 2024 12:11:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1722445869; bh=m8yE4PnEM9kCNwvR96U6Zj1VFy8LOKMPDIbWtSVfzE4=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=jViwoHkMf7BhDByqtGuxiueikGLsGl1rKo5oIhHK5eyv6A4SnnqXqbTnmy6eVdXLg ZdkEOHFmxW9LbOiYZnctkK6Mxd4p+th3D5bwGyZZvR2Z3A/4bP4dWZr9r8lm+VCrMv wxAp7t4yLBi0+uKSZPJnxRdFlQdXvcbc6Og96/hQ= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 46VHB9Gl109252 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 31 Jul 2024 12:11:09 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 31 Jul 2024 12:11:09 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 31 Jul 2024 12:11:09 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 46VHAVgW036362; Wed, 31 Jul 2024 12:11:06 -0500 From: Manorit Chawdhry Date: Wed, 31 Jul 2024 22:40:35 +0530 Subject: [PATCH v3 9/9] arm64: dts: ti: Add support for J742S2 EVM board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240731-b4-upstream-j742s2-v3-9-da7fe3aa9e90@ti.com> References: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> In-Reply-To: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Udit Kumar , Neha Malcom Francis , Aniket Limaye , Manorit Chawdhry X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1722445831; l=3518; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=bLKIStg32CKaj6+VtwdHIZvNTmLrFgAVJyIBzHe+KWc=; b=ihjIAZX8EBLlNu8Yw2LQskvPqfR4ghVf2LcNY2eyB3HR/dRzUDpo5AIAp0Orv4gmPc/iHTjfr NmXYKk1G3X8BUmZTOiCeTOyiHWoPBXKsI7v6WbDc20fCvXle/+zcm5n X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 J742S2 EVM board is designed for TI J742S2 SoC. It supports the following interfaces: * 16 GB DDR4 RAM * x2 Gigabit Ethernet interfaces capable of working in Switch and MAC mode * x1 Input Audio Jack, x1 Output Audio Jack * x1 USB2.0 Hub with two Type A host and x1 USB 3.1 Type-C Port * x1 4L PCIe connector * x1 UHS-1 capable micro-SD card slot * 512 Mbit OSPI flash, 1 Gbit Octal NAND flash, 512 Mbit QSPI flash, UFS flash. * x6 UART through UART-USB bridge * XDS110 for onboard JTAG debug using USB * Temperature sensors, user push buttons and LEDs * x1 GESI expander, x2 Display connector * x1 15-pin CSI header * x6 MCAN instances Link: https://www.ti.com/lit/ug/sprujd8/sprujd8.pdf (EVM user guide) Link: https://www.ti.com/lit/zip/SPAC001 (Schematics) Signed-off-by: Manorit Chawdhry Reviewed-By: Beleswar Padhi --- arch/arm64/boot/dts/ti/Makefile | 4 ++++ arch/arm64/boot/dts/ti/k3-j742s2-evm.dts | 26 ++++++++++++++++++= ++++ .../boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 3 ++- 3 files changed, 32 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index e20b27ddf901..1bf645726a10 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -119,6 +119,9 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-pcie0-pcie1-ep= .dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-quad-port-eth-exp1.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-usxgmii-exp1-exp2.dtbo =20 +# Boards with J742S2 SoC +dtb-$(CONFIG_ARCH_K3) +=3D k3-j742s2-evm.dtb + # Build time test only, enabled by CONFIG_OF_ALL_DTBS k3-am625-beagleplay-csi2-ov5640-dtbs :=3D k3-am625-beagleplay.dtb \ k3-am625-beagleplay-csi2-ov5640.dtbo @@ -240,3 +243,4 @@ DTC_FLAGS_k3-j721e-common-proc-board +=3D -@ DTC_FLAGS_k3-j721e-sk +=3D -@ DTC_FLAGS_k3-j721s2-common-proc-board +=3D -@ DTC_FLAGS_k3-j784s4-evm +=3D -@ +DTC_FLAGS_k3-j742s2-evm +=3D -@ diff --git a/arch/arm64/boot/dts/ti/k3-j742s2-evm.dts b/arch/arm64/boot/dts= /ti/k3-j742s2-evm.dts new file mode 100644 index 000000000000..ac683bcbfe97 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j742s2-evm.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * + * EVM Board Schematics: https://www.ti.com/lit/zip/SPAC001 + */ + +/dts-v1/; + +#include +#include +#include "k3-j742s2.dtsi" +#include "k3-j784s4-j742s2-evm-common.dtsi" + +/ { + model =3D "Texas Instruments J742S2 EVM"; + compatible =3D "ti,j742s2-evm", "ti,j742s2"; + + memory@80000000 { + device_type =3D "memory"; + bootph-all; + /* 16G RAM */ + reg =3D <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000003 0x80000000>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch= /arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi index 068ceed4ea15..a7bb1857b4e8 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi @@ -2,7 +2,8 @@ /* * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti= .com/ * - * EVM Board Schematics: https://www.ti.com/lit/zip/sprr458 + * EVM Board Schematics(j784s4): https://www.ti.com/lit/zip/sprr458 + * EVM Board Schematics(j742s2): https://www.ti.com/lit/zip/SPAC001 */ / { chosen { --=20 2.45.1