From nobody Mon Feb 9 16:02:45 2026 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 696B91BF32B; Wed, 31 Jul 2024 17:11:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722445873; cv=none; b=MbmCF3abm9pQiho+TF36p9MFDqio2cfXTe4V8ltcKeTyVBgLHarnhYo0DSpSC1aLnSqVZGkykJHS4//1HV8WwvC7nJOduDTTZQ6pJb7Z++P6u84mqEVorHsUQ6x0LcZaBsYvNeUu+N5iglCD2coLUQ2ipXupbb0LjANEX5w1iqk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722445873; c=relaxed/simple; bh=By+tJFbhJfeTWyNNGJuwnR1vAIVP3c4xKyvcdU6oMWo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=MtbnomuLoCsp5ZXFP1ZPpq7XFBvjswPiGAs+K0qGyQBZqG6G5QQydpha2ftioh5OEfyKv2S2T6SVeH06Y8I3O91CNH0a2fAPF8RcxnADyJNkLUBdxLkDctLWkGbnfb39nir8X8YdDMvnc0TLgQHo+NrHNPQFW5hl1oBOD0scrPw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=vd1cjBHh; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="vd1cjBHh" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 46VHB6lu090565; Wed, 31 Jul 2024 12:11:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1722445866; bh=6g9jwnaOxNsC1QlfmvMcnz6WmMwojd9rL7P/E6rLns0=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=vd1cjBHhZVz7q32htoiPcjWiX6dRV2yqM6bEjmr3HuEmd1YNzERGQCwDkF8RawBwI mn2UNy8hjyzh6uNQrnkkSFDaRl5ZnTV96V9iybvHWsJu1/2vr7uqrRk7f8qnD17+XC ZRRmzGedbZkfPJ2MUxeK1AFZti0/BIEst7BV/Qb4= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 46VHB6uD109225 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 31 Jul 2024 12:11:06 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 31 Jul 2024 12:11:05 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 31 Jul 2024 12:11:05 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 46VHAVgV036362; Wed, 31 Jul 2024 12:11:02 -0500 From: Manorit Chawdhry Date: Wed, 31 Jul 2024 22:40:34 +0530 Subject: [PATCH v3 8/9] arm64: dts: ti: Introduce J742S2 SoC family Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240731-b4-upstream-j742s2-v3-8-da7fe3aa9e90@ti.com> References: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> In-Reply-To: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Udit Kumar , Neha Malcom Francis , Aniket Limaye , Manorit Chawdhry X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1722445831; l=5457; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=By+tJFbhJfeTWyNNGJuwnR1vAIVP3c4xKyvcdU6oMWo=; b=QmOxY/XVUe6/61GBkqbK1VDwWMnKUUfXrKv7fuPVQq5z991GdbKfUTT5FWV7d1hQrIBWVESVO Cwc3JwT3SNYBZTIgHD0B3HJ5mQwmbwrCAH1VBlYNeqaO35H+vyhZU12 X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 This device is a subset of J784S4 and shares the same memory map and thus the nodes are being reused from J784S4 to avoid duplication. Here are some of the salient features of the J742S2 automotive grade application processor: The J742S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive, ADAS and industrial applications requiring AI at the network edge. This SoC extends the K3 Jacinto 7 family of SoCs with focus on raising performance and integration while providing interfaces, memory architecture and compute performance for multi-sensor, high concurrency applications. Some changes that this devices has from J784S4 are: * 4x Cortex-A72 vs 8x Cortex-A72 * 3x C7x DSP vs 4x C7x DSP * 4 port ethernet switch vs 8 port ethernet switch ( Refer Table 2-1 for Device comparison with J7AHP ) Link: https://www.ti.com/lit/pdf/spruje3 (TRM) Signed-off-by: Manorit Chawdhry --- arch/arm64/boot/dts/ti/k3-j742s2-main.dtsi | 45 ++++++++++ arch/arm64/boot/dts/ti/k3-j742s2.dtsi | 98 ++++++++++++++++++= ++++ .../arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi | 5 +- 3 files changed, 146 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j742s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j742s2-main.dtsi new file mode 100644 index 000000000000..b320c27f7afe --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j742s2-main.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree Source for J742S2 SoC Family + * + * TRM: https://www.ti.com/lit/pdf/spruje3 + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +&c71_0 { + firmware-name =3D "j742s2-c71_0-fw"; +}; + +&c71_1 { + firmware-name =3D "j742s2-c71_1-fw"; +}; + +&c71_2 { + firmware-name =3D "j742s2-c71_2-fw"; +}; + +&main_r5fss0_core0 { + firmware-name =3D "j742s2-main-r5f0_0-fw"; +}; + +&main_r5fss0_core1 { + firmware-name =3D "j742s2-main-r5f0_1-fw"; +}; + +&main_r5fss1_core0 { + firmware-name =3D "j742s2-main-r5f1_0-fw"; +}; + +&main_r5fss1_core1 { + firmware-name =3D "j742s2-main-r5f1_1-fw"; +}; + +&main_r5fss2_core0 { + firmware-name =3D "j742s2-main-r5f2_0-fw"; +}; + +&main_r5fss2_core1 { + firmware-name =3D "j742s2-main-r5f2_1-fw"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j742s2.dtsi b/arch/arm64/boot/dts/ti= /k3-j742s2.dtsi new file mode 100644 index 000000000000..7a72f82f56d6 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j742s2.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree Source for J742S2 SoC Family + * + * TRM: https://www.ti.com/lit/pdf/spruje3 + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * + */ +#include "k3-j784s4-j742s2-common.dtsi" + +/ { + model =3D "Texas Instruments K3 J742S2 SoC"; + compatible =3D "ti,j742s2"; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x000>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; + }; + + cpu1: cpu@1 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x001>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; + }; + + cpu2: cpu@2 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x002>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; + }; + + cpu3: cpu@3 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x003>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; + }; + }; +}; + +#include "k3-j742s2-main.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi b/arch/arm= 64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi index 958054ab1018..43fee57f0926 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Device Tree Source for J784S4 SoC Family + * Device Tree Source for J784S4 and J742S2 SoC Family * - * TRM (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52 + * TRM (j784s4) (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52 + * TRM (j742s2): https://www.ti.com/lit/pdf/spruje3 * * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti= .com/ * --=20 2.45.1