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Wed, 31 Jul 2024 12:10:58 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 31 Jul 2024 12:10:58 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 31 Jul 2024 12:10:58 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 46VHAVgT036362; Wed, 31 Jul 2024 12:10:54 -0500 From: Manorit Chawdhry Date: Wed, 31 Jul 2024 22:40:32 +0530 Subject: [PATCH v3 6/9] arm64: dts: ti: Split k3-j784s4-j742s2-evm-common.dtsi Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240731-b4-upstream-j742s2-v3-6-da7fe3aa9e90@ti.com> References: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> In-Reply-To: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Udit Kumar , Neha Malcom Francis , Aniket Limaye , Manorit Chawdhry X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1722445831; l=3971; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=Dp1xqNmWjeEfyr8ivz3G2b03eCcQ102npwLXFy/YWnY=; b=zqkjf/ntxkB2RWXxq2+tCnvBJZBixmFo5VYVDX995HSltebQsEfm4f1xXpGcOFCVAfNigi+Dx iKJuhr509S6BUcoxcc9Qn8l/PHc9xOi2Ux/ilyY5qw6fmSFoyKYRGZK X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 k3-j784s4-j742s2-evm-common.dtsi will be included in k3-j742s2-evm.dts at a later point so move j784s4 related stuff to k3-j784s4-evm.dts Signed-off-by: Manorit Chawdhry --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 49 ++++++++++++++++++= ++++ .../boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 42 ------------------- 2 files changed, 49 insertions(+), 42 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts= /ti/k3-j784s4-evm.dts index e3730b2bca92..2543983b7fe7 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -5,4 +5,53 @@ * EVM Board Schematics: https://www.ti.com/lit/zip/sprr458 */ =20 +/dts-v1/; + +#include +#include +#include "k3-j784s4.dtsi" #include "k3-j784s4-j742s2-evm-common.dtsi" + +/ { + compatible =3D "ti,j784s4-evm", "ti,j784s4"; + model =3D "Texas Instruments J784S4 EVM"; + + memory@80000000 { + device_type =3D "memory"; + bootph-all; + /* 32G RAM */ + reg =3D <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000007 0x80000000>; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + + c71_3_dma_memory_region: c71-dma-memory@ab000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xab000000 0x00 0x100000>; + no-map; + }; + + c71_3_memory_region: c71-memory@ab100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xab100000 0x00 0xf00000>; + no-map; + }; + }; +}; + +&mailbox0_cluster5 { + mbox_c71_3: mbox-c71-3 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&c71_3 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster5 &mbox_c71_3>; + memory-region =3D <&c71_3_dma_memory_region>, + <&c71_3_memory_region>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch= /arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi index ffa38f41679d..068ceed4ea15 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi @@ -4,17 +4,7 @@ * * EVM Board Schematics: https://www.ti.com/lit/zip/sprr458 */ - -/dts-v1/; - -#include -#include -#include "k3-j784s4.dtsi" - / { - compatible =3D "ti,j784s4-evm", "ti,j784s4"; - model =3D "Texas Instruments J784S4 EVM"; - chosen { stdout-path =3D "serial2:115200n8"; }; @@ -31,14 +21,6 @@ aliases { ethernet1 =3D &main_cpsw1_port1; }; =20 - memory@80000000 { - device_type =3D "memory"; - bootph-all; - /* 32G RAM */ - reg =3D <0x00000000 0x80000000 0x00000000 0x80000000>, - <0x00000008 0x80000000 0x00000007 0x80000000>; - }; - reserved_memory: reserved-memory { #address-cells =3D <2>; #size-cells =3D <2>; @@ -180,18 +162,6 @@ c71_2_memory_region: c71-memory@aa100000 { reg =3D <0x00 0xaa100000 0x00 0xf00000>; no-map; }; - - c71_3_dma_memory_region: c71-dma-memory@ab000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xab000000 0x00 0x100000>; - no-map; - }; - - c71_3_memory_region: c71-memory@ab100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xab100000 0x00 0xf00000>; - no-map; - }; }; =20 evm_12v0: regulator-evm12v0 { @@ -1133,11 +1103,6 @@ mbox_c71_2: mbox-c71-2 { ti,mbox-rx =3D <0 0 0>; ti,mbox-tx =3D <1 0 0>; }; - - mbox_c71_3: mbox-c71-3 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; }; =20 &mcu_r5fss0_core0 { @@ -1217,13 +1182,6 @@ &c71_2 { <&c71_2_memory_region>; }; =20 -&c71_3 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster5 &mbox_c71_3>; - memory-region =3D <&c71_3_dma_memory_region>, - <&c71_3_memory_region>; -}; - &tscadc0 { pinctrl-0 =3D <&mcu_adc0_pins_default>; pinctrl-names =3D "default"; --=20 2.45.1