From nobody Sun Feb 8 17:46:43 2026 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7461E1BD4ED; Wed, 31 Jul 2024 17:10:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722445849; cv=none; b=L2hgVjX8IHmgdCtIdXEu+2hoZjIaq/9q6ciZOoxbVDn9jTL4w0ar6mMkoScs6PWJUlshAPdVROPPB7B2C50e40cTNr9NWqwak82H0cTFSv7yAS7mokRYJgm3yOwpILtZXkzoQ/YdcFTmOak3XHEJqGMJomv7zYCj/vzXuYsp6fg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722445849; c=relaxed/simple; bh=KM94wb8SuRIdpVfm4xCuPtTZylQRif7udldhutgnZw4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Refb5DrlnvzWkkJtTLJra+56mYiRM/xItC9eSl3XHiec8mBLr1VYkqRhdd6w2IwEFH8GyCYsftRRGAm/aqU87SGDWlcpimSyW6gjxoIFdAAHA8HOPomQ31c1BHuZtjLIM6ek9Yz/2c+L34MeQqKzN7hWFpS7JUbwTrhImxMQtHs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=w5zfckEp; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="w5zfckEp" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 46VHAdx4108309; Wed, 31 Jul 2024 12:10:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1722445839; bh=zlhZl1fpMtrinZXymNW6JMSzbiViJzfmhLV/rRTKFKo=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=w5zfckEpPLcNKAb+6nG0CPzWyBzoVWdeGypu+4lHTHqSpmeTisfUumOsf2BUO6JJZ BryLbWcJv+3ynm8vZtQrJXrsJgdqUiYZzFoFNTr2V0CxVS90vff5mv7mFzXxUCNxrh ctBTmPD7t8nf/zeNtX3b7/J+P09f7Wx28Kkq4Ovc= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 46VHAd3C082425 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 31 Jul 2024 12:10:39 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 31 Jul 2024 12:10:39 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 31 Jul 2024 12:10:39 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 46VHAVgO036362; Wed, 31 Jul 2024 12:10:36 -0500 From: Manorit Chawdhry Date: Wed, 31 Jul 2024 22:40:27 +0530 Subject: [PATCH v3 1/9] arm64: dts: ti: Move j784s4-{} include files to j784s4-j742s2-{}-common.dtsi Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240731-b4-upstream-j742s2-v3-1-da7fe3aa9e90@ti.com> References: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> In-Reply-To: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Udit Kumar , Neha Malcom Francis , Aniket Limaye , Manorit Chawdhry X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1722445831; l=3022; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=KM94wb8SuRIdpVfm4xCuPtTZylQRif7udldhutgnZw4=; b=tGGJ7k1kPGo25yzuUOBTJit1k2bsNbaJoLy+XeNMCT6kxlX84Ih/QLuByt3X7MYkZPAb3Vf5a aadrohgbneYCd5dLCD81SpdYYmU1MsWNZ0lUlKuTbDbZ84dDr3HMP3+ X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 J784S4 shares a lot of things with J742s2. Move the files to common so that the split between j784s4 and j742s2 can be done at a later point. Signed-off-by: Manorit Chawdhry --- .../ti/{k3-j784s4-main.dtsi =3D> k3-j784s4-j742s2-main-common.dtsi} | 2 = +- ...84s4-mcu-wakeup.dtsi =3D> k3-j784s4-j742s2-mcu-wakeup-common.dtsi} | 2 = +- ...{k3-j784s4-thermal.dtsi =3D> k3-j784s4-j742s2-thermal-common.dtsi} | 0 arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 6 ++= +--- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-j742s2-main-common.dtsi similarity index 99% rename from arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi rename to arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index f170f80f00c1..17abd0f1560a 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Device Tree Source for J784S4 SoC Family Main Domain peripherals + * Device Tree Source for J784S4 and J742S2 SoC Family Main Domain periphe= rals * * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti= .com/ */ diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi similarity index 99% rename from arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi rename to arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi index f3a6ed1c979d..346623fa2ee9 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Device Tree Source for J784S4 SoC Family MCU/WAKEUP Domain peripherals + * Device Tree Source for J784S4 and J742S2 SoC Family MCU/WAKEUP Domain p= eripherals * * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti= .com/ */ diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-thermal.dtsi b/arch/arm64/boo= t/dts/ti/k3-j784s4-j742s2-thermal-common.dtsi similarity index 100% rename from arch/arm64/boot/dts/ti/k3-j784s4-thermal.dtsi rename to arch/arm64/boot/dts/ti/k3-j784s4-j742s2-thermal-common.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti= /k3-j784s4.dtsi index 73cc3c1fec08..76e43ee44496 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi @@ -296,10 +296,10 @@ cbass_mcu_wakeup: bus@28380000 { }; =20 thermal_zones: thermal-zones { - #include "k3-j784s4-thermal.dtsi" + #include "k3-j784s4-j742s2-thermal-common.dtsi" }; }; =20 /* Now include peripherals from each bus segment */ -#include "k3-j784s4-main.dtsi" -#include "k3-j784s4-mcu-wakeup.dtsi" +#include "k3-j784s4-j742s2-main-common.dtsi" +#include "k3-j784s4-j742s2-mcu-wakeup-common.dtsi" --=20 2.45.1 From nobody Sun Feb 8 17:46:43 2026 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD84B1BD038; Wed, 31 Jul 2024 17:10:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722445858; cv=none; b=gjWuWnZHmg9GTipWlpy1Y3dkwfsREpOkuLdJTgovyO8yIU1rpMgUl1Ex1P3OClIX89/mzAdnaLGN7Ig+zBmTCxVjn38e2Q9NuoPGMZp3CWgArsuH4Km5VmGDLg+jKRjEfU5DRa3i8m6Ku3GYC8kkeWZNfV/xtBNRVmhfJW8XJM4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722445858; c=relaxed/simple; bh=NQJhLkVUf4L1m2n4sGBHvUR7/0T/0z4Uo6zxCI/5Gsk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=glR9frBLgx50tYxl8GuOBNP+bVsNC8UijlHpJJhL/OQebBlXrWQL75HBFI9nzNvNCH07SwyUahkmtBN9sA6FXXQxuP6s10erDp0YIV2z5ADRcPbuGedCih8PSs8t/IxknanYsrswM8px70+RSZfaVH1KlHXgZ/DyyetRFF34Hns= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=xySRrZLp; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="xySRrZLp" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 46VHAhCM108324; Wed, 31 Jul 2024 12:10:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1722445843; bh=Trcpyc/NIUJEZNBzu4/5khk9DVmAdX9BtlRoMb1AqFU=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=xySRrZLp50/u6wIv4Lk+iTS0vw0/WI81d3EwNqLNensUSTiV9Jc6qr3CnA8a0U2PQ vZy3NcmiKUgfP+dT6dzk+K5hDrE3o1WiaEp/0Rs5QlKlLWF6mQoHfkUVGUh/GWPJdw 9XmgHKFPWUA5wCLJ4LMVRmr2R4yTokryjASo0i9o= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 46VHAh2t123626 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 31 Jul 2024 12:10:43 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 31 Jul 2024 12:10:43 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 31 Jul 2024 12:10:43 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 46VHAVgP036362; Wed, 31 Jul 2024 12:10:39 -0500 From: Manorit Chawdhry Date: Wed, 31 Jul 2024 22:40:28 +0530 Subject: [PATCH v3 2/9] arm64: dts: ti: Move k3-j784s4.dtsi to k3-j784s4-j742s2-common.dtsi Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240731-b4-upstream-j742s2-v3-2-da7fe3aa9e90@ti.com> References: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> In-Reply-To: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Udit Kumar , Neha Malcom Francis , Aniket Limaye , Manorit Chawdhry X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1722445831; l=19673; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=NQJhLkVUf4L1m2n4sGBHvUR7/0T/0z4Uo6zxCI/5Gsk=; b=FemCBjcj974/U58xhgeJzduBXBKMKSE1jnfiMNoeUSSAqAt2wDRVe5HnHVDNwvsJAx9nbD4l0 AVqCvn2UEgIAfhv9OFIFlnJWmSCxbxpUG/w/9abcss2IMgsMG1sFWti X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 This is to introduce j742s2 support later, things from here will be moved to appropriate location. File k3-j784s4.dtsi is not exactly removed as the EVM files are dependent on that. Hence to keep the compatibility, after moving; k3-j784s4.dtsi is including k3-j784s4-j742s2-common.dtsi Signed-off-by: Manorit Chawdhry --- .../arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi | 305 +++++++++++++++++= ++++ arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 295 +----------------= --- 2 files changed, 306 insertions(+), 294 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi b/arch/arm= 64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi new file mode 100644 index 000000000000..76e43ee44496 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree Source for J784S4 SoC Family + * + * TRM (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52 + * + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti= .com/ + * + */ + +#include +#include +#include + +#include "k3-pinctrl.h" + +/ { + model =3D "Texas Instruments K3 J784S4 SoC"; + compatible =3D "ti,j784s4"; + interrupt-parent =3D <&gic500>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + cpu-map { + cluster0: cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + }; + + cluster1: cluster1 { + core0 { + cpu =3D <&cpu4>; + }; + + core1 { + cpu =3D <&cpu5>; + }; + + core2 { + cpu =3D <&cpu6>; + }; + + core3 { + cpu =3D <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x000>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; + }; + + cpu1: cpu@1 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x001>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; + }; + + cpu2: cpu@2 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x002>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; + }; + + cpu3: cpu@3 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x003>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; + }; + + cpu4: cpu@100 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x100>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_1>; + }; + + cpu5: cpu@101 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x101>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_1>; + }; + + cpu6: cpu@102 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x102>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_1>; + }; + + cpu7: cpu@103 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x103>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_1>; + }; + }; + + L2_0: l2-cache0 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x200000>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + next-level-cache =3D <&msmc_l3>; + }; + + L2_1: l2-cache1 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x200000>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + next-level-cache =3D <&msmc_l3>; + }; + + msmc_l3: l3-cache0 { + compatible =3D "cache"; + cache-level =3D <3>; + cache-unified; + }; + + firmware { + optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + + psci: psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + }; + + a72_timer0: timer-cl0-cpu0 { + compatible =3D "arm,armv8-timer"; + interrupts =3D , /* cntpsirq */ + , /* cntpnsirq */ + , /* cntvirq */ + ; /* cnthpirq */ + }; + + pmu: pmu { + compatible =3D "arm,cortex-a72-pmu"; + /* Recommendation from GIC500 TRM Table A.3 */ + interrupts =3D ; + }; + + cbass_main: bus@100000 { + bootph-all; + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mm= r */ + <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ + <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals= */ + <0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */ + <0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */ + <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIe0 Core*/ + <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe1 Core*/ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00800000>, /* PCIe2 Core*/ + <0x00 0x0e800000 0x00 0x0e800000 0x00 0x00800000>, /* PCIe3 Core*/ + <0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */ + <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ + <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */ + <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */ + <0x00 0x66800000 0x00 0x66800000 0x00 0x0070c000>, /* C71_3 */ + <0x00 0x67800000 0x00 0x67800000 0x00 0x0070c000>, /* C71_4 */ + <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ + <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */ + <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ + <0x40 0x00000000 0x40 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */ + <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ + <0x42 0x00000000 0x42 0x00000000 0x01 0x00000000>, /* PCIe2 DAT1 */ + <0x43 0x00000000 0x43 0x00000000 0x01 0x00000000>, /* PCIe3 DAT1 */ + <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT0 */ + <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT0 */ + <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ + + /* MCUSS_WKUP Range */ + <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, + <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, + <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; + + cbass_mcu_wakeup: bus@28380000 { + bootph-all; + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NA= VSS*/ + <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First periphera= l window */ + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral= window */ + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining= NAVSS */ + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register s= pace */ + <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 dat= a region 0 */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data = region 3 */ + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data = region 3*/ + }; + }; + + thermal_zones: thermal-zones { + #include "k3-j784s4-j742s2-thermal-common.dtsi" + }; +}; + +/* Now include peripherals from each bus segment */ +#include "k3-j784s4-j742s2-main-common.dtsi" +#include "k3-j784s4-j742s2-mcu-wakeup-common.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti= /k3-j784s4.dtsi index 76e43ee44496..46cff5ed3730 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi @@ -8,298 +8,5 @@ * */ =20 -#include -#include -#include +#include "k3-j784s4-j742s2-common.dtsi" =20 -#include "k3-pinctrl.h" - -/ { - model =3D "Texas Instruments K3 J784S4 SoC"; - compatible =3D "ti,j784s4"; - interrupt-parent =3D <&gic500>; - #address-cells =3D <2>; - #size-cells =3D <2>; - - cpus { - #address-cells =3D <1>; - #size-cells =3D <0>; - cpu-map { - cluster0: cluster0 { - core0 { - cpu =3D <&cpu0>; - }; - - core1 { - cpu =3D <&cpu1>; - }; - - core2 { - cpu =3D <&cpu2>; - }; - - core3 { - cpu =3D <&cpu3>; - }; - }; - - cluster1: cluster1 { - core0 { - cpu =3D <&cpu4>; - }; - - core1 { - cpu =3D <&cpu5>; - }; - - core2 { - cpu =3D <&cpu6>; - }; - - core3 { - cpu =3D <&cpu7>; - }; - }; - }; - - cpu0: cpu@0 { - compatible =3D "arm,cortex-a72"; - reg =3D <0x000>; - device_type =3D "cpu"; - enable-method =3D "psci"; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&L2_0>; - }; - - cpu1: cpu@1 { - compatible =3D "arm,cortex-a72"; - reg =3D <0x001>; - device_type =3D "cpu"; - enable-method =3D "psci"; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&L2_0>; - }; - - cpu2: cpu@2 { - compatible =3D "arm,cortex-a72"; - reg =3D <0x002>; - device_type =3D "cpu"; - enable-method =3D "psci"; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&L2_0>; - }; - - cpu3: cpu@3 { - compatible =3D "arm,cortex-a72"; - reg =3D <0x003>; - device_type =3D "cpu"; - enable-method =3D "psci"; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&L2_0>; - }; - - cpu4: cpu@100 { - compatible =3D "arm,cortex-a72"; - reg =3D <0x100>; - device_type =3D "cpu"; - enable-method =3D "psci"; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&L2_1>; - }; - - cpu5: cpu@101 { - compatible =3D "arm,cortex-a72"; - reg =3D <0x101>; - device_type =3D "cpu"; - enable-method =3D "psci"; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&L2_1>; - }; - - cpu6: cpu@102 { - compatible =3D "arm,cortex-a72"; - reg =3D <0x102>; - device_type =3D "cpu"; - enable-method =3D "psci"; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&L2_1>; - }; - - cpu7: cpu@103 { - compatible =3D "arm,cortex-a72"; - reg =3D <0x103>; - device_type =3D "cpu"; - enable-method =3D "psci"; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&L2_1>; - }; - }; - - L2_0: l2-cache0 { - compatible =3D "cache"; - cache-level =3D <2>; - cache-unified; - cache-size =3D <0x200000>; - cache-line-size =3D <64>; - cache-sets =3D <1024>; - next-level-cache =3D <&msmc_l3>; - }; - - L2_1: l2-cache1 { - compatible =3D "cache"; - cache-level =3D <2>; - cache-unified; - cache-size =3D <0x200000>; - cache-line-size =3D <64>; - cache-sets =3D <1024>; - next-level-cache =3D <&msmc_l3>; - }; - - msmc_l3: l3-cache0 { - compatible =3D "cache"; - cache-level =3D <3>; - cache-unified; - }; - - firmware { - optee { - compatible =3D "linaro,optee-tz"; - method =3D "smc"; - }; - - psci: psci { - compatible =3D "arm,psci-1.0"; - method =3D "smc"; - }; - }; - - a72_timer0: timer-cl0-cpu0 { - compatible =3D "arm,armv8-timer"; - interrupts =3D , /* cntpsirq */ - , /* cntpnsirq */ - , /* cntvirq */ - ; /* cnthpirq */ - }; - - pmu: pmu { - compatible =3D "arm,cortex-a72-pmu"; - /* Recommendation from GIC500 TRM Table A.3 */ - interrupts =3D ; - }; - - cbass_main: bus@100000 { - bootph-all; - compatible =3D "simple-bus"; - #address-cells =3D <2>; - #size-cells =3D <2>; - ranges =3D <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mm= r */ - <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ - <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ - <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals= */ - <0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */ - <0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */ - <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIe0 Core*/ - <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe1 Core*/ - <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00800000>, /* PCIe2 Core*/ - <0x00 0x0e800000 0x00 0x0e800000 0x00 0x00800000>, /* PCIe3 Core*/ - <0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */ - <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ - <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */ - <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */ - <0x00 0x66800000 0x00 0x66800000 0x00 0x0070c000>, /* C71_3 */ - <0x00 0x67800000 0x00 0x67800000 0x00 0x0070c000>, /* C71_4 */ - <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ - <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */ - <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ - <0x40 0x00000000 0x40 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */ - <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ - <0x42 0x00000000 0x42 0x00000000 0x01 0x00000000>, /* PCIe2 DAT1 */ - <0x43 0x00000000 0x43 0x00000000 0x01 0x00000000>, /* PCIe3 DAT1 */ - <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT0 */ - <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT0 */ - <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ - - /* MCUSS_WKUP Range */ - <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, - <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; - - cbass_mcu_wakeup: bus@28380000 { - bootph-all; - compatible =3D "simple-bus"; - #address-cells =3D <2>; - #size-cells =3D <2>; - ranges =3D <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NA= VSS*/ - <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First periphera= l window */ - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral= window */ - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining= NAVSS */ - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register s= pace */ - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 dat= a region 0 */ - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data = region 3 */ - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data = region 3*/ - }; - }; - - thermal_zones: thermal-zones { - #include "k3-j784s4-j742s2-thermal-common.dtsi" - }; -}; - -/* Now include peripherals from each bus segment */ -#include "k3-j784s4-j742s2-main-common.dtsi" -#include "k3-j784s4-j742s2-mcu-wakeup-common.dtsi" --=20 2.45.1 From nobody Sun Feb 8 17:46:43 2026 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CEF5D1BE248; Wed, 31 Jul 2024 17:10:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722445854; cv=none; b=M2YcEX0Ni59sKDpF1e+5Z+5+NhoTt53EwSskAcr3r1gjZR8UQue1uG/Xgkfo+fIY0EVk3PoVXFwZj2BSoFZKwCuA+UAczxfx4iW9jig5HQIqN/ETtY62N8mYkCT2ZUlZfEUgVJ+3EMUMAv3u0/AJgb+eS0oCqcnKgn1u9Gq+Ybw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722445854; c=relaxed/simple; bh=tiZgpMVSYamgxzdjCpc1ORHBAdASeolJLopA9GJxS7g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=mOA8LFVvkuV0Dy8S6mheUiPqKO546A2QzNAkQnCM9dPjXaTEkJGtg741IIR8Z0N34BBu3er7zl3VgihQV1QgBXNEbWUy5FgyXc37G8fW7ZKX6Qe7Mua9t043PR3UYN05FM327oW5qpdKvS9KAsvP6CzDes2olweE4FwnGCsK9FA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=xkHMc/kT; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="xkHMc/kT" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 46VHAlKh090439; Wed, 31 Jul 2024 12:10:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1722445847; bh=3AtFgjJhDFuISlCzXz0wAjKkkwNzREb/N8mjoS1t8SU=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=xkHMc/kTiANgvQDsDUnc3Asy0j0tMl0JbDZxlWqstU5VXGvYEwodQLyBg3mPIVrSU dEky7HmODjbAbtlm92ny6YXk9hVeSFpmj53kIZQqqywWrNM4+6qNGG106jCJ9ssuKP 5YGN/px5a3/qQRrlY/4jdHIKR7L7I4aSnHeNCB4g= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 46VHAl3u123646 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 31 Jul 2024 12:10:47 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 31 Jul 2024 12:10:46 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 31 Jul 2024 12:10:46 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 46VHAVgQ036362; Wed, 31 Jul 2024 12:10:43 -0500 From: Manorit Chawdhry Date: Wed, 31 Jul 2024 22:40:29 +0530 Subject: [PATCH v3 3/9] arm64: dts: ti: Split k3-j784s4-j742s2-common.dtsi Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240731-b4-upstream-j742s2-v3-3-da7fe3aa9e90@ti.com> References: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> In-Reply-To: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Udit Kumar , Neha Malcom Francis , Aniket Limaye , Manorit Chawdhry X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1722445831; l=8025; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=tiZgpMVSYamgxzdjCpc1ORHBAdASeolJLopA9GJxS7g=; b=qmaSfh25Oo0U+Y9xZrOuwl2vqpnHEq0aCMZ81ehmr0q2sG4MHm+vVlcn1emRY/2BavouiLa2a uTQE6rqQRzoBgq3O8vVbViBM8VJeIEVZ8BNmZh0+FC3eyLTc58bL5I2 X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 k3-j784s4-j742s2-common.dtsi will be included in k3-j742s2.dtsi at a later point so move j784s4 related stuff to k3-j784s4.dtsi Signed-off-by: Manorit Chawdhry --- .../arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi | 156 -----------------= --- arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 158 +++++++++++++++++= ++++ 2 files changed, 158 insertions(+), 156 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi b/arch/arm= 64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi index 76e43ee44496..958054ab1018 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi @@ -15,166 +15,10 @@ #include "k3-pinctrl.h" =20 / { - model =3D "Texas Instruments K3 J784S4 SoC"; - compatible =3D "ti,j784s4"; interrupt-parent =3D <&gic500>; #address-cells =3D <2>; #size-cells =3D <2>; =20 - cpus { - #address-cells =3D <1>; - #size-cells =3D <0>; - cpu-map { - cluster0: cluster0 { - core0 { - cpu =3D <&cpu0>; - }; - - core1 { - cpu =3D <&cpu1>; - }; - - core2 { - cpu =3D <&cpu2>; - }; - - core3 { - cpu =3D <&cpu3>; - }; - }; - - cluster1: cluster1 { - core0 { - cpu =3D <&cpu4>; - }; - - core1 { - cpu =3D <&cpu5>; - }; - - core2 { - cpu =3D <&cpu6>; - }; - - core3 { - cpu =3D <&cpu7>; - }; - }; - }; - - cpu0: cpu@0 { - compatible =3D "arm,cortex-a72"; - reg =3D <0x000>; - device_type =3D "cpu"; - enable-method =3D "psci"; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&L2_0>; - }; - - cpu1: cpu@1 { - compatible =3D "arm,cortex-a72"; - reg =3D <0x001>; - device_type =3D "cpu"; - enable-method =3D "psci"; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&L2_0>; - }; - - cpu2: cpu@2 { - compatible =3D "arm,cortex-a72"; - reg =3D <0x002>; - device_type =3D "cpu"; - enable-method =3D "psci"; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&L2_0>; - }; - - cpu3: cpu@3 { - compatible =3D "arm,cortex-a72"; - reg =3D <0x003>; - device_type =3D "cpu"; - enable-method =3D "psci"; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&L2_0>; - }; - - cpu4: cpu@100 { - compatible =3D "arm,cortex-a72"; - reg =3D <0x100>; - device_type =3D "cpu"; - enable-method =3D "psci"; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&L2_1>; - }; - - cpu5: cpu@101 { - compatible =3D "arm,cortex-a72"; - reg =3D <0x101>; - device_type =3D "cpu"; - enable-method =3D "psci"; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&L2_1>; - }; - - cpu6: cpu@102 { - compatible =3D "arm,cortex-a72"; - reg =3D <0x102>; - device_type =3D "cpu"; - enable-method =3D "psci"; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&L2_1>; - }; - - cpu7: cpu@103 { - compatible =3D "arm,cortex-a72"; - reg =3D <0x103>; - device_type =3D "cpu"; - enable-method =3D "psci"; - i-cache-size =3D <0xc000>; - i-cache-line-size =3D <64>; - i-cache-sets =3D <256>; - d-cache-size =3D <0x8000>; - d-cache-line-size =3D <64>; - d-cache-sets =3D <256>; - next-level-cache =3D <&L2_1>; - }; - }; - L2_0: l2-cache0 { compatible =3D "cache"; cache-level =3D <2>; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti= /k3-j784s4.dtsi index 46cff5ed3730..16ade4fd9cbd 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi @@ -10,3 +10,161 @@ =20 #include "k3-j784s4-j742s2-common.dtsi" =20 +/ { + model =3D "Texas Instruments K3 J784S4 SoC"; + compatible =3D "ti,j784s4"; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + cpu-map { + cluster0: cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + }; + + cluster1: cluster1 { + core0 { + cpu =3D <&cpu4>; + }; + + core1 { + cpu =3D <&cpu5>; + }; + + core2 { + cpu =3D <&cpu6>; + }; + + core3 { + cpu =3D <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x000>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; + }; + + cpu1: cpu@1 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x001>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; + }; + + cpu2: cpu@2 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x002>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; + }; + + cpu3: cpu@3 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x003>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; + }; + + cpu4: cpu@100 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x100>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_1>; + }; + + cpu5: cpu@101 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x101>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_1>; + }; + + cpu6: cpu@102 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x102>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_1>; + }; + + cpu7: cpu@103 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x103>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_1>; + }; + }; +}; --=20 2.45.1 From nobody Sun Feb 8 17:46:43 2026 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B1E51BE24B; Wed, 31 Jul 2024 17:10:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722445858; cv=none; b=JOuFfstYPW5OWOAkHd7kbPdkhOfUizIsICazLI9qeUTTP84Rtil48MmYM7u3netd4koB1HqNnx0StD559DjKwgNMN09hjWVG7kHWwhzXShDEm1A+iwHRpWnXIuKtoW6DIwJgfCx8maL8ClCjXJCTICEtwoPt8AIDvhv1pNspS88= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722445858; c=relaxed/simple; bh=PxrG8bZxhw5fS8NLV0uCqWQHJe+edChWzsafCHdHp30=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=QnuFcwi2XfgrxPXl5m9JkUSXPb6NlNlqoFiaulmOU5IsvFg6TFq4GaSyQIiNv2dYLsOVDSAxyU/HN/1At5CcNpgfu3KfcfbvKiJmsjfvEGcGOUIiqUmFmMAprpdUo/HbaVSlIYbFPw4xyLbhgNBxce+A62o7g1CqKpNgLbN78ak= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=I1OksOch; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="I1OksOch" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 46VHAoXc090454; Wed, 31 Jul 2024 12:10:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1722445851; bh=VVhDA/DT3hGQQoCDjSRbk4R2xYQLd5qL46zIyAsBaqo=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=I1OksOchEQLcN8K5SyNF+NktJnt5+sBk+k6lO/cPi1Czt+5hfvTHN86EoC7tiYhgd KQjRl5fhGTBWd7VKlmFhA5ttMHX8Lf1n6dF0ht48jYMs6K4JG/+mAgXHTzcPzzG/Uh e0u3S4IfUiQsqai91iHtpF6+TdXWqxnAqzDPHmO0= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 46VHAoPf108877 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 31 Jul 2024 12:10:50 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 31 Jul 2024 12:10:50 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 31 Jul 2024 12:10:50 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 46VHAVgR036362; Wed, 31 Jul 2024 12:10:47 -0500 From: Manorit Chawdhry Date: Wed, 31 Jul 2024 22:40:30 +0530 Subject: [PATCH v3 4/9] arm64: dts: ti: Split k3-j784s4-j742s2-main-common.dtsi Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240731-b4-upstream-j742s2-v3-4-da7fe3aa9e90@ti.com> References: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> In-Reply-To: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Udit Kumar , Neha Malcom Francis , Aniket Limaye , Manorit Chawdhry X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1722445831; l=2512; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=PxrG8bZxhw5fS8NLV0uCqWQHJe+edChWzsafCHdHp30=; b=8Ny2Sufd49QCrbrTXLkPx6pOhFFJ/g8ZhyklB/Q8yVOnOjqUu/jTBBcuqBYOrZcFCWFYJl5cR LUcuFBm/g5KASfRk5nDw6nZ/26q9ssXUhpQe2kVDGgMEkU+SR6QbxiU X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 k3-j784s4-j742s2-main-common.dtsi will be included in k3-j742s2-main.dtsi a= t a later point so move j784s4 related stuff to k3-j784s4-main.dtsi Signed-off-by: Manorit Chawdhry --- .../boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 13 ------------- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 21 +++++++++++++++++= ++++ arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 2 ++ 3 files changed, 23 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arc= h/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index 17abd0f1560a..91352b1f63d2 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -2405,19 +2405,6 @@ c71_2: dsp@66800000 { status =3D "disabled"; }; =20 - c71_3: dsp@67800000 { - compatible =3D "ti,j721s2-c71-dsp"; - reg =3D <0x00 0x67800000 0x00 0x00080000>, - <0x00 0x67e00000 0x00 0x0000c000>; - reg-names =3D "l2sram", "l1dram"; - ti,sci =3D <&sms>; - ti,sci-dev-id =3D <40>; - ti,sci-proc-ids =3D <0x33 0xff>; - resets =3D <&k3_reset 40 1>; - firmware-name =3D "j784s4-c71_3-fw"; - status =3D "disabled"; - }; - main_esm: esm@700000 { compatible =3D "ti,j721e-esm"; reg =3D <0x00 0x700000 0x00 0x1000>; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi new file mode 100644 index 000000000000..2ea470d1206d --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree Source for J784S4 SoC Family Main Domain peripherals + * + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +&cbass_main { + c71_3: dsp@67800000 { + compatible =3D "ti,j721s2-c71-dsp"; + reg =3D <0x00 0x67800000 0x00 0x00080000>, + <0x00 0x67e00000 0x00 0x0000c000>; + reg-names =3D "l2sram", "l1dram"; + ti,sci =3D <&sms>; + ti,sci-dev-id =3D <40>; + ti,sci-proc-ids =3D <0x33 0xff>; + resets =3D <&k3_reset 40 1>; + firmware-name =3D "j784s4-c71_3-fw"; + status =3D "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti= /k3-j784s4.dtsi index 16ade4fd9cbd..f5afa32157cb 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi @@ -168,3 +168,5 @@ cpu7: cpu@103 { }; }; }; + +#include "k3-j784s4-main.dtsi" --=20 2.45.1 From nobody Sun Feb 8 17:46:43 2026 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F00641BF30B; Wed, 31 Jul 2024 17:11:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722445871; cv=none; b=pEMLWIilcO7h3ZPM0CzO6+lmRdrRa5qycwDpg49gCMmqrTXOgQ8RYqiQvRtkIXtcgqkU5Ix7sy0Inl1E+M4sT/azrAr/cfoXiNl/WZMJ8oQcrBTX68E+oTbjCcQq/q2hrPqSs2vMp1nsVU0GAkhz7n+yyv3mn3aFPc1rwupo1yw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722445871; c=relaxed/simple; bh=/cZKhFc/8QIDv/QQ5OBWgY0k+XOP7Ojr7ldGR5OeVFo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=GMT4fFxgovfoWfdGg5NYzbJl8BuF9T2IctwN1SLUPJKe2flksOvuwNzJy24tnmsDxeyuBzBC04GbUIKCbDt5V/6SICRA9q4DnKvRohLAf6XjGVBKx7k9WrpCqZBPYa8D2sMUAEslnnvj9s1UnqgZtJxPqsUIh+6b/LhGDfCApe4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=eUPuMPpU; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="eUPuMPpU" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 46VHAs9h117315; Wed, 31 Jul 2024 12:10:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1722445854; bh=BIlnQn5XpzW1F2pdDBig/9KzLK0pGu4kWxjLX7yxamw=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=eUPuMPpUNhQDNa6rtxGk2SlkI0eVR06mcI6Odkb1hFRH+1GdG0HyQftCFboiyt4b3 NaH8TOG+QNKo9lO3KndY6kMSF9SGALwXa5JDzlBpPsXOcKWNkuLJpx+WFeQL3pwW6c z4CYjXLU6bXV7NVfK2EGw79NSmHEkbDZI5L8np0I= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 46VHAs7l108969 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 31 Jul 2024 12:10:54 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 31 Jul 2024 12:10:54 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 31 Jul 2024 12:10:54 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 46VHAVgS036362; Wed, 31 Jul 2024 12:10:51 -0500 From: Manorit Chawdhry Date: Wed, 31 Jul 2024 22:40:31 +0530 Subject: [PATCH v3 5/9] arm64: dts: ti: Move k3-j784s4-evm.dts to k3-j784s4-j742s2-evm-common.dtsi Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240731-b4-upstream-j742s2-v3-5-da7fe3aa9e90@ti.com> References: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> In-Reply-To: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Udit Kumar , Neha Malcom Francis , Aniket Limaye , Manorit Chawdhry X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1722445831; l=78544; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=/cZKhFc/8QIDv/QQ5OBWgY0k+XOP7Ojr7ldGR5OeVFo=; b=IMZY9OC/3k9HZJUqUh83hJSfUgpSY7VgfJVCLoo6/MSbbDFtqz3jJ+kWFL2zvGaYzzGftni4C iQp+6LOJ+vbAE3VKRB/6S/qsBVFyFqbrT3lP9Hx5krZYySVXyiBcQg6 X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 This is to introduce j742s2 support later, things from here will be moved to appropriate location. File k3-j784s4-evm.dts is not exactly removed as the name of DTS files shouldn't change mid refactor commits. Hence to keep the compatibility, after moving; k3-j784s4-evm.dts is including k3-j784s4-j742s2-evm-common.dtsi Signed-off-by: Manorit Chawdhry --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 1471 +---------------= --- .../boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 1477 ++++++++++++++++= ++++ 2 files changed, 1478 insertions(+), 1470 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts= /ti/k3-j784s4-evm.dts index ffa38f41679d..e3730b2bca92 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -5,1473 +5,4 @@ * EVM Board Schematics: https://www.ti.com/lit/zip/sprr458 */ =20 -/dts-v1/; - -#include -#include -#include "k3-j784s4.dtsi" - -/ { - compatible =3D "ti,j784s4-evm", "ti,j784s4"; - model =3D "Texas Instruments J784S4 EVM"; - - chosen { - stdout-path =3D "serial2:115200n8"; - }; - - aliases { - serial0 =3D &wkup_uart0; - serial1 =3D &mcu_uart0; - serial2 =3D &main_uart8; - mmc0 =3D &main_sdhci0; - mmc1 =3D &main_sdhci1; - i2c0 =3D &wkup_i2c0; - i2c3 =3D &main_i2c0; - ethernet0 =3D &mcu_cpsw_port1; - ethernet1 =3D &main_cpsw1_port1; - }; - - memory@80000000 { - device_type =3D "memory"; - bootph-all; - /* 32G RAM */ - reg =3D <0x00000000 0x80000000 0x00000000 0x80000000>, - <0x00000008 0x80000000 0x00000007 0x80000000>; - }; - - reserved_memory: reserved-memory { - #address-cells =3D <2>; - #size-cells =3D <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg =3D <0x00 0x9e800000 0x00 0x01800000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa0000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa0100000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - main_r5fss2_core0_memory_region: r5f-memory@a6100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - main_r5fss2_core1_memory_region: r5f-memory@a7100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a8000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa8000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a8100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa8100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: c71-dma-memory@a9000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa9000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: c71-memory@a9100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa9100000 0x00 0xf00000>; - no-map; - }; - - c71_2_dma_memory_region: c71-dma-memory@aa000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xaa000000 0x00 0x100000>; - no-map; - }; - - c71_2_memory_region: c71-memory@aa100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xaa100000 0x00 0xf00000>; - no-map; - }; - - c71_3_dma_memory_region: c71-dma-memory@ab000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xab000000 0x00 0x100000>; - no-map; - }; - - c71_3_memory_region: c71-memory@ab100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xab100000 0x00 0xf00000>; - no-map; - }; - }; - - evm_12v0: regulator-evm12v0 { - /* main supply */ - compatible =3D "regulator-fixed"; - regulator-name =3D "evm_12v0"; - regulator-min-microvolt =3D <12000000>; - regulator-max-microvolt =3D <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: regulator-vsys3v3 { - /* Output of LM5140 */ - compatible =3D "regulator-fixed"; - regulator-name =3D "vsys_3v3"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - vin-supply =3D <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_5v0: regulator-vsys5v0 { - /* Output of LM5140 */ - compatible =3D "regulator-fixed"; - regulator-name =3D "vsys_5v0"; - regulator-min-microvolt =3D <5000000>; - regulator-max-microvolt =3D <5000000>; - vin-supply =3D <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: regulator-sd { - /* Output of TPS22918 */ - compatible =3D "regulator-fixed"; - regulator-name =3D "vdd_mmc1"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply =3D <&vsys_3v3>; - gpio =3D <&exp2 2 GPIO_ACTIVE_HIGH>; - }; - - vdd_sd_dv: regulator-TLV71033 { - /* Output of TLV71033 */ - compatible =3D "regulator-gpio"; - regulator-name =3D "tlv71033"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&vdd_sd_dv_pins_default>; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <3300000>; - regulator-boot-on; - vin-supply =3D <&vsys_5v0>; - gpios =3D <&main_gpio0 8 GPIO_ACTIVE_HIGH>; - states =3D <1800000 0x0>, - <3300000 0x1>; - }; - - dp0_pwr_3v3: regulator-dp0-prw { - compatible =3D "regulator-fixed"; - regulator-name =3D "dp0-pwr"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - gpio =3D <&exp4 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - dp0: connector-dp0 { - compatible =3D "dp-connector"; - label =3D "DP0"; - type =3D "full-size"; - dp-pwr-supply =3D <&dp0_pwr_3v3>; - - port { - dp0_connector_in: endpoint { - remote-endpoint =3D <&dp0_out>; - }; - }; - }; - - transceiver0: can-phy0 { - compatible =3D "ti,tcan1042"; - #phy-cells =3D <0>; - max-bitrate =3D <5000000>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mcu_mcan0_gpio_pins_default>; - standby-gpios =3D <&wkup_gpio0 69 GPIO_ACTIVE_HIGH>; - }; - - transceiver1: can-phy1 { - compatible =3D "ti,tcan1042"; - #phy-cells =3D <0>; - max-bitrate =3D <5000000>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mcu_mcan1_gpio_pins_default>; - standby-gpios =3D <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; - }; - - transceiver2: can-phy2 { - /* standby pin has been grounded by default */ - compatible =3D "ti,tcan1042"; - #phy-cells =3D <0>; - max-bitrate =3D <5000000>; - }; - - transceiver3: can-phy3 { - compatible =3D "ti,tcan1042"; - #phy-cells =3D <0>; - max-bitrate =3D <5000000>; - standby-gpios =3D <&exp2 7 GPIO_ACTIVE_HIGH>; - mux-states =3D <&mux1 1>; - }; - - mux1: mux-controller { - compatible =3D "gpio-mux"; - #mux-state-cells =3D <1>; - mux-gpios =3D <&exp2 14 GPIO_ACTIVE_HIGH>; - idle-state =3D <1>; - }; - - codec_audio: sound { - compatible =3D "ti,j7200-cpb-audio"; - model =3D "j784s4-cpb"; - - ti,cpb-mcasp =3D <&mcasp0>; - ti,cpb-codec =3D <&pcm3168a_1>; - - clocks =3D <&k3_clks 265 0>, <&k3_clks 265 1>, - <&k3_clks 157 34>, <&k3_clks 157 63>; - clock-names =3D "cpb-mcasp-auxclk", "cpb-mcasp-auxclk-48000", - "cpb-codec-scki", "cpb-codec-scki-48000"; - }; -}; - -&wkup_gpio0 { - status =3D "okay"; -}; - -&main_pmx0 { - bootph-all; - main_cpsw2g_default_pins: main-cpsw2g-default-pins { - pinctrl-single,pins =3D < - J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */ - J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */ - J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */ - J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */ - J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */ - J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL = */ - J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */ - J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */ - J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */ - J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */ - J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */ - J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL = */ - >; - }; - - main_cpsw2g_mdio_default_pins: main-cpsw2g-mdio-default-pins { - pinctrl-single,pins =3D < - J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */ - J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */ - >; - }; - - main_uart8_pins_default: main-uart8-default-pins { - bootph-all; - pinctrl-single,pins =3D < - J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ - J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ - J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ - J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ - >; - }; - - main_i2c0_pins_default: main-i2c0-default-pins { - pinctrl-single,pins =3D < - J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ - J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ - >; - }; - - main_i2c5_pins_default: main-i2c5-default-pins { - pinctrl-single,pins =3D < - J784S4_IOPAD(0x01c, PIN_INPUT, 8) /* (AG34) MCAN15_TX.I2C5_SCL */ - J784S4_IOPAD(0x018, PIN_INPUT, 8) /* (AK36) MCAN14_RX.I2C5_SDA */ - >; - }; - - main_mmc1_pins_default: main-mmc1-default-pins { - bootph-all; - pinctrl-single,pins =3D < - J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ - J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ - J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */ - J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ - J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ - J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ - J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ - J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */ - >; - }; - - vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { - pinctrl-single,pins =3D < - J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ - >; - }; - - dp0_pins_default: dp0-default-pins { - pinctrl-single,pins =3D < - J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */ - >; - }; - - main_i2c4_pins_default: main-i2c4-default-pins { - pinctrl-single,pins =3D < - J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */ - J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */ - >; - }; - - main_mcan4_pins_default: main-mcan4-default-pins { - pinctrl-single,pins =3D < - J784S4_IOPAD(0x088, PIN_INPUT, 0) /* (AF36) MCAN4_RX */ - J784S4_IOPAD(0x084, PIN_OUTPUT, 0) /* (AG38) MCAN4_TX */ - >; - }; - - main_mcan16_pins_default: main-mcan16-default-pins { - pinctrl-single,pins =3D < - J784S4_IOPAD(0x028, PIN_INPUT, 0) /* (AE33) MCAN16_RX */ - J784S4_IOPAD(0x024, PIN_OUTPUT, 0) /* (AH34) MCAN16_TX */ - >; - }; - - main_usbss0_pins_default: main-usbss0-default-pins { - bootph-all; - pinctrl-single,pins =3D < - J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */ - >; - }; - - main_i2c3_pins_default: main-i2c3-default-pins { - pinctrl-single,pins =3D < - J784S4_IOPAD(0x064, PIN_INPUT, 13) /* (AF38) MCAN0_TX.I2C3_SCL */ - J784S4_IOPAD(0x060, PIN_INPUT, 13) /* (AE36) MCASP2_AXR1.I2C3_SDA */ - >; - }; - - main_mcasp0_pins_default: main-mcasp0-default-pins { - pinctrl-single,pins =3D < - J784S4_IOPAD(0x038, PIN_OUTPUT_PULLDOWN, 1) /* (AK35) MCASP0_ACLKX */ - J784S4_IOPAD(0x03c, PIN_OUTPUT_PULLDOWN, 1) /* (AK38) MCASP0_AFSX */ - J784S4_IOPAD(0x07c, PIN_OUTPUT_PULLDOWN, 1) /* (AJ38) MCASP0_AXR3 */ - J784S4_IOPAD(0x080, PIN_INPUT_PULLDOWN, 1) /* (AK34) MCASP0_AXR4 */ - >; - }; - - audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins { - pinctrl-single,pins =3D < - J784S4_IOPAD(0x078, PIN_OUTPUT, 1) /* (AH37) MCAN2_RX.AUDIO_EXT_REFCLK1= */ - >; - }; -}; - -&wkup_pmx2 { - bootph-all; - wkup_uart0_pins_default: wkup-uart0-default-pins { - bootph-all; - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ - J784S4_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */ - >; - }; - - wkup_i2c0_pins_default: wkup-i2c0-default-pins { - bootph-all; - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ - J784S4_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ - >; - }; - - mcu_uart0_pins_default: mcu-uart0-default-pins { - bootph-all; - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0= _CTSn */ - J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART= 0_RTSn */ - J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0= _RXD */ - J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART= 0_TXD */ - >; - }; - - mcu_cpsw_pins_default: mcu-cpsw-default-pins { - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ - J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ - J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ - J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ - J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ - J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ - J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ - J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ - J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ - J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ - J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ - J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ - >; - }; - - mcu_mdio_pins_default: mcu-mdio-default-pins { - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ - J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ - >; - }; - - mcu_adc0_pins_default: mcu-adc0-default-pins { - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ - J784S4_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ - J784S4_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ - J784S4_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ - J784S4_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ - J784S4_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ - J784S4_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ - J784S4_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ - >; - }; - - mcu_adc1_pins_default: mcu-adc1-default-pins { - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ - J784S4_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ - J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ - J784S4_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ - J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ - J784S4_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ - J784S4_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ - J784S4_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ - >; - }; - - mcu_mcan0_pins_default: mcu-mcan0-default-pins { - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */ - J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */ - >; - }; - - mcu_mcan1_pins_default: mcu-mcan1-default-pins { - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (H35) WKUP_GPIO0_4.MCU_MCAN1= _TX */ - J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_= RX */ - >; - }; - - mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (J38) MCU_SPI0_D1.WKUP_GPIO0_= 69 */ - >; - }; - - mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */ - >; - }; -}; - -&wkup_pmx1 { - status =3D "okay"; - - pmic_irq_pins_default: pmic-irq-default-pins { - pinctrl-single,pins =3D < - /* (G33) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ - J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) - >; - }; -}; - -&wkup_pmx0 { - bootph-all; - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { - bootph-all; - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ - J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ - J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ - J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ - J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ - J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ - J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ - J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ - J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ - J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ - J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ - >; - }; -}; - -&wkup_pmx1 { - bootph-all; - mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { - bootph-all; - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */ - J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ - >; - }; - - mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { - bootph-all; - pinctrl-single,pins =3D < - J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ - J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ - J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ - J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ - J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ - J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ - J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ - J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ - >; - }; -}; - -&wkup_uart0 { - /* Firmware usage */ - status =3D "reserved"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&wkup_uart0_pins_default>; -}; - -&wkup_i2c0 { - bootph-all; - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&wkup_i2c0_pins_default>; - clock-frequency =3D <400000>; - - eeprom@50 { - /* CAV24C256WE-GT3 */ - compatible =3D "atmel,24c256"; - reg =3D <0x50>; - }; - - tps659413: pmic@48 { - compatible =3D "ti,tps6594-q1"; - reg =3D <0x48>; - system-power-controller; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pmic_irq_pins_default>; - interrupt-parent =3D <&wkup_gpio0>; - interrupts =3D <39 IRQ_TYPE_EDGE_FALLING>; - gpio-controller; - #gpio-cells =3D <2>; - ti,primary-pmic; - buck12-supply =3D <&vsys_3v3>; - buck3-supply =3D <&vsys_3v3>; - buck4-supply =3D <&vsys_3v3>; - buck5-supply =3D <&vsys_3v3>; - ldo1-supply =3D <&vsys_3v3>; - ldo2-supply =3D <&vsys_3v3>; - ldo3-supply =3D <&vsys_3v3>; - ldo4-supply =3D <&vsys_3v3>; - - regulators { - bucka12: buck12 { - regulator-name =3D "vdd_ddr_1v1"; - regulator-min-microvolt =3D <1100000>; - regulator-max-microvolt =3D <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - bucka3: buck3 { - regulator-name =3D "vdd_ram_0v85"; - regulator-min-microvolt =3D <850000>; - regulator-max-microvolt =3D <850000>; - regulator-boot-on; - regulator-always-on; - }; - - bucka4: buck4 { - regulator-name =3D "vdd_io_1v8"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - bucka5: buck5 { - regulator-name =3D "vdd_mcu_0v85"; - regulator-min-microvolt =3D <850000>; - regulator-max-microvolt =3D <850000>; - regulator-boot-on; - regulator-always-on; - }; - - ldoa1: ldo1 { - regulator-name =3D "vdd_mcuio_1v8"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldoa2: ldo2 { - regulator-name =3D "vdd_mcuio_3v3"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldoa3: ldo3 { - regulator-name =3D "vds_dll_0v8"; - regulator-min-microvolt =3D <800000>; - regulator-max-microvolt =3D <800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldoa4: ldo4 { - regulator-name =3D "vda_mcu_1v8"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - tps62873a: regulator@40 { - compatible =3D "ti,tps62873"; - reg =3D <0x40>; - bootph-pre-ram; - regulator-name =3D "VDD_CPU_AVS"; - regulator-min-microvolt =3D <750000>; - regulator-max-microvolt =3D <1330000>; - regulator-boot-on; - regulator-always-on; - }; - - tps62873b: regulator@43 { - compatible =3D "ti,tps62873"; - reg =3D <0x43>; - regulator-name =3D "VDD_CORE_0V8"; - regulator-min-microvolt =3D <760000>; - regulator-max-microvolt =3D <840000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&mcu_uart0 { - bootph-all; - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mcu_uart0_pins_default>; -}; - -&main_uart8 { - bootph-all; - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&main_uart8_pins_default>; -}; - -&ufs_wrapper { - status =3D "okay"; -}; - -&fss { - bootph-all; - status =3D "okay"; -}; - -&ospi0 { - bootph-all; - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_def= ault>; - - flash@0 { - bootph-all; - compatible =3D "jedec,spi-nor"; - reg =3D <0x0>; - spi-tx-bus-width =3D <8>; - spi-rx-bus-width =3D <8>; - spi-max-frequency =3D <25000000>; - cdns,tshsl-ns =3D <60>; - cdns,tsd2d-ns =3D <60>; - cdns,tchsh-ns =3D <60>; - cdns,tslch-ns =3D <60>; - cdns,read-delay =3D <4>; - - partitions { - compatible =3D "fixed-partitions"; - #address-cells =3D <1>; - #size-cells =3D <1>; - - partition@0 { - label =3D "ospi.tiboot3"; - reg =3D <0x0 0x80000>; - }; - - partition@80000 { - label =3D "ospi.tispl"; - reg =3D <0x80000 0x200000>; - }; - - partition@280000 { - label =3D "ospi.u-boot"; - reg =3D <0x280000 0x400000>; - }; - - partition@680000 { - label =3D "ospi.env"; - reg =3D <0x680000 0x40000>; - }; - - partition@6c0000 { - label =3D "ospi.env.backup"; - reg =3D <0x6c0000 0x40000>; - }; - - partition@800000 { - label =3D "ospi.rootfs"; - reg =3D <0x800000 0x37c0000>; - }; - - partition@3fc0000 { - bootph-all; - label =3D "ospi.phypattern"; - reg =3D <0x3fc0000 0x40000>; - }; - }; - }; -}; - -&ospi1 { - bootph-all; - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mcu_fss0_ospi1_pins_default>; - - flash@0 { - bootph-all; - compatible =3D "jedec,spi-nor"; - reg =3D <0x0>; - spi-tx-bus-width =3D <1>; - spi-rx-bus-width =3D <4>; - spi-max-frequency =3D <40000000>; - cdns,tshsl-ns =3D <60>; - cdns,tsd2d-ns =3D <60>; - cdns,tchsh-ns =3D <60>; - cdns,tslch-ns =3D <60>; - cdns,read-delay =3D <2>; - - partitions { - compatible =3D "fixed-partitions"; - #address-cells =3D <1>; - #size-cells =3D <1>; - - partition@0 { - label =3D "qspi.tiboot3"; - reg =3D <0x0 0x80000>; - }; - - partition@80000 { - label =3D "qspi.tispl"; - reg =3D <0x80000 0x200000>; - }; - - partition@280000 { - label =3D "qspi.u-boot"; - reg =3D <0x280000 0x400000>; - }; - - partition@680000 { - label =3D "qspi.env"; - reg =3D <0x680000 0x40000>; - }; - - partition@6c0000 { - label =3D "qspi.env.backup"; - reg =3D <0x6c0000 0x40000>; - }; - - partition@800000 { - label =3D "qspi.rootfs"; - reg =3D <0x800000 0x37c0000>; - }; - - partition@3fc0000 { - bootph-all; - label =3D "qspi.phypattern"; - reg =3D <0x3fc0000 0x40000>; - }; - }; - - }; -}; - -&main_i2c0 { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&main_i2c0_pins_default>; - - clock-frequency =3D <400000>; - - exp1: gpio@20 { - compatible =3D "ti,tca6416"; - reg =3D <0x20>; - gpio-controller; - #gpio-cells =3D <2>; - gpio-line-names =3D "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC= _RSTZ", - "PCIE1_2L_EP_RST_EN", "PCIE0_4L_MODE_SEL", "PCIE0_4L_PERSTZ", - "PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#", - "PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", - "AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ"; - - p12-hog { - /* P12 - AUDIO_MUX_SEL */ - gpio-hog; - gpios =3D <12 GPIO_ACTIVE_HIGH>; - output-low; - line-name =3D "AUDIO_MUX_SEL"; - }; - }; - - exp2: gpio@22 { - compatible =3D "ti,tca6424"; - reg =3D <0x22>; - gpio-controller; - #gpio-cells =3D <2>; - gpio-line-names =3D "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_P= WR_EN", - "USBC_PWR_EN", "USBC_MODE_SEL1", "USBC_MODE_SEL0", - "GPIO_LIN_EN", "R_CAN_STB", "CTRL_PM_I2C_OE#", - "ENET2_EXP_PWRDN", "ENET2_EXP_SPARE2", "CDCI2_RSTZ", - "USB2.0_MUX_SEL", "CANUART_MUX_SEL0", "CANUART_MUX2_SEL1", - "CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ", - "ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ", - "USER_INPUT1", "USER_LED1", "USER_LED2"; - - p13-hog { - /* P13 - CANUART_MUX_SEL0 */ - gpio-hog; - gpios =3D <13 GPIO_ACTIVE_HIGH>; - output-high; - line-name =3D "CANUART_MUX_SEL0"; - }; - - p15-hog { - /* P15 - CANUART_MUX1_SEL1 */ - gpio-hog; - gpios =3D <15 GPIO_ACTIVE_HIGH>; - output-high; - line-name =3D "CANUART_MUX1_SEL1"; - }; - }; -}; - -&main_i2c5 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&main_i2c5_pins_default>; - clock-frequency =3D <400000>; - status =3D "okay"; - - exp5: gpio@20 { - compatible =3D "ti,tca6408"; - reg =3D <0x20>; - gpio-controller; - #gpio-cells =3D <2>; - gpio-line-names =3D "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", - "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO3", - "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", - "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; - }; -}; - -&main_sdhci0 { - bootph-all; - /* eMMC */ - status =3D "okay"; - non-removable; - ti,driver-strength-ohm =3D <50>; - disable-wp; -}; - -&main_sdhci1 { - bootph-all; - /* SD card */ - status =3D "okay"; - pinctrl-0 =3D <&main_mmc1_pins_default>; - pinctrl-names =3D "default"; - disable-wp; - vmmc-supply =3D <&vdd_mmc1>; - vqmmc-supply =3D <&vdd_sd_dv>; -}; - -&main_gpio0 { - status =3D "okay"; -}; - -&mcu_cpsw { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mcu_cpsw_pins_default>; -}; - -&davinci_mdio { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mcu_mdio_pins_default>; - - mcu_phy0: ethernet-phy@0 { - reg =3D <0>; - ti,rx-internal-delay =3D ; - ti,fifo-depth =3D ; - ti,min-output-impedance; - }; -}; - -&mcu_cpsw_port1 { - status =3D "okay"; - phy-mode =3D "rgmii-rxid"; - phy-handle =3D <&mcu_phy0>; -}; - -&main_cpsw1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&main_cpsw2g_default_pins>; - status =3D "okay"; -}; - -&main_cpsw1_mdio { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&main_cpsw2g_mdio_default_pins>; - status =3D "okay"; - - main_cpsw1_phy0: ethernet-phy@0 { - reg =3D <0>; - ti,rx-internal-delay =3D ; - ti,fifo-depth =3D ; - ti,min-output-impedance; - }; -}; - -&main_cpsw1_port1 { - phy-mode =3D "rgmii-rxid"; - phy-handle =3D <&main_cpsw1_phy0>; - status =3D "okay"; -}; - -&mailbox0_cluster0 { - status =3D "okay"; - interrupts =3D <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status =3D "okay"; - interrupts =3D <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status =3D "okay"; - interrupts =3D <428>; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - status =3D "okay"; - interrupts =3D <424>; - - mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status =3D "okay"; - interrupts =3D <420>; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster5 { - status =3D "okay"; - interrupts =3D <416>; - - mbox_c71_2: mbox-c71-2 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_c71_3: mbox-c71-3 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mcu_r5fss0_core0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0_core0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region =3D <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region =3D <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region =3D <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region =3D <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&main_r5fss2_core0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; - memory-region =3D <&main_r5fss2_core0_dma_memory_region>, - <&main_r5fss2_core0_memory_region>; -}; - -&main_r5fss2_core1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; - memory-region =3D <&main_r5fss2_core1_dma_memory_region>, - <&main_r5fss2_core1_memory_region>; -}; - -&c71_0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster4 &mbox_c71_0>; - memory-region =3D <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; - -&c71_1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster4 &mbox_c71_1>; - memory-region =3D <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; -}; - -&c71_2 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster5 &mbox_c71_2>; - memory-region =3D <&c71_2_dma_memory_region>, - <&c71_2_memory_region>; -}; - -&c71_3 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster5 &mbox_c71_3>; - memory-region =3D <&c71_3_dma_memory_region>, - <&c71_3_memory_region>; -}; - -&tscadc0 { - pinctrl-0 =3D <&mcu_adc0_pins_default>; - pinctrl-names =3D "default"; - status =3D "okay"; - adc { - ti,adc-channels =3D <0 1 2 3 4 5 6 7>; - }; -}; - -&tscadc1 { - pinctrl-0 =3D <&mcu_adc1_pins_default>; - pinctrl-names =3D "default"; - status =3D "okay"; - adc { - ti,adc-channels =3D <0 1 2 3 4 5 6 7>; - }; -}; - -&serdes_refclk { - status =3D "okay"; - clock-frequency =3D <100000000>; -}; - -&dss { - status =3D "okay"; - assigned-clocks =3D <&k3_clks 218 2>, - <&k3_clks 218 5>, - <&k3_clks 218 14>, - <&k3_clks 218 18>; - assigned-clock-parents =3D <&k3_clks 218 3>, - <&k3_clks 218 7>, - <&k3_clks 218 16>, - <&k3_clks 218 22>; -}; - -&serdes0 { - status =3D "okay"; - - serdes0_pcie1_link: phy@0 { - reg =3D <0>; - cdns,num-lanes =3D <2>; - #phy-cells =3D <0>; - cdns,phy-type =3D ; - resets =3D <&serdes_wiz0 1>, <&serdes_wiz0 2>; - }; - - serdes0_usb_link: phy@3 { - reg =3D <3>; - cdns,num-lanes =3D <1>; - #phy-cells =3D <0>; - cdns,phy-type =3D ; - resets =3D <&serdes_wiz0 4>; - }; -}; - -&serdes_wiz0 { - status =3D "okay"; -}; - -&usb_serdes_mux { - idle-states =3D <0>; /* USB0 to SERDES lane 3 */ -}; - -&usbss0 { - status =3D "okay"; - pinctrl-0 =3D <&main_usbss0_pins_default>; - pinctrl-names =3D "default"; - ti,vbus-divider; -}; - -&usb0 { - dr_mode =3D "otg"; - maximum-speed =3D "super-speed"; - phys =3D <&serdes0_usb_link>; - phy-names =3D "cdns3,usb3-phy"; -}; - -&serdes_wiz4 { - status =3D "okay"; -}; - -&serdes4 { - status =3D "okay"; - serdes4_dp_link: phy@0 { - reg =3D <0>; - cdns,num-lanes =3D <4>; - #phy-cells =3D <0>; - cdns,phy-type =3D ; - resets =3D <&serdes_wiz4 1>, <&serdes_wiz4 2>, - <&serdes_wiz4 3>, <&serdes_wiz4 4>; - }; -}; - -&mhdp { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&dp0_pins_default>; - phys =3D <&serdes4_dp_link>; - phy-names =3D "dpphy"; -}; - -&dss_ports { - /* DP */ - port { - dpi0_out: endpoint { - remote-endpoint =3D <&dp0_in>; - }; - }; -}; - -&main_i2c4 { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&main_i2c4_pins_default>; - clock-frequency =3D <400000>; - - exp4: gpio@20 { - compatible =3D "ti,tca6408"; - reg =3D <0x20>; - gpio-controller; - #gpio-cells =3D <2>; - }; -}; - -&dp0_ports { - port@0 { - reg =3D <0>; - - dp0_in: endpoint { - remote-endpoint =3D <&dpi0_out>; - }; - }; - - port@4 { - reg =3D <4>; - - dp0_out: endpoint { - remote-endpoint =3D <&dp0_connector_in>; - }; - }; -}; - -&mcu_mcan0 { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mcu_mcan0_pins_default>; - phys =3D <&transceiver0>; -}; - -&mcu_mcan1 { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mcu_mcan1_pins_default>; - phys =3D <&transceiver1>; -}; - -&main_mcan16 { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&main_mcan16_pins_default>; - phys =3D <&transceiver2>; -}; - -&main_mcan4 { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&main_mcan4_pins_default>; - phys =3D <&transceiver3>; -}; - -&pcie1_rc { - status =3D "okay"; - num-lanes =3D <2>; - reset-gpios =3D <&exp1 2 GPIO_ACTIVE_HIGH>; - phys =3D <&serdes0_pcie1_link>; - phy-names =3D "pcie-phy"; -}; - -&serdes1 { - status =3D "okay"; - - serdes1_pcie0_link: phy@0 { - reg =3D <0>; - cdns,num-lanes =3D <2>; - #phy-cells =3D <0>; - cdns,phy-type =3D ; - resets =3D <&serdes_wiz1 1>, <&serdes_wiz1 2>; - }; -}; - -&serdes_wiz1 { - status =3D "okay"; -}; - -&pcie0_rc { - status =3D "okay"; - reset-gpios =3D <&exp1 6 GPIO_ACTIVE_HIGH>; - phys =3D <&serdes1_pcie0_link>; - phy-names =3D "pcie-phy"; -}; - -&k3_clks { - /* Confiure AUDIO_EXT_REFCLK1 pin as output */ - pinctrl-names =3D "default"; - pinctrl-0 =3D <&audio_ext_refclk1_pins_default>; -}; - -&main_i2c3 { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&main_i2c3_pins_default>; - clock-frequency =3D <400000>; - - exp3: gpio@20 { - compatible =3D "ti,tca6408"; - reg =3D <0x20>; - gpio-controller; - #gpio-cells =3D <2>; - }; - - pcm3168a_1: audio-codec@44 { - compatible =3D "ti,pcm3168a"; - reg =3D <0x44>; - #sound-dai-cells =3D <1>; - reset-gpios =3D <&exp3 0 GPIO_ACTIVE_LOW>; - clocks =3D <&audio_refclk1>; - clock-names =3D "scki"; - VDD1-supply =3D <&vsys_3v3>; - VDD2-supply =3D <&vsys_3v3>; - VCCAD1-supply =3D <&vsys_5v0>; - VCCAD2-supply =3D <&vsys_5v0>; - VCCDA1-supply =3D <&vsys_5v0>; - VCCDA2-supply =3D <&vsys_5v0>; - }; -}; - -&mcasp0 { - status =3D "okay"; - #sound-dai-cells =3D <0>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&main_mcasp0_pins_default>; - op-mode =3D <0>; /* MCASP_IIS_MODE */ - tdm-slots =3D <2>; - auxclk-fs-ratio =3D <256>; - serial-dir =3D < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 0 1 - 2 0 0 0 - 0 0 0 0 - 0 0 0 0 - >; -}; +#include "k3-j784s4-j742s2-evm-common.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch= /arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi new file mode 100644 index 000000000000..ffa38f41679d --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi @@ -0,0 +1,1477 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti= .com/ + * + * EVM Board Schematics: https://www.ti.com/lit/zip/sprr458 + */ + +/dts-v1/; + +#include +#include +#include "k3-j784s4.dtsi" + +/ { + compatible =3D "ti,j784s4-evm", "ti,j784s4"; + model =3D "Texas Instruments J784S4 EVM"; + + chosen { + stdout-path =3D "serial2:115200n8"; + }; + + aliases { + serial0 =3D &wkup_uart0; + serial1 =3D &mcu_uart0; + serial2 =3D &main_uart8; + mmc0 =3D &main_sdhci0; + mmc1 =3D &main_sdhci1; + i2c0 =3D &wkup_i2c0; + i2c3 =3D &main_i2c0; + ethernet0 =3D &mcu_cpsw_port1; + ethernet1 =3D &main_cpsw1_port1; + }; + + memory@80000000 { + device_type =3D "memory"; + bootph-all; + /* 32G RAM */ + reg =3D <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000007 0x80000000>; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg =3D <0x00 0x9e800000 0x00 0x01800000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + main_r5fss2_core0_memory_region: r5f-memory@a6100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + main_r5fss2_core1_memory_region: r5f-memory@a7100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: c71-dma-memory@a8000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa8000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a8100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa8100000 0x00 0xf00000>; + no-map; + }; + + c71_1_dma_memory_region: c71-dma-memory@a9000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa9000000 0x00 0x100000>; + no-map; + }; + + c71_1_memory_region: c71-memory@a9100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa9100000 0x00 0xf00000>; + no-map; + }; + + c71_2_dma_memory_region: c71-dma-memory@aa000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xaa000000 0x00 0x100000>; + no-map; + }; + + c71_2_memory_region: c71-memory@aa100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xaa100000 0x00 0xf00000>; + no-map; + }; + + c71_3_dma_memory_region: c71-dma-memory@ab000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xab000000 0x00 0x100000>; + no-map; + }; + + c71_3_memory_region: c71-memory@ab100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xab100000 0x00 0xf00000>; + no-map; + }; + }; + + evm_12v0: regulator-evm12v0 { + /* main supply */ + compatible =3D "regulator-fixed"; + regulator-name =3D "evm_12v0"; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_3v3: regulator-vsys3v3 { + /* Output of LM5140 */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vsys_3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_5v0: regulator-vsys5v0 { + /* Output of LM5140 */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vsys_5v0"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-sd { + /* Output of TPS22918 */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_mmc1"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply =3D <&vsys_3v3>; + gpio =3D <&exp2 2 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv: regulator-TLV71033 { + /* Output of TLV71033 */ + compatible =3D "regulator-gpio"; + regulator-name =3D "tlv71033"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vdd_sd_dv_pins_default>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + vin-supply =3D <&vsys_5v0>; + gpios =3D <&main_gpio0 8 GPIO_ACTIVE_HIGH>; + states =3D <1800000 0x0>, + <3300000 0x1>; + }; + + dp0_pwr_3v3: regulator-dp0-prw { + compatible =3D "regulator-fixed"; + regulator-name =3D "dp0-pwr"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&exp4 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + dp0: connector-dp0 { + compatible =3D "dp-connector"; + label =3D "DP0"; + type =3D "full-size"; + dp-pwr-supply =3D <&dp0_pwr_3v3>; + + port { + dp0_connector_in: endpoint { + remote-endpoint =3D <&dp0_out>; + }; + }; + }; + + transceiver0: can-phy0 { + compatible =3D "ti,tcan1042"; + #phy-cells =3D <0>; + max-bitrate =3D <5000000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_mcan0_gpio_pins_default>; + standby-gpios =3D <&wkup_gpio0 69 GPIO_ACTIVE_HIGH>; + }; + + transceiver1: can-phy1 { + compatible =3D "ti,tcan1042"; + #phy-cells =3D <0>; + max-bitrate =3D <5000000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_mcan1_gpio_pins_default>; + standby-gpios =3D <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; + }; + + transceiver2: can-phy2 { + /* standby pin has been grounded by default */ + compatible =3D "ti,tcan1042"; + #phy-cells =3D <0>; + max-bitrate =3D <5000000>; + }; + + transceiver3: can-phy3 { + compatible =3D "ti,tcan1042"; + #phy-cells =3D <0>; + max-bitrate =3D <5000000>; + standby-gpios =3D <&exp2 7 GPIO_ACTIVE_HIGH>; + mux-states =3D <&mux1 1>; + }; + + mux1: mux-controller { + compatible =3D "gpio-mux"; + #mux-state-cells =3D <1>; + mux-gpios =3D <&exp2 14 GPIO_ACTIVE_HIGH>; + idle-state =3D <1>; + }; + + codec_audio: sound { + compatible =3D "ti,j7200-cpb-audio"; + model =3D "j784s4-cpb"; + + ti,cpb-mcasp =3D <&mcasp0>; + ti,cpb-codec =3D <&pcm3168a_1>; + + clocks =3D <&k3_clks 265 0>, <&k3_clks 265 1>, + <&k3_clks 157 34>, <&k3_clks 157 63>; + clock-names =3D "cpb-mcasp-auxclk", "cpb-mcasp-auxclk-48000", + "cpb-codec-scki", "cpb-codec-scki-48000"; + }; +}; + +&wkup_gpio0 { + status =3D "okay"; +}; + +&main_pmx0 { + bootph-all; + main_cpsw2g_default_pins: main-cpsw2g-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */ + J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */ + J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */ + J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */ + J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */ + J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL = */ + J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */ + J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */ + J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */ + J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */ + J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */ + J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL = */ + >; + }; + + main_cpsw2g_mdio_default_pins: main-cpsw2g-mdio-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */ + J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */ + >; + }; + + main_uart8_pins_default: main-uart8-default-pins { + bootph-all; + pinctrl-single,pins =3D < + J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ + J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ + J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ + J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ + >; + }; + + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ + J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ + >; + }; + + main_i2c5_pins_default: main-i2c5-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x01c, PIN_INPUT, 8) /* (AG34) MCAN15_TX.I2C5_SCL */ + J784S4_IOPAD(0x018, PIN_INPUT, 8) /* (AK36) MCAN14_RX.I2C5_SDA */ + >; + }; + + main_mmc1_pins_default: main-mmc1-default-pins { + bootph-all; + pinctrl-single,pins =3D < + J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ + J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ + J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */ + J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ + J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ + J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ + J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ + J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */ + >; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ + >; + }; + + dp0_pins_default: dp0-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */ + >; + }; + + main_i2c4_pins_default: main-i2c4-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */ + J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */ + >; + }; + + main_mcan4_pins_default: main-mcan4-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x088, PIN_INPUT, 0) /* (AF36) MCAN4_RX */ + J784S4_IOPAD(0x084, PIN_OUTPUT, 0) /* (AG38) MCAN4_TX */ + >; + }; + + main_mcan16_pins_default: main-mcan16-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x028, PIN_INPUT, 0) /* (AE33) MCAN16_RX */ + J784S4_IOPAD(0x024, PIN_OUTPUT, 0) /* (AH34) MCAN16_TX */ + >; + }; + + main_usbss0_pins_default: main-usbss0-default-pins { + bootph-all; + pinctrl-single,pins =3D < + J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */ + >; + }; + + main_i2c3_pins_default: main-i2c3-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x064, PIN_INPUT, 13) /* (AF38) MCAN0_TX.I2C3_SCL */ + J784S4_IOPAD(0x060, PIN_INPUT, 13) /* (AE36) MCASP2_AXR1.I2C3_SDA */ + >; + }; + + main_mcasp0_pins_default: main-mcasp0-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x038, PIN_OUTPUT_PULLDOWN, 1) /* (AK35) MCASP0_ACLKX */ + J784S4_IOPAD(0x03c, PIN_OUTPUT_PULLDOWN, 1) /* (AK38) MCASP0_AFSX */ + J784S4_IOPAD(0x07c, PIN_OUTPUT_PULLDOWN, 1) /* (AJ38) MCASP0_AXR3 */ + J784S4_IOPAD(0x080, PIN_INPUT_PULLDOWN, 1) /* (AK34) MCASP0_AXR4 */ + >; + }; + + audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x078, PIN_OUTPUT, 1) /* (AH37) MCAN2_RX.AUDIO_EXT_REFCLK1= */ + >; + }; +}; + +&wkup_pmx2 { + bootph-all; + wkup_uart0_pins_default: wkup-uart0-default-pins { + bootph-all; + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ + J784S4_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */ + >; + }; + + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + bootph-all; + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ + J784S4_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-default-pins { + bootph-all; + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0= _CTSn */ + J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART= 0_RTSn */ + J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0= _RXD */ + J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART= 0_TXD */ + >; + }; + + mcu_cpsw_pins_default: mcu-cpsw-default-pins { + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ + J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ + J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ + J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ + J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ + J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ + J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio-default-pins { + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ + J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ + >; + }; + + mcu_adc0_pins_default: mcu-adc0-default-pins { + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ + J784S4_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ + J784S4_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ + J784S4_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ + J784S4_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ + J784S4_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ + J784S4_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ + J784S4_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ + >; + }; + + mcu_adc1_pins_default: mcu-adc1-default-pins { + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ + J784S4_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ + J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ + J784S4_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ + J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ + J784S4_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ + J784S4_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ + J784S4_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ + >; + }; + + mcu_mcan0_pins_default: mcu-mcan0-default-pins { + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */ + J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-default-pins { + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (H35) WKUP_GPIO0_4.MCU_MCAN1= _TX */ + J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_= RX */ + >; + }; + + mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (J38) MCU_SPI0_D1.WKUP_GPIO0_= 69 */ + >; + }; + + mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */ + >; + }; +}; + +&wkup_pmx1 { + status =3D "okay"; + + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins =3D < + /* (G33) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) + >; + }; +}; + +&wkup_pmx0 { + bootph-all; + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { + bootph-all; + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ + J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ + J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ + J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ + J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ + J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ + J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ + >; + }; +}; + +&wkup_pmx1 { + bootph-all; + mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { + bootph-all; + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */ + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ + >; + }; + + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { + bootph-all; + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ + J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ + J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ + J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ + J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ + J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ + J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ + >; + }; +}; + +&wkup_uart0 { + /* Firmware usage */ + status =3D "reserved"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wkup_uart0_pins_default>; +}; + +&wkup_i2c0 { + bootph-all; + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wkup_i2c0_pins_default>; + clock-frequency =3D <400000>; + + eeprom@50 { + /* CAV24C256WE-GT3 */ + compatible =3D "atmel,24c256"; + reg =3D <0x50>; + }; + + tps659413: pmic@48 { + compatible =3D "ti,tps6594-q1"; + reg =3D <0x48>; + system-power-controller; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_irq_pins_default>; + interrupt-parent =3D <&wkup_gpio0>; + interrupts =3D <39 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells =3D <2>; + ti,primary-pmic; + buck12-supply =3D <&vsys_3v3>; + buck3-supply =3D <&vsys_3v3>; + buck4-supply =3D <&vsys_3v3>; + buck5-supply =3D <&vsys_3v3>; + ldo1-supply =3D <&vsys_3v3>; + ldo2-supply =3D <&vsys_3v3>; + ldo3-supply =3D <&vsys_3v3>; + ldo4-supply =3D <&vsys_3v3>; + + regulators { + bucka12: buck12 { + regulator-name =3D "vdd_ddr_1v1"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka3: buck3 { + regulator-name =3D "vdd_ram_0v85"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka4: buck4 { + regulator-name =3D "vdd_io_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka5: buck5 { + regulator-name =3D "vdd_mcu_0v85"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa1: ldo1 { + regulator-name =3D "vdd_mcuio_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa2: ldo2 { + regulator-name =3D "vdd_mcuio_3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa3: ldo3 { + regulator-name =3D "vds_dll_0v8"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa4: ldo4 { + regulator-name =3D "vda_mcu_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + tps62873a: regulator@40 { + compatible =3D "ti,tps62873"; + reg =3D <0x40>; + bootph-pre-ram; + regulator-name =3D "VDD_CPU_AVS"; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <1330000>; + regulator-boot-on; + regulator-always-on; + }; + + tps62873b: regulator@43 { + compatible =3D "ti,tps62873"; + reg =3D <0x43>; + regulator-name =3D "VDD_CORE_0V8"; + regulator-min-microvolt =3D <760000>; + regulator-max-microvolt =3D <840000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&mcu_uart0 { + bootph-all; + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_uart0_pins_default>; +}; + +&main_uart8 { + bootph-all; + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_uart8_pins_default>; +}; + +&ufs_wrapper { + status =3D "okay"; +}; + +&fss { + bootph-all; + status =3D "okay"; +}; + +&ospi0 { + bootph-all; + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_def= ault>; + + flash@0 { + bootph-all; + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + spi-tx-bus-width =3D <8>; + spi-rx-bus-width =3D <8>; + spi-max-frequency =3D <25000000>; + cdns,tshsl-ns =3D <60>; + cdns,tsd2d-ns =3D <60>; + cdns,tchsh-ns =3D <60>; + cdns,tslch-ns =3D <60>; + cdns,read-delay =3D <4>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "ospi.tiboot3"; + reg =3D <0x0 0x80000>; + }; + + partition@80000 { + label =3D "ospi.tispl"; + reg =3D <0x80000 0x200000>; + }; + + partition@280000 { + label =3D "ospi.u-boot"; + reg =3D <0x280000 0x400000>; + }; + + partition@680000 { + label =3D "ospi.env"; + reg =3D <0x680000 0x40000>; + }; + + partition@6c0000 { + label =3D "ospi.env.backup"; + reg =3D <0x6c0000 0x40000>; + }; + + partition@800000 { + label =3D "ospi.rootfs"; + reg =3D <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + bootph-all; + label =3D "ospi.phypattern"; + reg =3D <0x3fc0000 0x40000>; + }; + }; + }; +}; + +&ospi1 { + bootph-all; + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_fss0_ospi1_pins_default>; + + flash@0 { + bootph-all; + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + spi-tx-bus-width =3D <1>; + spi-rx-bus-width =3D <4>; + spi-max-frequency =3D <40000000>; + cdns,tshsl-ns =3D <60>; + cdns,tsd2d-ns =3D <60>; + cdns,tchsh-ns =3D <60>; + cdns,tslch-ns =3D <60>; + cdns,read-delay =3D <2>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "qspi.tiboot3"; + reg =3D <0x0 0x80000>; + }; + + partition@80000 { + label =3D "qspi.tispl"; + reg =3D <0x80000 0x200000>; + }; + + partition@280000 { + label =3D "qspi.u-boot"; + reg =3D <0x280000 0x400000>; + }; + + partition@680000 { + label =3D "qspi.env"; + reg =3D <0x680000 0x40000>; + }; + + partition@6c0000 { + label =3D "qspi.env.backup"; + reg =3D <0x6c0000 0x40000>; + }; + + partition@800000 { + label =3D "qspi.rootfs"; + reg =3D <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + bootph-all; + label =3D "qspi.phypattern"; + reg =3D <0x3fc0000 0x40000>; + }; + }; + + }; +}; + +&main_i2c0 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c0_pins_default>; + + clock-frequency =3D <400000>; + + exp1: gpio@20 { + compatible =3D "ti,tca6416"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC= _RSTZ", + "PCIE1_2L_EP_RST_EN", "PCIE0_4L_MODE_SEL", "PCIE0_4L_PERSTZ", + "PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#", + "PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", + "AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ"; + + p12-hog { + /* P12 - AUDIO_MUX_SEL */ + gpio-hog; + gpios =3D <12 GPIO_ACTIVE_HIGH>; + output-low; + line-name =3D "AUDIO_MUX_SEL"; + }; + }; + + exp2: gpio@22 { + compatible =3D "ti,tca6424"; + reg =3D <0x22>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_P= WR_EN", + "USBC_PWR_EN", "USBC_MODE_SEL1", "USBC_MODE_SEL0", + "GPIO_LIN_EN", "R_CAN_STB", "CTRL_PM_I2C_OE#", + "ENET2_EXP_PWRDN", "ENET2_EXP_SPARE2", "CDCI2_RSTZ", + "USB2.0_MUX_SEL", "CANUART_MUX_SEL0", "CANUART_MUX2_SEL1", + "CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ", + "ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ", + "USER_INPUT1", "USER_LED1", "USER_LED2"; + + p13-hog { + /* P13 - CANUART_MUX_SEL0 */ + gpio-hog; + gpios =3D <13 GPIO_ACTIVE_HIGH>; + output-high; + line-name =3D "CANUART_MUX_SEL0"; + }; + + p15-hog { + /* P15 - CANUART_MUX1_SEL1 */ + gpio-hog; + gpios =3D <15 GPIO_ACTIVE_HIGH>; + output-high; + line-name =3D "CANUART_MUX1_SEL1"; + }; + }; +}; + +&main_i2c5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c5_pins_default>; + clock-frequency =3D <400000>; + status =3D "okay"; + + exp5: gpio@20 { + compatible =3D "ti,tca6408"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", + "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO3", + "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", + "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; + }; +}; + +&main_sdhci0 { + bootph-all; + /* eMMC */ + status =3D "okay"; + non-removable; + ti,driver-strength-ohm =3D <50>; + disable-wp; +}; + +&main_sdhci1 { + bootph-all; + /* SD card */ + status =3D "okay"; + pinctrl-0 =3D <&main_mmc1_pins_default>; + pinctrl-names =3D "default"; + disable-wp; + vmmc-supply =3D <&vdd_mmc1>; + vqmmc-supply =3D <&vdd_sd_dv>; +}; + +&main_gpio0 { + status =3D "okay"; +}; + +&mcu_cpsw { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_cpsw_pins_default>; +}; + +&davinci_mdio { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_mdio_pins_default>; + + mcu_phy0: ethernet-phy@0 { + reg =3D <0>; + ti,rx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,min-output-impedance; + }; +}; + +&mcu_cpsw_port1 { + status =3D "okay"; + phy-mode =3D "rgmii-rxid"; + phy-handle =3D <&mcu_phy0>; +}; + +&main_cpsw1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_cpsw2g_default_pins>; + status =3D "okay"; +}; + +&main_cpsw1_mdio { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_cpsw2g_mdio_default_pins>; + status =3D "okay"; + + main_cpsw1_phy0: ethernet-phy@0 { + reg =3D <0>; + ti,rx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,min-output-impedance; + }; +}; + +&main_cpsw1_port1 { + phy-mode =3D "rgmii-rxid"; + phy-handle =3D <&main_cpsw1_phy0>; + status =3D "okay"; +}; + +&mailbox0_cluster0 { + status =3D "okay"; + interrupts =3D <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status =3D "okay"; + interrupts =3D <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status =3D "okay"; + interrupts =3D <428>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster3 { + status =3D "okay"; + interrupts =3D <424>; + + mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + status =3D "okay"; + interrupts =3D <420>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_c71_1: mbox-c71-1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster5 { + status =3D "okay"; + interrupts =3D <416>; + + mbox_c71_2: mbox-c71-2 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_c71_3: mbox-c71-3 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mcu_r5fss0_core0 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0_core0 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region =3D <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region =3D <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + memory-region =3D <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + memory-region =3D <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&main_r5fss2_core0 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; + memory-region =3D <&main_r5fss2_core0_dma_memory_region>, + <&main_r5fss2_core0_memory_region>; +}; + +&main_r5fss2_core1 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; + memory-region =3D <&main_r5fss2_core1_dma_memory_region>, + <&main_r5fss2_core1_memory_region>; +}; + +&c71_0 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster4 &mbox_c71_0>; + memory-region =3D <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; + +&c71_1 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster4 &mbox_c71_1>; + memory-region =3D <&c71_1_dma_memory_region>, + <&c71_1_memory_region>; +}; + +&c71_2 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster5 &mbox_c71_2>; + memory-region =3D <&c71_2_dma_memory_region>, + <&c71_2_memory_region>; +}; + +&c71_3 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster5 &mbox_c71_3>; + memory-region =3D <&c71_3_dma_memory_region>, + <&c71_3_memory_region>; +}; + +&tscadc0 { + pinctrl-0 =3D <&mcu_adc0_pins_default>; + pinctrl-names =3D "default"; + status =3D "okay"; + adc { + ti,adc-channels =3D <0 1 2 3 4 5 6 7>; + }; +}; + +&tscadc1 { + pinctrl-0 =3D <&mcu_adc1_pins_default>; + pinctrl-names =3D "default"; + status =3D "okay"; + adc { + ti,adc-channels =3D <0 1 2 3 4 5 6 7>; + }; +}; + +&serdes_refclk { + status =3D "okay"; + clock-frequency =3D <100000000>; +}; + +&dss { + status =3D "okay"; + assigned-clocks =3D <&k3_clks 218 2>, + <&k3_clks 218 5>, + <&k3_clks 218 14>, + <&k3_clks 218 18>; + assigned-clock-parents =3D <&k3_clks 218 3>, + <&k3_clks 218 7>, + <&k3_clks 218 16>, + <&k3_clks 218 22>; +}; + +&serdes0 { + status =3D "okay"; + + serdes0_pcie1_link: phy@0 { + reg =3D <0>; + cdns,num-lanes =3D <2>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz0 1>, <&serdes_wiz0 2>; + }; + + serdes0_usb_link: phy@3 { + reg =3D <3>; + cdns,num-lanes =3D <1>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz0 4>; + }; +}; + +&serdes_wiz0 { + status =3D "okay"; +}; + +&usb_serdes_mux { + idle-states =3D <0>; /* USB0 to SERDES lane 3 */ +}; + +&usbss0 { + status =3D "okay"; + pinctrl-0 =3D <&main_usbss0_pins_default>; + pinctrl-names =3D "default"; + ti,vbus-divider; +}; + +&usb0 { + dr_mode =3D "otg"; + maximum-speed =3D "super-speed"; + phys =3D <&serdes0_usb_link>; + phy-names =3D "cdns3,usb3-phy"; +}; + +&serdes_wiz4 { + status =3D "okay"; +}; + +&serdes4 { + status =3D "okay"; + serdes4_dp_link: phy@0 { + reg =3D <0>; + cdns,num-lanes =3D <4>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz4 1>, <&serdes_wiz4 2>, + <&serdes_wiz4 3>, <&serdes_wiz4 4>; + }; +}; + +&mhdp { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&dp0_pins_default>; + phys =3D <&serdes4_dp_link>; + phy-names =3D "dpphy"; +}; + +&dss_ports { + /* DP */ + port { + dpi0_out: endpoint { + remote-endpoint =3D <&dp0_in>; + }; + }; +}; + +&main_i2c4 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c4_pins_default>; + clock-frequency =3D <400000>; + + exp4: gpio@20 { + compatible =3D "ti,tca6408"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + }; +}; + +&dp0_ports { + port@0 { + reg =3D <0>; + + dp0_in: endpoint { + remote-endpoint =3D <&dpi0_out>; + }; + }; + + port@4 { + reg =3D <4>; + + dp0_out: endpoint { + remote-endpoint =3D <&dp0_connector_in>; + }; + }; +}; + +&mcu_mcan0 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_mcan0_pins_default>; + phys =3D <&transceiver0>; +}; + +&mcu_mcan1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_mcan1_pins_default>; + phys =3D <&transceiver1>; +}; + +&main_mcan16 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_mcan16_pins_default>; + phys =3D <&transceiver2>; +}; + +&main_mcan4 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_mcan4_pins_default>; + phys =3D <&transceiver3>; +}; + +&pcie1_rc { + status =3D "okay"; + num-lanes =3D <2>; + reset-gpios =3D <&exp1 2 GPIO_ACTIVE_HIGH>; + phys =3D <&serdes0_pcie1_link>; + phy-names =3D "pcie-phy"; +}; + +&serdes1 { + status =3D "okay"; + + serdes1_pcie0_link: phy@0 { + reg =3D <0>; + cdns,num-lanes =3D <2>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz1 1>, <&serdes_wiz1 2>; + }; +}; + +&serdes_wiz1 { + status =3D "okay"; +}; + +&pcie0_rc { + status =3D "okay"; + reset-gpios =3D <&exp1 6 GPIO_ACTIVE_HIGH>; + phys =3D <&serdes1_pcie0_link>; + phy-names =3D "pcie-phy"; +}; + +&k3_clks { + /* Confiure AUDIO_EXT_REFCLK1 pin as output */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&audio_ext_refclk1_pins_default>; +}; + +&main_i2c3 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c3_pins_default>; + clock-frequency =3D <400000>; + + exp3: gpio@20 { + compatible =3D "ti,tca6408"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + }; + + pcm3168a_1: audio-codec@44 { + compatible =3D "ti,pcm3168a"; + reg =3D <0x44>; + #sound-dai-cells =3D <1>; + reset-gpios =3D <&exp3 0 GPIO_ACTIVE_LOW>; + clocks =3D <&audio_refclk1>; + clock-names =3D "scki"; + VDD1-supply =3D <&vsys_3v3>; + VDD2-supply =3D <&vsys_3v3>; + VCCAD1-supply =3D <&vsys_5v0>; + VCCAD2-supply =3D <&vsys_5v0>; + VCCDA1-supply =3D <&vsys_5v0>; + VCCDA2-supply =3D <&vsys_5v0>; + }; +}; + +&mcasp0 { + status =3D "okay"; + #sound-dai-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_mcasp0_pins_default>; + op-mode =3D <0>; /* MCASP_IIS_MODE */ + tdm-slots =3D <2>; + auxclk-fs-ratio =3D <256>; + serial-dir =3D < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 0 1 + 2 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; +}; --=20 2.45.1 From nobody Sun Feb 8 17:46:43 2026 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A06B1BD504; Wed, 31 Jul 2024 17:11:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722445865; cv=none; b=cU1IG/LrKrDlC5K3oKoJEpGjaG+OqJ3tmhN7ffmVq9TVClp/J5hy/CL5sUtUv+YQ+o+FAHD7nJcviEfOCLrNeB4VXXUbOI3xrm+PDBg2Hx6av6vARgAMfW1dq9yKahS61lSzguz0rNmbiBEX+oHqr6m/8LpuUzNPs5qj4Mx2+7Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722445865; c=relaxed/simple; bh=Dp1xqNmWjeEfyr8ivz3G2b03eCcQ102npwLXFy/YWnY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=o9U9+CkWe5YV0Vd1A07TMOgTWjjoVtPUPPKJcY4KT5KNRW1Ky6iDuCswH8/mDBAJISzz6YHx0Mmvpa6TOkMXg92ZDOTetsieBR52TGG/ypom+pWVX0QS5QUDPLwKOQex4KqYKeTB7Yg3v9+EhqvC/sT+ZL8xpeO1KxtlPlfxwqI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=m4qbGVlX; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="m4qbGVlX" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 46VHAwKd090501; Wed, 31 Jul 2024 12:10:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1722445858; bh=S0EVF2J3bxH4Rux65iS8ruAQxaG26bK/wUdfuAFiVo4=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=m4qbGVlXXQY965jCLoT3MZ1/YvKFkavB1VbWwULyiBc1hcytgZ7IIxTiGFvPRloh8 vQnSpAVHkrEe3nACDgg5ToGqg1gw8xWNYrHAbEo9vsGDOl21QQqcHHgu/u2CCsHpeU oaqWOCkxUjLN7LZn+PkacgA66GCYEVjBJrHehLwU= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 46VHAwWW109094 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 31 Jul 2024 12:10:58 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 31 Jul 2024 12:10:58 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 31 Jul 2024 12:10:58 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 46VHAVgT036362; Wed, 31 Jul 2024 12:10:54 -0500 From: Manorit Chawdhry Date: Wed, 31 Jul 2024 22:40:32 +0530 Subject: [PATCH v3 6/9] arm64: dts: ti: Split k3-j784s4-j742s2-evm-common.dtsi Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240731-b4-upstream-j742s2-v3-6-da7fe3aa9e90@ti.com> References: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> In-Reply-To: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Udit Kumar , Neha Malcom Francis , Aniket Limaye , Manorit Chawdhry X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1722445831; l=3971; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=Dp1xqNmWjeEfyr8ivz3G2b03eCcQ102npwLXFy/YWnY=; b=zqkjf/ntxkB2RWXxq2+tCnvBJZBixmFo5VYVDX995HSltebQsEfm4f1xXpGcOFCVAfNigi+Dx iKJuhr509S6BUcoxcc9Qn8l/PHc9xOi2Ux/ilyY5qw6fmSFoyKYRGZK X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 k3-j784s4-j742s2-evm-common.dtsi will be included in k3-j742s2-evm.dts at a later point so move j784s4 related stuff to k3-j784s4-evm.dts Signed-off-by: Manorit Chawdhry --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 49 ++++++++++++++++++= ++++ .../boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 42 ------------------- 2 files changed, 49 insertions(+), 42 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts= /ti/k3-j784s4-evm.dts index e3730b2bca92..2543983b7fe7 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -5,4 +5,53 @@ * EVM Board Schematics: https://www.ti.com/lit/zip/sprr458 */ =20 +/dts-v1/; + +#include +#include +#include "k3-j784s4.dtsi" #include "k3-j784s4-j742s2-evm-common.dtsi" + +/ { + compatible =3D "ti,j784s4-evm", "ti,j784s4"; + model =3D "Texas Instruments J784S4 EVM"; + + memory@80000000 { + device_type =3D "memory"; + bootph-all; + /* 32G RAM */ + reg =3D <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000007 0x80000000>; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + + c71_3_dma_memory_region: c71-dma-memory@ab000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xab000000 0x00 0x100000>; + no-map; + }; + + c71_3_memory_region: c71-memory@ab100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xab100000 0x00 0xf00000>; + no-map; + }; + }; +}; + +&mailbox0_cluster5 { + mbox_c71_3: mbox-c71-3 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&c71_3 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster5 &mbox_c71_3>; + memory-region =3D <&c71_3_dma_memory_region>, + <&c71_3_memory_region>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch= /arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi index ffa38f41679d..068ceed4ea15 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi @@ -4,17 +4,7 @@ * * EVM Board Schematics: https://www.ti.com/lit/zip/sprr458 */ - -/dts-v1/; - -#include -#include -#include "k3-j784s4.dtsi" - / { - compatible =3D "ti,j784s4-evm", "ti,j784s4"; - model =3D "Texas Instruments J784S4 EVM"; - chosen { stdout-path =3D "serial2:115200n8"; }; @@ -31,14 +21,6 @@ aliases { ethernet1 =3D &main_cpsw1_port1; }; =20 - memory@80000000 { - device_type =3D "memory"; - bootph-all; - /* 32G RAM */ - reg =3D <0x00000000 0x80000000 0x00000000 0x80000000>, - <0x00000008 0x80000000 0x00000007 0x80000000>; - }; - reserved_memory: reserved-memory { #address-cells =3D <2>; #size-cells =3D <2>; @@ -180,18 +162,6 @@ c71_2_memory_region: c71-memory@aa100000 { reg =3D <0x00 0xaa100000 0x00 0xf00000>; no-map; }; - - c71_3_dma_memory_region: c71-dma-memory@ab000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xab000000 0x00 0x100000>; - no-map; - }; - - c71_3_memory_region: c71-memory@ab100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xab100000 0x00 0xf00000>; - no-map; - }; }; =20 evm_12v0: regulator-evm12v0 { @@ -1133,11 +1103,6 @@ mbox_c71_2: mbox-c71-2 { ti,mbox-rx =3D <0 0 0>; ti,mbox-tx =3D <1 0 0>; }; - - mbox_c71_3: mbox-c71-3 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; }; =20 &mcu_r5fss0_core0 { @@ -1217,13 +1182,6 @@ &c71_2 { <&c71_2_memory_region>; }; =20 -&c71_3 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster5 &mbox_c71_3>; - memory-region =3D <&c71_3_dma_memory_region>, - <&c71_3_memory_region>; -}; - &tscadc0 { pinctrl-0 =3D <&mcu_adc0_pins_default>; pinctrl-names =3D "default"; --=20 2.45.1 From nobody Sun Feb 8 17:46:43 2026 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E6D71BD50F; Wed, 31 Jul 2024 17:11:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722445869; cv=none; b=R5s13FiQU2QCRL9eQcqbc/kRid8s3h/VqD663vqNo69FuGhxI73ujjAzgAjj07R3ZrgiVha1w9Hp3gyZtc4yvFMclh196b3If8JvXFACoV4THDA91VReuYkCp6eoceOr6bLjeFuhGXjngaoRdLsxQCjNIYnrC9+Lf9jFQiI1fH0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722445869; c=relaxed/simple; bh=OfqMQxCSWE27UlsNpnjdXgQIat1JVMciWYIFyaHChes=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Tt02BCS1XzoDQow/Nxaa8a7yzkgrT9iy5lLiD1XIxPD3HWu5pctzDuu3FVPqszPL17VacbAZSohm4lHVIKvr6+8uBWzHMzRLBSmqvaVH5YY1iVP/k/e/8ytiubOuhp2rPcx6c8UEMp4pwDm+jMzqQUvHRu7coKXkMHiRz9RcrwE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=EC7JD7TI; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="EC7JD7TI" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 46VHB2KI117340; Wed, 31 Jul 2024 12:11:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1722445862; bh=5x0WjPy3waX9hOSHXkRlMB+bk26nCzu1WtvsRQOSaAg=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=EC7JD7TIWkK3ISLCBkiYTF92bkTDowAZ7+h5FDGbhXAanF4p5hExltfS+eg7fL8Eh EcyrnKxR3BNLxaN8Mq+FQ+FvmbZfI7JLalVRaphW6l3d2z9FX/3UEQFdxA2gcPJ1KR gGAtyhUa2p0QKqSCI0q45EZPzXxp8HgSnfva+o+c= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 46VHB2t2082551 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 31 Jul 2024 12:11:02 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 31 Jul 2024 12:11:01 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 31 Jul 2024 12:11:01 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 46VHAVgU036362; Wed, 31 Jul 2024 12:10:58 -0500 From: Manorit Chawdhry Date: Wed, 31 Jul 2024 22:40:33 +0530 Subject: [PATCH v3 7/9] dt-bindings: arm: ti: Add bindings for J742S2 SoCs and Boards Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240731-b4-upstream-j742s2-v3-7-da7fe3aa9e90@ti.com> References: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> In-Reply-To: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Udit Kumar , Neha Malcom Francis , Aniket Limaye , Manorit Chawdhry , Krzysztof Kozlowski X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1722445831; l=871; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=OfqMQxCSWE27UlsNpnjdXgQIat1JVMciWYIFyaHChes=; b=TbppVw5loyyoXXIxse0DPMZZXlblNsDSWK8dZ+mLeAUiDj0MY+JB7XpTgjeMkPKSkviXe/d+r Uu5iU9JAOLGAotNasrCUt5OYDM1KuyCG+Q406zWSET8fX5Wzrx8uxwG X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Add devicetree bindings for J742S2 family of devices. Acked-by: Krzysztof Kozlowski Signed-off-by: Manorit Chawdhry --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentati= on/devicetree/bindings/arm/ti/k3.yaml index 4d9c5fbb4c26..074d6dc6092f 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -143,6 +143,12 @@ properties: - ti,j722s-evm - const: ti,j722s =20 + - description: K3 J742S2 SoC + items: + - enum: + - ti,j742s2-evm + - const: ti,j742s2 + - description: K3 J784s4 SoC items: - enum: --=20 2.45.1 From nobody Sun Feb 8 17:46:43 2026 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 696B91BF32B; Wed, 31 Jul 2024 17:11:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722445873; cv=none; b=MbmCF3abm9pQiho+TF36p9MFDqio2cfXTe4V8ltcKeTyVBgLHarnhYo0DSpSC1aLnSqVZGkykJHS4//1HV8WwvC7nJOduDTTZQ6pJb7Z++P6u84mqEVorHsUQ6x0LcZaBsYvNeUu+N5iglCD2coLUQ2ipXupbb0LjANEX5w1iqk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722445873; c=relaxed/simple; bh=By+tJFbhJfeTWyNNGJuwnR1vAIVP3c4xKyvcdU6oMWo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=MtbnomuLoCsp5ZXFP1ZPpq7XFBvjswPiGAs+K0qGyQBZqG6G5QQydpha2ftioh5OEfyKv2S2T6SVeH06Y8I3O91CNH0a2fAPF8RcxnADyJNkLUBdxLkDctLWkGbnfb39nir8X8YdDMvnc0TLgQHo+NrHNPQFW5hl1oBOD0scrPw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=vd1cjBHh; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="vd1cjBHh" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 46VHB6lu090565; Wed, 31 Jul 2024 12:11:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1722445866; bh=6g9jwnaOxNsC1QlfmvMcnz6WmMwojd9rL7P/E6rLns0=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=vd1cjBHhZVz7q32htoiPcjWiX6dRV2yqM6bEjmr3HuEmd1YNzERGQCwDkF8RawBwI mn2UNy8hjyzh6uNQrnkkSFDaRl5ZnTV96V9iybvHWsJu1/2vr7uqrRk7f8qnD17+XC ZRRmzGedbZkfPJ2MUxeK1AFZti0/BIEst7BV/Qb4= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 46VHB6uD109225 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 31 Jul 2024 12:11:06 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 31 Jul 2024 12:11:05 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 31 Jul 2024 12:11:05 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 46VHAVgV036362; Wed, 31 Jul 2024 12:11:02 -0500 From: Manorit Chawdhry Date: Wed, 31 Jul 2024 22:40:34 +0530 Subject: [PATCH v3 8/9] arm64: dts: ti: Introduce J742S2 SoC family Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240731-b4-upstream-j742s2-v3-8-da7fe3aa9e90@ti.com> References: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> In-Reply-To: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Udit Kumar , Neha Malcom Francis , Aniket Limaye , Manorit Chawdhry X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1722445831; l=5457; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=By+tJFbhJfeTWyNNGJuwnR1vAIVP3c4xKyvcdU6oMWo=; b=QmOxY/XVUe6/61GBkqbK1VDwWMnKUUfXrKv7fuPVQq5z991GdbKfUTT5FWV7d1hQrIBWVESVO Cwc3JwT3SNYBZTIgHD0B3HJ5mQwmbwrCAH1VBlYNeqaO35H+vyhZU12 X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 This device is a subset of J784S4 and shares the same memory map and thus the nodes are being reused from J784S4 to avoid duplication. Here are some of the salient features of the J742S2 automotive grade application processor: The J742S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive, ADAS and industrial applications requiring AI at the network edge. This SoC extends the K3 Jacinto 7 family of SoCs with focus on raising performance and integration while providing interfaces, memory architecture and compute performance for multi-sensor, high concurrency applications. Some changes that this devices has from J784S4 are: * 4x Cortex-A72 vs 8x Cortex-A72 * 3x C7x DSP vs 4x C7x DSP * 4 port ethernet switch vs 8 port ethernet switch ( Refer Table 2-1 for Device comparison with J7AHP ) Link: https://www.ti.com/lit/pdf/spruje3 (TRM) Signed-off-by: Manorit Chawdhry --- arch/arm64/boot/dts/ti/k3-j742s2-main.dtsi | 45 ++++++++++ arch/arm64/boot/dts/ti/k3-j742s2.dtsi | 98 ++++++++++++++++++= ++++ .../arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi | 5 +- 3 files changed, 146 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j742s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j742s2-main.dtsi new file mode 100644 index 000000000000..b320c27f7afe --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j742s2-main.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree Source for J742S2 SoC Family + * + * TRM: https://www.ti.com/lit/pdf/spruje3 + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +&c71_0 { + firmware-name =3D "j742s2-c71_0-fw"; +}; + +&c71_1 { + firmware-name =3D "j742s2-c71_1-fw"; +}; + +&c71_2 { + firmware-name =3D "j742s2-c71_2-fw"; +}; + +&main_r5fss0_core0 { + firmware-name =3D "j742s2-main-r5f0_0-fw"; +}; + +&main_r5fss0_core1 { + firmware-name =3D "j742s2-main-r5f0_1-fw"; +}; + +&main_r5fss1_core0 { + firmware-name =3D "j742s2-main-r5f1_0-fw"; +}; + +&main_r5fss1_core1 { + firmware-name =3D "j742s2-main-r5f1_1-fw"; +}; + +&main_r5fss2_core0 { + firmware-name =3D "j742s2-main-r5f2_0-fw"; +}; + +&main_r5fss2_core1 { + firmware-name =3D "j742s2-main-r5f2_1-fw"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j742s2.dtsi b/arch/arm64/boot/dts/ti= /k3-j742s2.dtsi new file mode 100644 index 000000000000..7a72f82f56d6 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j742s2.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree Source for J742S2 SoC Family + * + * TRM: https://www.ti.com/lit/pdf/spruje3 + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * + */ +#include "k3-j784s4-j742s2-common.dtsi" + +/ { + model =3D "Texas Instruments K3 J742S2 SoC"; + compatible =3D "ti,j742s2"; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x000>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; + }; + + cpu1: cpu@1 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x001>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; + }; + + cpu2: cpu@2 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x002>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; + }; + + cpu3: cpu@3 { + compatible =3D "arm,cortex-a72"; + reg =3D <0x003>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&L2_0>; + }; + }; +}; + +#include "k3-j742s2-main.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi b/arch/arm= 64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi index 958054ab1018..43fee57f0926 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Device Tree Source for J784S4 SoC Family + * Device Tree Source for J784S4 and J742S2 SoC Family * - * TRM (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52 + * TRM (j784s4) (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52 + * TRM (j742s2): https://www.ti.com/lit/pdf/spruje3 * * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti= .com/ * --=20 2.45.1 From nobody Sun Feb 8 17:46:43 2026 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1947B1BE227; Wed, 31 Jul 2024 17:11:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722445876; cv=none; b=QRluBDox4/oH2Y2vZoCRPJxvqpj7jjWYvW1TOOHlXHdzmJ8H/KtPqKkQoDRFWVMVlbJGXB2ZrfN8/hd+4JCqPht3MX9VrX0ety6Hw98YovT3xcFb6Ybv4V5BqPkrVmDvACorwhpxBPjGV2j2bXAZ9vITlGNxlS2nsYOM5PVdndU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722445876; c=relaxed/simple; bh=bLKIStg32CKaj6+VtwdHIZvNTmLrFgAVJyIBzHe+KWc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=ZqzvUV9kfD7A/Yb6KrbMsCRYWZy/efiB3rjZtIvOA7990vrhlm+EjAswBMuqR94YjatgLdEKk3tt5EJ6oLCqcvGLWstTJ+c/7VSs4ZbK6+2bcScOqIE++/gMfM2LWep7cpgSSn09LK2fLGNb5NlC0VUzR5rHU3NpshNaWYbtnLg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=jViwoHkM; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="jViwoHkM" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 46VHB9l3117367; Wed, 31 Jul 2024 12:11:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1722445869; bh=m8yE4PnEM9kCNwvR96U6Zj1VFy8LOKMPDIbWtSVfzE4=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=jViwoHkMf7BhDByqtGuxiueikGLsGl1rKo5oIhHK5eyv6A4SnnqXqbTnmy6eVdXLg ZdkEOHFmxW9LbOiYZnctkK6Mxd4p+th3D5bwGyZZvR2Z3A/4bP4dWZr9r8lm+VCrMv wxAp7t4yLBi0+uKSZPJnxRdFlQdXvcbc6Og96/hQ= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 46VHB9Gl109252 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 31 Jul 2024 12:11:09 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 31 Jul 2024 12:11:09 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 31 Jul 2024 12:11:09 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 46VHAVgW036362; Wed, 31 Jul 2024 12:11:06 -0500 From: Manorit Chawdhry Date: Wed, 31 Jul 2024 22:40:35 +0530 Subject: [PATCH v3 9/9] arm64: dts: ti: Add support for J742S2 EVM board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240731-b4-upstream-j742s2-v3-9-da7fe3aa9e90@ti.com> References: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> In-Reply-To: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Udit Kumar , Neha Malcom Francis , Aniket Limaye , Manorit Chawdhry X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1722445831; l=3518; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=bLKIStg32CKaj6+VtwdHIZvNTmLrFgAVJyIBzHe+KWc=; b=ihjIAZX8EBLlNu8Yw2LQskvPqfR4ghVf2LcNY2eyB3HR/dRzUDpo5AIAp0Orv4gmPc/iHTjfr NmXYKk1G3X8BUmZTOiCeTOyiHWoPBXKsI7v6WbDc20fCvXle/+zcm5n X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 J742S2 EVM board is designed for TI J742S2 SoC. It supports the following interfaces: * 16 GB DDR4 RAM * x2 Gigabit Ethernet interfaces capable of working in Switch and MAC mode * x1 Input Audio Jack, x1 Output Audio Jack * x1 USB2.0 Hub with two Type A host and x1 USB 3.1 Type-C Port * x1 4L PCIe connector * x1 UHS-1 capable micro-SD card slot * 512 Mbit OSPI flash, 1 Gbit Octal NAND flash, 512 Mbit QSPI flash, UFS flash. * x6 UART through UART-USB bridge * XDS110 for onboard JTAG debug using USB * Temperature sensors, user push buttons and LEDs * x1 GESI expander, x2 Display connector * x1 15-pin CSI header * x6 MCAN instances Link: https://www.ti.com/lit/ug/sprujd8/sprujd8.pdf (EVM user guide) Link: https://www.ti.com/lit/zip/SPAC001 (Schematics) Signed-off-by: Manorit Chawdhry Reviewed-By: Beleswar Padhi --- arch/arm64/boot/dts/ti/Makefile | 4 ++++ arch/arm64/boot/dts/ti/k3-j742s2-evm.dts | 26 ++++++++++++++++++= ++++ .../boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 3 ++- 3 files changed, 32 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index e20b27ddf901..1bf645726a10 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -119,6 +119,9 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-pcie0-pcie1-ep= .dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-quad-port-eth-exp1.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-usxgmii-exp1-exp2.dtbo =20 +# Boards with J742S2 SoC +dtb-$(CONFIG_ARCH_K3) +=3D k3-j742s2-evm.dtb + # Build time test only, enabled by CONFIG_OF_ALL_DTBS k3-am625-beagleplay-csi2-ov5640-dtbs :=3D k3-am625-beagleplay.dtb \ k3-am625-beagleplay-csi2-ov5640.dtbo @@ -240,3 +243,4 @@ DTC_FLAGS_k3-j721e-common-proc-board +=3D -@ DTC_FLAGS_k3-j721e-sk +=3D -@ DTC_FLAGS_k3-j721s2-common-proc-board +=3D -@ DTC_FLAGS_k3-j784s4-evm +=3D -@ +DTC_FLAGS_k3-j742s2-evm +=3D -@ diff --git a/arch/arm64/boot/dts/ti/k3-j742s2-evm.dts b/arch/arm64/boot/dts= /ti/k3-j742s2-evm.dts new file mode 100644 index 000000000000..ac683bcbfe97 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j742s2-evm.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * + * EVM Board Schematics: https://www.ti.com/lit/zip/SPAC001 + */ + +/dts-v1/; + +#include +#include +#include "k3-j742s2.dtsi" +#include "k3-j784s4-j742s2-evm-common.dtsi" + +/ { + model =3D "Texas Instruments J742S2 EVM"; + compatible =3D "ti,j742s2-evm", "ti,j742s2"; + + memory@80000000 { + device_type =3D "memory"; + bootph-all; + /* 16G RAM */ + reg =3D <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000003 0x80000000>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch= /arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi index 068ceed4ea15..a7bb1857b4e8 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi @@ -2,7 +2,8 @@ /* * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti= .com/ * - * EVM Board Schematics: https://www.ti.com/lit/zip/sprr458 + * EVM Board Schematics(j784s4): https://www.ti.com/lit/zip/sprr458 + * EVM Board Schematics(j742s2): https://www.ti.com/lit/zip/SPAC001 */ / { chosen { --=20 2.45.1