From nobody Thu Sep 19 01:00:13 2024 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23F131A4F15 for ; Wed, 31 Jul 2024 07:05:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722409553; cv=none; b=krK7tgKGEyvWPCrKtwNc8TxI/+WqRIWoQ05Y2dmq8lzkRAde2r7ZydPEqEJlgDxvhRs4AAL1hNza0aZDB9TP9+xDWZrsU5mpUl/rDEyWGGXUxQVJKLoKTO16BzLTuCY55v+lM1/dcBiFGa5RVj3VkIo793rx1Z7u4CH/ME4neMg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722409553; c=relaxed/simple; bh=CVeeM9agMlhOuzB//PVeugDjFr+JlKm6KzovrQHMqX0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=s25lwufuiphs3jhh+s6G4sSg+wbNgJrOGWH3IzBB9OdLsC28VR5uQnqLRZbm4GYifc18ehCWqq+FHaOAqZy7UqTr1t27hnMypJ4SeX5oooVa2nFwAA9iu+PEbG8r2wXniRYMUrwa+fn/aUkTrYyx9rKYZDh9DKgEMeaI72gWXrw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=iSziX4iK; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="iSziX4iK" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-4280ee5f1e3so34247865e9.0 for ; Wed, 31 Jul 2024 00:05:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1722409549; x=1723014349; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=mFCuIz7C9sKLND6RuCsZOq0lXreIYCfstfjNtwHxLOQ=; b=iSziX4iKBzQ/BtWR7pcIVTQ4O8pnQHYw0R85Zj1PUNfh7p3S2OKFggaKwkW4UYiOQY yUcLolZv/e4GkqTZtKbO9+uWUmAYGlGgQgWGR9YiO+N+YJA/621dQveMorlHNc69bccu wtLlA/NQWi+rfN9k7FAY3fMPI5zZzvwf3GCXtdfOjlPqU8UndERB2MHneenSeqdnnX9g WA2c2V7YykmTB5wm6//740qxmCczpvBtp438uZUuCeC0CQ1c7HKtGR0Fn14G9VuOYWJR 6KPkFaSChq+FTZGMHDLTVAKpLMbeW3lRNVsJUX54x9uKPlM9tXPTH7gECeHr5uXNz336 j9IQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722409549; x=1723014349; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mFCuIz7C9sKLND6RuCsZOq0lXreIYCfstfjNtwHxLOQ=; b=aoTezMqKSNYdCIOpl9OAPZnooEKXAmDUBSl+zuvlRTi6fg3sCKD1tNgTdcNDddWiQ0 lyhLMgaEu7lW9bqNDfDxGrl/uog359FBimWJZSdL50YcJElAb9XmsZUd8imApJtQugFk /qLmHKOLOy73pAPBqy3gdht7Mt3VBh5vNW5aAe4Tm3epRv68oInDHFfPXEFOd0EjX+2+ FZDpSaI3Z6MRqmlq3ov4tOwVl3z7xOd1cE9HeDMaR+ZikiB855nCOCdzzUmVwKLG8QE3 NTaIv25NY9+71bsVdzw6vghyMcxQJvMuDhzkak0Ag9bZNYgxUFlJUzsZxUbpTIZTT8tu o8Mw== X-Forwarded-Encrypted: i=1; AJvYcCX0xWf9DJgoN0PlLerM54QRBIUNU0GYP5WHHmhvqOSz4+rXTdaMHgniuAL0BfPgE/I+Ef+QmufI9KvwQRWMF2ujibearPWWc58Na+C5 X-Gm-Message-State: AOJu0Ywo5Q9ib2TiTS2zlf6HDRkAOT6PjFJFRVr7y7Ot/q7wBFDn76kp G2L+MzBXXsc08uyKEHfuX4roFZ6FqVc3P8b247Pe5uzYbBuljIfcXwxNS7AymcA= X-Google-Smtp-Source: AGHT+IGetKYVTW5hZ9jxdlylMXS0vLE2omCWqfpv9It70piPrSEHFmOVA4GtdWvPtzBnHg0b0GPogQ== X-Received: by 2002:a05:600c:1e26:b0:426:5b84:86d2 with SMTP id 5b1f17b1804b1-42811da946fmr100643465e9.20.1722409549382; Wed, 31 Jul 2024 00:05:49 -0700 (PDT) Received: from [192.168.1.61] (2a02-842a-d52e-6101-6f8f-5617-c4b6-8627.rev.sfr.net. [2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4282b8a2593sm9953215e9.4.2024.07.31.00.05.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jul 2024 00:05:49 -0700 (PDT) From: Julien Stephan Date: Wed, 31 Jul 2024 09:05:42 +0200 Subject: [PATCH v2 1/7] dt-bindings: iio: adc: ad7380: add single-ended compatible parts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240731-ad7380-add-single-ended-chips-v2-1-cd63bf05744c@baylibre.com> References: <20240731-ad7380-add-single-ended-chips-v2-0-cd63bf05744c@baylibre.com> In-Reply-To: <20240731-ad7380-add-single-ended-chips-v2-0-cd63bf05744c@baylibre.com> To: Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Lars-Peter Clausen , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Cc: Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Julien Stephan , Krzysztof Kozlowski X-Mailer: b4 0.13.0 Adding ad7386/7/8 single-ended compatible parts, and the corresponding ad7386-4/7-4/8-4 4 channels. Acked-by: Krzysztof Kozlowski Signed-off-by: Julien Stephan Reviewed-by: David Lechner --- Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml | 13 +++++++++++= ++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7380.yaml index 899b777017ce..bd19abb867d9 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml @@ -15,10 +15,17 @@ description: | * https://www.analog.com/en/products/ad7381.html * https://www.analog.com/en/products/ad7383.html * https://www.analog.com/en/products/ad7384.html + * https://www.analog.com/en/products/ad7386.html + * https://www.analog.com/en/products/ad7387.html + * https://www.analog.com/en/products/ad7388.html * https://www.analog.com/en/products/ad7380-4.html * https://www.analog.com/en/products/ad7381-4.html * https://www.analog.com/en/products/ad7383-4.html * https://www.analog.com/en/products/ad7384-4.html + * https://www.analog.com/en/products/ad7386-4.html + * https://www.analog.com/en/products/ad7387-4.html + * https://www.analog.com/en/products/ad7388-4.html + =20 $ref: /schemas/spi/spi-peripheral-props.yaml# =20 @@ -29,10 +36,16 @@ properties: - adi,ad7381 - adi,ad7383 - adi,ad7384 + - adi,ad7386 + - adi,ad7387 + - adi,ad7388 - adi,ad7380-4 - adi,ad7381-4 - adi,ad7383-4 - adi,ad7384-4 + - adi,ad7386-4 + - adi,ad7387-4 + - adi,ad7388-4 =20 reg: maxItems: 1 --=20 2.45.1 From nobody Thu Sep 19 01:00:13 2024 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1FBD51A4F18 for ; Wed, 31 Jul 2024 07:05:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722409554; cv=none; b=LNf+appWockrM5TtPttc0wjr59GaXwHb+Z6WPrCXNlIWv/rj+ewVK/meJnQDuk/2BsmKP0Xqi/0JUv2kp5Jwc4vTxa1l0hiibX706kqwVWbW8Pnu6L2juNNDqrAe1tx3aKWRwe8nIkCzDaMV2IWdeWyPSy+Lxwgr5uN1rDpFf18= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722409554; c=relaxed/simple; bh=DmT1lkaAUXmyCjselEQKioQon1H08Xpiwh19x8GvP9A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=c3ETY2h6ap5h3rE66ao01VAjwRa+a0AjqhsrbGBjsofkCrYsAgDIU2RIdSJitpfo/GQ48Hg9n/5wjinUBKTVOSba+cRZZxXmKQ/ZW2aDknmPKYUf+zcLeH3j9iim1FMedd+oH48745h/fKFfvCdwTMxtqU4upUjv9imQymH0d8E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=mZlkrUgz; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="mZlkrUgz" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-4280bbdad3dso34723715e9.0 for ; Wed, 31 Jul 2024 00:05:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1722409550; x=1723014350; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=xh88NQ9QvsN4DODTuwx5BwmanL/AOw553yOYeKfdouo=; b=mZlkrUgzRHEXswHt7YXtfJQ0FC+Up+umcTzWRSkkJIOFkva7Ju10l7FrrR4tS24MwH jk5MgxQUahDjxi87zpFtKOReoAqN++JnuTAQNSc5pq2aHEo5oa1NYs4uMH/bZ2wAL74Y XBpdhH9k0/61DyLZsC3vTgGBkI7yDV602QkXqkBLlQK8R4GgcDi87Xrl9x9w0Xavm7ZP YESHvtRry99J1Yk7z3JuGvSkfFzptJmgYpSOrMFTz5Wg78a479qrkIhwwqhWAmm7JFQW DHPZwvryQ+kzGMV78hu35P1B3RHOIHtJdIDi4mNFAJaTKBDrR6fQFwMVikia7L923dfo BkyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722409550; x=1723014350; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xh88NQ9QvsN4DODTuwx5BwmanL/AOw553yOYeKfdouo=; b=m5ehaEw7LAk+zFuXf8OxJYx2hifQqRyBlgcwdGqsxopVn2jYAAj0s+LbdH+un7gzK5 b9OVQuTu3lBBYaHHbhJcwFVdxFxMKpLrOCoRhhT1AAN+Ovm7aYfbem2JWIk+cw9C26Pm T8hJqIvHp3y5M8k0oH83XdNMb4DRyqqHU62sEtsh9daTqr4hP30CAvhZyVy2Nvjvsjl6 UcnjmHCZmN80iNtmYrdbRG6iptOaduiGvTxsnHo1wPEXNKWAThbUUTHAq/osUQufGeWt clBfGnNp9Z2doO6M+2bQ8weGoSGUTotSt5NEdZkitHlkJOfkMeRaIkg3DeY07w1lHNnu RGtA== X-Forwarded-Encrypted: i=1; AJvYcCWhafrpDfSsBNn6wMA+Cr2BxzOvNLuygAQQHtnLN0MV9gTSSgRfRjhUXy+OJZRugCN7WvvMYQt4QWMaKXhcUKwITzOz8qfm8DIjp1EU X-Gm-Message-State: AOJu0Yw2rSQ4/R0ssAyB5n15UznytbWD4vUA+S19kK8SV6tlOWnxyf6j 28UPSGCYKEBDwpxJ9mQ7p+mpn6J87efeGUVOe8bFhaYdGcBr7tmtc8UaeEWHi3E= X-Google-Smtp-Source: AGHT+IF1BsxjqLXjQCg0o51ymFFuLeG7sRz3r2y5FeNtGXo/X7OD6zqXUXoKy9RwDi4FIdp/PydsMw== X-Received: by 2002:a05:600c:4f8e:b0:426:6379:3b4f with SMTP id 5b1f17b1804b1-42811df0e76mr90800015e9.31.1722409550521; Wed, 31 Jul 2024 00:05:50 -0700 (PDT) Received: from [192.168.1.61] (2a02-842a-d52e-6101-6f8f-5617-c4b6-8627.rev.sfr.net. [2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4282b8a2593sm9953215e9.4.2024.07.31.00.05.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jul 2024 00:05:50 -0700 (PDT) From: Julien Stephan Date: Wed, 31 Jul 2024 09:05:43 +0200 Subject: [PATCH v2 2/7] iio: core: add function to retrieve active_scan_mask index Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240731-ad7380-add-single-ended-chips-v2-2-cd63bf05744c@baylibre.com> References: <20240731-ad7380-add-single-ended-chips-v2-0-cd63bf05744c@baylibre.com> In-Reply-To: <20240731-ad7380-add-single-ended-chips-v2-0-cd63bf05744c@baylibre.com> To: Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Lars-Peter Clausen , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Cc: Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Julien Stephan X-Mailer: b4 0.13.0 Add a function to retrieve the index of the active scan mask inside the available scan masks array. As in iio_scan_mask_match and iio_sanity_check_avail_scan_masks, this function does not handle multi-long masks correctly. It only checks the first long to be zero, and will use such mask as a terminator even if there was bits set after the first long. This should be fine since the available_scan_mask has already been sanity tested using iio_sanity_check_avail_scan_masks. See iio_scan_mask_match and iio_sanity_check_avail_scan_masks for more details Signed-off-by: Julien Stephan Reviewed-by: David Lechner --- drivers/iio/industrialio-core.c | 43 +++++++++++++++++++++++++++++++++++++= ++++ include/linux/iio/iio.h | 2 ++ 2 files changed, 45 insertions(+) diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-cor= e.c index e6fad8a6a1fc..f18f48c7eb03 100644 --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c @@ -1965,6 +1965,49 @@ static void iio_sanity_check_avail_scan_masks(struct= iio_dev *indio_dev) } } =20 +/** + * iio_active_scan_mask_index - Get index of the active scan mask inside t= he + * available scan masks array + * @indio_dev: the IIO device containing the active and available scan mas= ks + * + * Returns: the index or -EINVAL if active_scan_mask is not set + */ +int iio_active_scan_mask_index(struct iio_dev *indio_dev) + +{ + const unsigned long *av_masks; + unsigned int masklength =3D iio_get_masklength(indio_dev); + int i =3D 0; + + if (!indio_dev->active_scan_mask) + return -EINVAL; + + /* + * As in iio_scan_mask_match and iio_sanity_check_avail_scan_masks, + * the condition here do not handle multi-long masks correctly. + * It only checks the first long to be zero, and will use such mask + * as a terminator even if there was bits set after the first long. + * + * This should be fine since the available_scan_mask has already been + * sanity tested using iio_sanity_check_avail_scan_masks. + * + * See iio_scan_mask_match and iio_sanity_check_avail_scan_masks for + * more details + */ + av_masks =3D indio_dev->available_scan_masks; + while (*av_masks) { + if (indio_dev->active_scan_mask =3D=3D av_masks) + return i; + av_masks +=3D BITS_TO_LONGS(masklength); + i++; + } + + dev_warn(indio_dev->dev.parent, + "active scan mask is not part of the avaialable scan masks\n"); + return -EINVAL; +} +EXPORT_SYMBOL_GPL(iio_active_scan_mask_index); + int __iio_device_register(struct iio_dev *indio_dev, struct module *this_m= od) { struct iio_dev_opaque *iio_dev_opaque =3D to_iio_dev_opaque(indio_dev); diff --git a/include/linux/iio/iio.h b/include/linux/iio/iio.h index dd6bbc468283..73b75a9ff314 100644 --- a/include/linux/iio/iio.h +++ b/include/linux/iio/iio.h @@ -864,6 +864,8 @@ static inline unsigned int iio_get_masklength(const str= uct iio_dev *indio_dev) return indio_dev->masklength; } =20 +int iio_active_scan_mask_index(struct iio_dev *indio_dev); + /** * iio_for_each_active_channel - Iterated over active channels * @indio_dev: the IIO device --=20 2.45.1 From nobody Thu Sep 19 01:00:13 2024 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3E101A4F33 for ; Wed, 31 Jul 2024 07:05:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722409555; cv=none; b=STIE5TC4WI4nE1JhgOIuM+/19VWB4DNZSWp6+H5txGCHW5NZD8aP99eC9oEvlwAPg7y/UZj0uAFrNeby0XGJJ6b+dAlV0IraULLug6IbKAvXoFz3W/xQYY3XHdH/RJ9lTxsqYvDP88B7xB472eZAiAcA7xoMyyiAgrM3KAfgSGo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722409555; c=relaxed/simple; bh=QnD2BToR4Nwm3fzJOwnxm/3JHf/41UbLqSYaKrl5UA0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NeCe7LnN5JIuw6EzMhDmZLKLwlqOJlBICrtYk01oA4VUTJ4ArrT8E7BlNnNJISPe8Bac98VRyawlCBfsyl/tTYyCRojIjR9UpDozuk9+KBPbrUkqu921FkBuLKov+JkD8EiGIM/Kr9FUrIEGlmKm504XM3A5qdSsYWW1xXLrqTA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=jpb8Wchr; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="jpb8Wchr" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-4281c164408so27010505e9.1 for ; Wed, 31 Jul 2024 00:05:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1722409552; x=1723014352; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ma/nRsNL/NmomeGPp3xpJ7bK2CtwegdhnZZFnIG8n9I=; b=jpb8Wchr15EQ9GEzyz3Ht6SvL6G8C6Qsfwf4yHaxU/LNpln4X6VGpvHpfp8dKoB5AG 5A7HLnSDJR6kPrsXij7ITnMDj6mNvfZr0yLf3XHkrp3chogdAX37bgB9XPkWemPLyNfA t4UB9wTAnRgbZZQebpvScmoA2PJHh+GlPVkfOMe+MlNzNYKh6ELMj7Y/E7XADcz+I+41 +iKhwTRbnijsAE+/W286gwP+dXE6Mdjl+yPEiojFRHyX/0eRC7xlu9buGNh07bNElipi Sh6W7zGokVInJbT6X6zu71jh8QAG8yyJSyHeK96oyHRp4VmoP5RLksghyZECUs5xLXm/ klcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722409552; x=1723014352; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ma/nRsNL/NmomeGPp3xpJ7bK2CtwegdhnZZFnIG8n9I=; b=Nl6fILMV/JcbAax9OP+UPjSK21ntp5RIJHKQ2GV1OfWmjQ1C+kWITN/9PXQJ1IN7x0 njyNYcj6iM90gxaCRU7U1WW3CxcDWRWrLQTsAXUySEQriCFP0dElOnHglQ0ag5dt7qKo c45L3sJ2VMailbWZ6Azc9AhPJsjMWWO1y/eJZaJZCG5PH77W9N53kEVhCrxERhLk8kCH W+RbvIStBYgYqe/o7x4L/Tixn+M8wATOboICcnFMuTFuqlNhmGHo/ZjRuD/2iLQzsBym xcPaX9AJDZ2ahndFl9cUbV/bCpc3oMjbRQWpumREyfb3joLZsAZPzkUA5tjqHq8nm/XN /Ieg== X-Forwarded-Encrypted: i=1; AJvYcCU7Uj/N0SODZzwfR75djniS1pFMQUj/oc9P9C7uwNgJkkTdPtsSoCj4pUFAuE7EX/iQq2eggfIl1B2Oobg=@vger.kernel.org X-Gm-Message-State: AOJu0YwsUJ0x1dm9ZLI5J9PIM6oGQ3J8Fpkpg/CYrj30Ni8RgICWH2ko 90SHLyHwBKv0YMSecva4qPNgRdWSPMB0eppre84IJxHz+a3lE9ehvJnirgJ9pzs= X-Google-Smtp-Source: AGHT+IFTtyFkmP5aNXcUZvN5CS82N1Zzoo59tEP+gFc3i3IpNJlN+gyZnV2sH7d17TEGTLQWL6ZGJA== X-Received: by 2002:a05:600c:35d5:b0:426:61af:e1d6 with SMTP id 5b1f17b1804b1-42811e131aamr86638515e9.29.1722409551968; Wed, 31 Jul 2024 00:05:51 -0700 (PDT) Received: from [192.168.1.61] (2a02-842a-d52e-6101-6f8f-5617-c4b6-8627.rev.sfr.net. [2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4282b8a2593sm9953215e9.4.2024.07.31.00.05.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jul 2024 00:05:51 -0700 (PDT) From: Julien Stephan Date: Wed, 31 Jul 2024 09:05:44 +0200 Subject: [PATCH v2 3/7] iio: adc: ad7380: add missing trailing commas Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240731-ad7380-add-single-ended-chips-v2-3-cd63bf05744c@baylibre.com> References: <20240731-ad7380-add-single-ended-chips-v2-0-cd63bf05744c@baylibre.com> In-Reply-To: <20240731-ad7380-add-single-ended-chips-v2-0-cd63bf05744c@baylibre.com> To: Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Lars-Peter Clausen , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Cc: Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Julien Stephan X-Mailer: b4 0.13.0 Add missing trailing commas in iio_scan_type structures Signed-off-by: Julien Stephan Reviewed-by: David Lechner --- drivers/iio/adc/ad7380.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index 7568cd0a2b32..72fece383f72 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -97,13 +97,13 @@ static const struct iio_scan_type ad7380_scan_type_14[]= =3D { .sign =3D 's', .realbits =3D 14, .storagebits =3D 16, - .endianness =3D IIO_CPU + .endianness =3D IIO_CPU, }, [AD7380_SCAN_TYPE_RESOLUTION_BOOST] =3D { .sign =3D 's', .realbits =3D 16, .storagebits =3D 16, - .endianness =3D IIO_CPU + .endianness =3D IIO_CPU, }, }; =20 @@ -113,13 +113,13 @@ static const struct iio_scan_type ad7380_scan_type_16= [] =3D { .sign =3D 's', .realbits =3D 16, .storagebits =3D 16, - .endianness =3D IIO_CPU + .endianness =3D IIO_CPU, }, [AD7380_SCAN_TYPE_RESOLUTION_BOOST] =3D { .sign =3D 's', .realbits =3D 18, .storagebits =3D 32, - .endianness =3D IIO_CPU + .endianness =3D IIO_CPU, }, }; =20 --=20 2.45.1 From nobody Thu Sep 19 01:00:13 2024 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA5AF1A4B39 for ; Wed, 31 Jul 2024 07:05:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722409556; cv=none; b=gy70gAXmHULhVm8j5JLZ9YJbwHWJcTpduffrzW64Fm1SAgP3+ZTWO+00u8Ua+KZDqH1aG/p01198VwUWhP4O82VccQ6daBXw2rOIcGgIMeMlz5KEvkTfEdip2Bhk7pEA6GbpVgpukkh+gP4rZVeUmNHEPaNl2QTgD+44epAOjYo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722409556; c=relaxed/simple; bh=9dGPkiTFYDkEvhn/NqjG5/RctGzuW49L9Sh3Gg5iz5U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=muCs6nOepaxKFPHywbcKGaegnOr7K61VKhfuWuLIkiTwkwT/MrZwt3fR8ekARGiIlE1ROgyXvr8egq2Yg2/cv1LqTDnyHo5h1tH50JNdpOd7LqNuW+ccwFtI8T+a9uIlcBSHe/gz0itWdiwtS6997lY3ZtuegOw03vwGf6hWh5k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=uxrpKHHN; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="uxrpKHHN" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-427fc97a88cso35143405e9.0 for ; Wed, 31 Jul 2024 00:05:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1722409553; x=1723014353; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=f8DToPXnh1aWxX7ybAN+wh21IynsQgrWjhcqvmXDduw=; b=uxrpKHHNCklnT9o7EqJWH+cFAYMFeCqj5JPNdUqHn5BI5aDUg5rAXzPEykxPoBaQvd eyWghem1iyb37QTjjEOWwg90OSjoOfjkrMdZ42bP4gBUjic+T2FnmZC+KvoLVwhtL3gE q2o2x4AGjhBp5Js0umVUsXWDJvt7wLhwcgVkvJ6VmVJGSQH0rYpIWdPeollDRV3Fzagr wtI3fVHxvbwgSPClO7m6DyW9Zyul3cjMtgovuCevQ+vzSV4qhpfv9oYMzaS0ME9toHcB fz6Kj/LBX+in8sk8CbAdfGtoeYfLIDm6Tw9zH4tHhWjCXNcqK9kEp7wi45WwGgbOkw+W iR+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722409553; x=1723014353; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f8DToPXnh1aWxX7ybAN+wh21IynsQgrWjhcqvmXDduw=; b=QPMI2pUn1X0TpdQbFU3XGGmTVYKsn1QcGX13Kfkr1ec0RsuQOu1FvNn+sSmLcN5oRU +cPDNz4e+8BKySuVnlgzkc3md9OCvKlIiWqxNiLSYIhZNDv5yLusBIxo4JQwu0u/c02k QKLM7s/LiV8W5OoqHNOax/ZL09zKlVtSoaK/8FBhHEG1Sxp/yj/lDwsNkvtEHYg3vHLj bv1twsfBEUHfkd1VHLvGtG0Omd81R5Ww2eKAlUQzJqN7XArz6bosxMODLByD+TpFU/XZ el64cV5rfRLHUTea61HQBYhJxlc6YgB+Z42Cn3QnItJxotP77B6maI0AKcXkJLxD7tDX tdVA== X-Forwarded-Encrypted: i=1; AJvYcCVnVhVK936biAiyADMlwLV2nzJC23ARFwCvxVeZpH60uaPu0g+wBnlsUJixIKoOc1aI2nFIPhKoUbeXgMFrzaPp7p2ziv7+4N439JNV X-Gm-Message-State: AOJu0YyTTJgY36CXgR2Kw5e9N6Xk09l00lo+4wSI2YV7zGv4eLlj55vK 7fLXNyugX3l4soTuIlJVaH4l8YaeuBCf1I1BzDE3osZB5JHqSWDrnA5qfdrBPb0= X-Google-Smtp-Source: AGHT+IH1GAfFv5sNgUZ04+uyD4pq8HEHaz/JsKPmRVMY/Gl2o8hakRh/+nIMT5w9mIRlMBI4xcfXFg== X-Received: by 2002:a05:600c:4ec9:b0:426:58cb:8ca3 with SMTP id 5b1f17b1804b1-42811d9eda7mr92210285e9.21.1722409553116; Wed, 31 Jul 2024 00:05:53 -0700 (PDT) Received: from [192.168.1.61] (2a02-842a-d52e-6101-6f8f-5617-c4b6-8627.rev.sfr.net. [2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4282b8a2593sm9953215e9.4.2024.07.31.00.05.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jul 2024 00:05:52 -0700 (PDT) From: Julien Stephan Date: Wed, 31 Jul 2024 09:05:45 +0200 Subject: [PATCH v2 4/7] iio: adc: ad7380: prepare driver for single-ended parts support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240731-ad7380-add-single-ended-chips-v2-4-cd63bf05744c@baylibre.com> References: <20240731-ad7380-add-single-ended-chips-v2-0-cd63bf05744c@baylibre.com> In-Reply-To: <20240731-ad7380-add-single-ended-chips-v2-0-cd63bf05744c@baylibre.com> To: Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Lars-Peter Clausen , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Cc: Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Julien Stephan X-Mailer: b4 0.13.0 ad738x family contains single-ended parts that have a 2:1 mux in front of ADC, so the number of IIO channels is different from the number of simultaneous channels that can be sampled. To prepare the support for single-ended parts, introduce a new num_simultaneous_channels variable. For currently supported parts, num_simultaneous_channels is equal to num_channels minus 1 (the timestamps channel) Signed-off-by: Julien Stephan Reviewed-by: David Lechner --- drivers/iio/adc/ad7380.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index 72fece383f72..04cc1ef18131 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -80,6 +80,7 @@ struct ad7380_chip_info { const char *name; const struct iio_chan_spec *channels; unsigned int num_channels; + unsigned int num_simult_channels; const char * const *vcm_supplies; unsigned int num_vcm_supplies; const unsigned long *available_scan_masks; @@ -208,6 +209,7 @@ static const struct ad7380_chip_info ad7380_chip_info = =3D { .name =3D "ad7380", .channels =3D ad7380_channels, .num_channels =3D ARRAY_SIZE(ad7380_channels), + .num_simult_channels =3D 2, .available_scan_masks =3D ad7380_2_channel_scan_masks, .timing_specs =3D &ad7380_timing, }; @@ -216,6 +218,7 @@ static const struct ad7380_chip_info ad7381_chip_info = =3D { .name =3D "ad7381", .channels =3D ad7381_channels, .num_channels =3D ARRAY_SIZE(ad7381_channels), + .num_simult_channels =3D 2, .available_scan_masks =3D ad7380_2_channel_scan_masks, .timing_specs =3D &ad7380_timing, }; @@ -224,6 +227,7 @@ static const struct ad7380_chip_info ad7383_chip_info = =3D { .name =3D "ad7383", .channels =3D ad7383_channels, .num_channels =3D ARRAY_SIZE(ad7383_channels), + .num_simult_channels =3D 2, .vcm_supplies =3D ad7380_2_channel_vcm_supplies, .num_vcm_supplies =3D ARRAY_SIZE(ad7380_2_channel_vcm_supplies), .available_scan_masks =3D ad7380_2_channel_scan_masks, @@ -234,6 +238,7 @@ static const struct ad7380_chip_info ad7384_chip_info = =3D { .name =3D "ad7384", .channels =3D ad7384_channels, .num_channels =3D ARRAY_SIZE(ad7384_channels), + .num_simult_channels =3D 2, .vcm_supplies =3D ad7380_2_channel_vcm_supplies, .num_vcm_supplies =3D ARRAY_SIZE(ad7380_2_channel_vcm_supplies), .available_scan_masks =3D ad7380_2_channel_scan_masks, @@ -244,6 +249,7 @@ static const struct ad7380_chip_info ad7380_4_chip_info= =3D { .name =3D "ad7380-4", .channels =3D ad7380_4_channels, .num_channels =3D ARRAY_SIZE(ad7380_4_channels), + .num_simult_channels =3D 4, .available_scan_masks =3D ad7380_4_channel_scan_masks, .timing_specs =3D &ad7380_4_timing, }; @@ -252,6 +258,7 @@ static const struct ad7380_chip_info ad7381_4_chip_info= =3D { .name =3D "ad7381-4", .channels =3D ad7381_4_channels, .num_channels =3D ARRAY_SIZE(ad7381_4_channels), + .num_simult_channels =3D 4, .available_scan_masks =3D ad7380_4_channel_scan_masks, .timing_specs =3D &ad7380_4_timing, }; @@ -260,6 +267,7 @@ static const struct ad7380_chip_info ad7383_4_chip_info= =3D { .name =3D "ad7383-4", .channels =3D ad7383_4_channels, .num_channels =3D ARRAY_SIZE(ad7383_4_channels), + .num_simult_channels =3D 4, .vcm_supplies =3D ad7380_4_channel_vcm_supplies, .num_vcm_supplies =3D ARRAY_SIZE(ad7380_4_channel_vcm_supplies), .available_scan_masks =3D ad7380_4_channel_scan_masks, @@ -270,6 +278,7 @@ static const struct ad7380_chip_info ad7384_4_chip_info= =3D { .name =3D "ad7384-4", .channels =3D ad7384_4_channels, .num_channels =3D ARRAY_SIZE(ad7384_4_channels), + .num_simult_channels =3D 4, .vcm_supplies =3D ad7380_4_channel_vcm_supplies, .num_vcm_supplies =3D ARRAY_SIZE(ad7380_4_channel_vcm_supplies), .available_scan_masks =3D ad7380_4_channel_scan_masks, @@ -407,7 +416,7 @@ static void ad7380_update_xfers(struct ad7380_state *st, */ st->xfer[1].bits_per_word =3D scan_type->realbits; st->xfer[1].len =3D BITS_TO_BYTES(scan_type->storagebits) * - (st->chip_info->num_channels - 1); + st->chip_info->num_simult_channels; } =20 static int ad7380_triggered_buffer_preenable(struct iio_dev *indio_dev) --=20 2.45.1 From nobody Thu Sep 19 01:00:13 2024 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 565A41A6187 for ; Wed, 31 Jul 2024 07:05:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722409560; cv=none; b=XFokxR84KxBzmmsxQ4gxGrBSjAomh/Boh1PVHY+jQcCHsoKs1kJYXKH0faUAnq6RBEFMH7PFU/nMdE6XplpwpDUbwapbhiKbmtMwg91Wat3M7s/K+0TtbPyAP3zem/W7AqM0uuHURSqTOGgSmtn+7FxAl8ncyc/ScU1LVNt8vaw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722409560; c=relaxed/simple; bh=N+VAsoVMf0kYaOmZRtqmOTy82UerzihLlHhBrWb2ieY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oFpUyLEq3NgAA5kJZwGL8Xf++WFDnh1QKibJ8wJ4dQmIj10WxeTnPSOuQC8dR6quALEapGnkWAcoEaXYhV2G9TX5+B7AUcsstrmZyfmb1LNw61RLngAv5mpSDux+rRZeSYAob5m+0NCcWuUTjALLBwNQRheQ+//mJU22h8jSDPI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=ON43Mv3f; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="ON43Mv3f" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-427b1d4da32so3240555e9.0 for ; Wed, 31 Jul 2024 00:05:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1722409555; x=1723014355; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=b3bgQ57CHVc0q9CRE3lnl6yM7nPtiuF3hPunbjRQ+tE=; b=ON43Mv3fL0GsOgYV4nI8MiB8r1g8KgNvd/Rn3Ew3q70xFLVPkqduK9BK59BfrRUOy/ T96PQEn7yXOTopOCdaVNLO4GtkFG5xQmwIlnM/3gXcmyldiGEbhsGDCza8lFibdReUFS XgLU3QbAwY95TsPB4ZMUULgN57Zs9gC16vav2YjHtiuk9KQQrdmWo0NDKBWCqjN73/7J Pz2yeVVAh7An1CT2JzHqizqVMt1+vZk3SljGNM9mA+9ZFFl3g29zHuET+3WMLOvGoveI 0zqRJe0q4qVGllbpJiBVozD2QFHXXQs7IT+ZdgIRONa9I3kk9p0d+Qzoq3iFeKY6U6Y0 ZMfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722409555; x=1723014355; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b3bgQ57CHVc0q9CRE3lnl6yM7nPtiuF3hPunbjRQ+tE=; b=ex47r8Hwa537SS2hx99z6x9dqjaGqKAYalRVHN0toTRKHvVNe1jcy6CtZAgGSz6IEO 6zH6esjFdo8pFAZ7cVYIAQjWygJMHFEqKPmtP9oDRAdPJfIfKuxilO42WByTn8udo98j p6V/vl7/iaPhJaDmkjOCNn5ZEM7I0dHF2RhQxlHC2Yocfx9eNe1HB186/8HyDkIx9UoS R+EkpeoN5VTd1NeJhE/YDOAR7ZsSkvnkd4U2Qf6Ac8VGWimVx8KtjzMFzOOZkyPCZQ4I walU/x/VRqkvaJe6eyhIGFHQcbdiUNxTLlMrrwPc37/OlEuR7ADRmv8iFnfUZrXVoNOH PQwQ== X-Forwarded-Encrypted: i=1; AJvYcCUprdxB0QvOghe6isST3bElnIgsq3o+J4xW1eLuO6thJ9c9pJYxVnMJwU4zgMOnhDhlix3F+drOK2dNndgaZ8kc/aHFyAfx4GyneBw7 X-Gm-Message-State: AOJu0Yz6EHSFL6KAZEdoRD6dfktW53Aiw5WA9baJdctawzxDcfeZZTbd n96xXuq4rp5wcMyy/KL5gEP+CJj0csxds/utuL/W5hiRl6Cn5p3VUM14x3YTl18= X-Google-Smtp-Source: AGHT+IHaNgJ9qJUDwpfCS2bmF3oSur6kZVjB8NRZNOTRFu6mqp0yrMIwSz+MHZqNTQXGtQuHInyg3Q== X-Received: by 2002:a05:6000:d01:b0:362:4679:b5a with SMTP id ffacd0b85a97d-36b8c8e99ebmr2991645f8f.16.1722409554646; Wed, 31 Jul 2024 00:05:54 -0700 (PDT) Received: from [192.168.1.61] (2a02-842a-d52e-6101-6f8f-5617-c4b6-8627.rev.sfr.net. [2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4282b8a2593sm9953215e9.4.2024.07.31.00.05.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jul 2024 00:05:54 -0700 (PDT) From: Julien Stephan Date: Wed, 31 Jul 2024 09:05:46 +0200 Subject: [PATCH v2 5/7] iio: adc: ad7380: add support for single-ended parts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240731-ad7380-add-single-ended-chips-v2-5-cd63bf05744c@baylibre.com> References: <20240731-ad7380-add-single-ended-chips-v2-0-cd63bf05744c@baylibre.com> In-Reply-To: <20240731-ad7380-add-single-ended-chips-v2-0-cd63bf05744c@baylibre.com> To: Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Lars-Peter Clausen , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Cc: Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Julien Stephan X-Mailer: b4 0.13.0 Adding ad7386/7/8 (16/14/12 bits) unsigned, dual simultaneous sampling, single-ended compatible parts, and the corresponding ad7386-4/7-4/8-4 4 channels. These parts have a 2:1 multiplexer in front of each ADC. They also include additional configuration registers that allow for either manual selection or automatic switching (sequencer mode), of the multiplexer inputs. This commit focus on integrating manual selection. Sequencer mode will be implemented later. From an IIO point of view, all inputs are exported, i.e ad7386/7/8 export 4 channels and ad7386-4/7-4/8-4 export 8 channels. Inputs AinX0 of multiplexers correspond to the first half of IIO channels (i.e 0-1 or 0-3) and inputs AinX1 correspond to second half (i.e 2-3 or 4-7). Example for AD7386/7/8 (2 channels parts): IIO | AD7386/7/8 | +---------------------------- | | _____ ______ | | | | | | voltage0 | AinA0 --|--->| | | | | | | mux |----->| ADCA |--- voltage2 | AinA1 --|--->| | | | | | |_____| |_____ | | | _____ ______ | | | | | | voltage1 | AinB0 --|--->| | | | | | | mux |----->| ADCB |--- voltage3 | AinB1 --|--->| | | | | | |_____| |______| | | | +---------------------------- When switching channel, the ADC require an additional settling time. According to the datasheet, data is valid on the third CS low. We already have an extra toggle before each read (either direct reads or buffered reads) to sample correct data, so we just add a single CS toggle at the end of the register write. Signed-off-by: Julien Stephan Reviewed-by: David Lechner --- drivers/iio/adc/ad7380.c | 351 +++++++++++++++++++++++++++++++++++++++++--= ---- 1 file changed, 309 insertions(+), 42 deletions(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index 04cc1ef18131..820df04b9eb2 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -8,9 +8,11 @@ * Datasheets of supported parts: * ad7380/1 : https://www.analog.com/media/en/technical-documentation/data= -sheets/AD7380-7381.pdf * ad7383/4 : https://www.analog.com/media/en/technical-documentation/data= -sheets/ad7383-7384.pdf + * ad7386/7/8 : https://www.analog.com/media/en/technical-documentation/da= ta-sheets/AD7386-7387-7388.pdf * ad7380-4 : https://www.analog.com/media/en/technical-documentation/data= -sheets/ad7380-4.pdf * ad7381-4 : https://www.analog.com/media/en/technical-documentation/data= -sheets/ad7381-4.pdf * ad7383/4-4 : https://www.analog.com/media/en/technical-documentation/da= ta-sheets/ad7383-4-ad7384-4.pdf + * ad7386/7/8-4 : https://www.analog.com/media/en/technical-documentation/= data-sheets/ad7386-4-7387-4-7388-4.pdf */ =20 #include @@ -49,6 +51,7 @@ #define AD7380_REG_ADDR_ALERT_LOW_TH 0x4 #define AD7380_REG_ADDR_ALERT_HIGH_TH 0x5 =20 +#define AD7380_CONFIG1_CH BIT(11) #define AD7380_CONFIG1_OS_MODE BIT(9) #define AD7380_CONFIG1_OSR GENMASK(8, 6) #define AD7380_CONFIG1_CRC_W BIT(5) @@ -81,6 +84,7 @@ struct ad7380_chip_info { const struct iio_chan_spec *channels; unsigned int num_channels; unsigned int num_simult_channels; + bool has_mux; const char * const *vcm_supplies; unsigned int num_vcm_supplies; const unsigned long *available_scan_masks; @@ -92,8 +96,24 @@ enum { AD7380_SCAN_TYPE_RESOLUTION_BOOST, }; =20 -/* Extended scan types for 14-bit chips. */ -static const struct iio_scan_type ad7380_scan_type_14[] =3D { +/* Extended scan types for 12-bit unsigned chips. */ +static const struct iio_scan_type ad7380_scan_type_12_u[] =3D { + [AD7380_SCAN_TYPE_NORMAL] =3D { + .sign =3D 'u', + .realbits =3D 12, + .storagebits =3D 16, + .endianness =3D IIO_CPU, + }, + [AD7380_SCAN_TYPE_RESOLUTION_BOOST] =3D { + .sign =3D 'u', + .realbits =3D 14, + .storagebits =3D 16, + .endianness =3D IIO_CPU, + }, +}; + +/* Extended scan types for 14-bit signed chips. */ +static const struct iio_scan_type ad7380_scan_type_14_s[] =3D { [AD7380_SCAN_TYPE_NORMAL] =3D { .sign =3D 's', .realbits =3D 14, @@ -108,8 +128,24 @@ static const struct iio_scan_type ad7380_scan_type_14[= ] =3D { }, }; =20 -/* Extended scan types for 16-bit chips. */ -static const struct iio_scan_type ad7380_scan_type_16[] =3D { +/* Extended scan types for 14-bit unsigned chips. */ +static const struct iio_scan_type ad7380_scan_type_14_u[] =3D { + [AD7380_SCAN_TYPE_NORMAL] =3D { + .sign =3D 'u', + .realbits =3D 14, + .storagebits =3D 16, + .endianness =3D IIO_CPU, + }, + [AD7380_SCAN_TYPE_RESOLUTION_BOOST] =3D { + .sign =3D 'u', + .realbits =3D 16, + .storagebits =3D 16, + .endianness =3D IIO_CPU, + }, +}; + +/* Extended scan types for 16-bit signed_chips. */ +static const struct iio_scan_type ad7380_scan_type_16_s[] =3D { [AD7380_SCAN_TYPE_NORMAL] =3D { .sign =3D 's', .realbits =3D 16, @@ -124,50 +160,87 @@ static const struct iio_scan_type ad7380_scan_type_16= [] =3D { }, }; =20 -#define AD7380_CHANNEL(index, bits, diff) { \ - .type =3D IIO_VOLTAGE, \ - .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ - ((diff) ? 0 : BIT(IIO_CHAN_INFO_OFFSET)), \ - .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE) | \ - BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ - .info_mask_shared_by_type_available =3D \ - BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ - .indexed =3D 1, \ - .differential =3D (diff), \ - .channel =3D (diff) ? (2 * (index)) : (index), \ - .channel2 =3D (diff) ? (2 * (index) + 1) : 0, \ - .scan_index =3D (index), \ - .has_ext_scan_type =3D 1, \ - .ext_scan_type =3D ad7380_scan_type_##bits, \ - .num_ext_scan_type =3D ARRAY_SIZE(ad7380_scan_type_##bits),\ +/* Extended scan types for 16-bit unsigned chips. */ +static const struct iio_scan_type ad7380_scan_type_16_u[] =3D { + [AD7380_SCAN_TYPE_NORMAL] =3D { + .sign =3D 'u', + .realbits =3D 16, + .storagebits =3D 16, + .endianness =3D IIO_CPU, + }, + [AD7380_SCAN_TYPE_RESOLUTION_BOOST] =3D { + .sign =3D 'u', + .realbits =3D 18, + .storagebits =3D 32, + .endianness =3D IIO_CPU, + }, +}; + +#define AD7380_CHANNEL(index, bits, diff, sign) { \ + .type =3D IIO_VOLTAGE, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ + ((diff) ? 0 : BIT(IIO_CHAN_INFO_OFFSET)), \ + .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .info_mask_shared_by_type_available =3D \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .indexed =3D 1, \ + .differential =3D (diff), \ + .channel =3D (diff) ? (2 * (index)) : (index), \ + .channel2 =3D (diff) ? (2 * (index) + 1) : 0, \ + .scan_index =3D (index), \ + .has_ext_scan_type =3D 1, \ + .ext_scan_type =3D ad7380_scan_type_##bits##_##sign, \ + .num_ext_scan_type =3D ARRAY_SIZE(ad7380_scan_type_##bits##_##sign), \ } =20 -#define DEFINE_AD7380_2_CHANNEL(name, bits, diff) \ +#define DEFINE_AD7380_2_CHANNEL(name, bits, diff, sign) \ static const struct iio_chan_spec name[] =3D { \ - AD7380_CHANNEL(0, bits, diff), \ - AD7380_CHANNEL(1, bits, diff), \ + AD7380_CHANNEL(0, bits, diff, sign), \ + AD7380_CHANNEL(1, bits, diff, sign), \ IIO_CHAN_SOFT_TIMESTAMP(2), \ } =20 -#define DEFINE_AD7380_4_CHANNEL(name, bits, diff) \ +#define DEFINE_AD7380_4_CHANNEL(name, bits, diff, sign) \ static const struct iio_chan_spec name[] =3D { \ - AD7380_CHANNEL(0, bits, diff), \ - AD7380_CHANNEL(1, bits, diff), \ - AD7380_CHANNEL(2, bits, diff), \ - AD7380_CHANNEL(3, bits, diff), \ + AD7380_CHANNEL(0, bits, diff, sign), \ + AD7380_CHANNEL(1, bits, diff, sign), \ + AD7380_CHANNEL(2, bits, diff, sign), \ + AD7380_CHANNEL(3, bits, diff, sign), \ IIO_CHAN_SOFT_TIMESTAMP(4), \ } =20 +#define DEFINE_AD7380_8_CHANNEL(name, bits, diff, sign) \ +static const struct iio_chan_spec name[] =3D { \ + AD7380_CHANNEL(0, bits, diff, sign), \ + AD7380_CHANNEL(1, bits, diff, sign), \ + AD7380_CHANNEL(2, bits, diff, sign), \ + AD7380_CHANNEL(3, bits, diff, sign), \ + AD7380_CHANNEL(4, bits, diff, sign), \ + AD7380_CHANNEL(5, bits, diff, sign), \ + AD7380_CHANNEL(6, bits, diff, sign), \ + AD7380_CHANNEL(7, bits, diff, sign), \ + IIO_CHAN_SOFT_TIMESTAMP(8), \ +} + /* fully differential */ -DEFINE_AD7380_2_CHANNEL(ad7380_channels, 16, 1); -DEFINE_AD7380_2_CHANNEL(ad7381_channels, 14, 1); -DEFINE_AD7380_4_CHANNEL(ad7380_4_channels, 16, 1); -DEFINE_AD7380_4_CHANNEL(ad7381_4_channels, 14, 1); +DEFINE_AD7380_2_CHANNEL(ad7380_channels, 16, 1, s); +DEFINE_AD7380_2_CHANNEL(ad7381_channels, 14, 1, s); +DEFINE_AD7380_4_CHANNEL(ad7380_4_channels, 16, 1, s); +DEFINE_AD7380_4_CHANNEL(ad7381_4_channels, 14, 1, s); /* pseudo differential */ -DEFINE_AD7380_2_CHANNEL(ad7383_channels, 16, 0); -DEFINE_AD7380_2_CHANNEL(ad7384_channels, 14, 0); -DEFINE_AD7380_4_CHANNEL(ad7383_4_channels, 16, 0); -DEFINE_AD7380_4_CHANNEL(ad7384_4_channels, 14, 0); +DEFINE_AD7380_2_CHANNEL(ad7383_channels, 16, 0, s); +DEFINE_AD7380_2_CHANNEL(ad7384_channels, 14, 0, s); +DEFINE_AD7380_4_CHANNEL(ad7383_4_channels, 16, 0, s); +DEFINE_AD7380_4_CHANNEL(ad7384_4_channels, 14, 0, s); + +/* Single ended */ +DEFINE_AD7380_4_CHANNEL(ad7386_channels, 16, 0, u); +DEFINE_AD7380_4_CHANNEL(ad7387_channels, 14, 0, u); +DEFINE_AD7380_4_CHANNEL(ad7388_channels, 12, 0, u); +DEFINE_AD7380_8_CHANNEL(ad7386_4_channels, 16, 0, u); +DEFINE_AD7380_8_CHANNEL(ad7387_4_channels, 14, 0, u); +DEFINE_AD7380_8_CHANNEL(ad7388_4_channels, 12, 0, u); =20 static const char * const ad7380_2_channel_vcm_supplies[] =3D { "aina", "ainb", @@ -188,6 +261,48 @@ static const unsigned long ad7380_4_channel_scan_masks= [] =3D { 0 }; =20 +/* + * Single ended parts have a 2:1 multiplexer in front of each ADC. + * + * From an IIO point of view, all inputs are exported, i.e ad7386/7/8 + * export 4 channels and ad7386-4/7-4/8-4 export 8 channels. + * + * Inputs AinX0 of multiplexers correspond to the first half of IIO channe= ls + * (i.e 0-1 or 0-3) and inputs AinX1 correspond to second half (i.e 2-3 or + * 4-7). Example for AD7386/7/8 (2 channels parts): + * + * IIO | AD7386/7/8 + * | +---------------------------- + * | | _____ ______ + * | | | | | | + * voltage0 | AinA0 --|--->| | | | + * | | | mux |----->| ADCA |--- + * voltage2 | AinA1 --|--->| | | | + * | | |_____| |_____ | + * | | _____ ______ + * | | | | | | + * voltage1 | AinB0 --|--->| | | | + * | | | mux |----->| ADCB |--- + * voltage3 | AinB1 --|--->| | | | + * | | |_____| |______| + * | | + * | +---------------------------- + * + * Since this is simultaneous sampling for AinX0 OR AinX1 we have two sepa= rate + * scan masks. + */ +static const unsigned long ad7380_2x2_channel_scan_masks[] =3D { + GENMASK(1, 0), + GENMASK(3, 2), + 0 +}; + +static const unsigned long ad7380_2x4_channel_scan_masks[] =3D { + GENMASK(3, 0), + GENMASK(7, 4), + 0 +}; + static const struct ad7380_timing_specs ad7380_timing =3D { .t_csh_ns =3D 10, }; @@ -245,6 +360,36 @@ static const struct ad7380_chip_info ad7384_chip_info = =3D { .timing_specs =3D &ad7380_timing, }; =20 +static const struct ad7380_chip_info ad7386_chip_info =3D { + .name =3D "ad7386", + .channels =3D ad7386_channels, + .num_channels =3D ARRAY_SIZE(ad7386_channels), + .num_simult_channels =3D 2, + .has_mux =3D true, + .available_scan_masks =3D ad7380_2x2_channel_scan_masks, + .timing_specs =3D &ad7380_timing, +}; + +static const struct ad7380_chip_info ad7387_chip_info =3D { + .name =3D "ad7387", + .channels =3D ad7387_channels, + .num_channels =3D ARRAY_SIZE(ad7387_channels), + .num_simult_channels =3D 2, + .has_mux =3D true, + .available_scan_masks =3D ad7380_2x2_channel_scan_masks, + .timing_specs =3D &ad7380_timing, +}; + +static const struct ad7380_chip_info ad7388_chip_info =3D { + .name =3D "ad7388", + .channels =3D ad7388_channels, + .num_channels =3D ARRAY_SIZE(ad7388_channels), + .num_simult_channels =3D 2, + .has_mux =3D true, + .available_scan_masks =3D ad7380_2x2_channel_scan_masks, + .timing_specs =3D &ad7380_timing, +}; + static const struct ad7380_chip_info ad7380_4_chip_info =3D { .name =3D "ad7380-4", .channels =3D ad7380_4_channels, @@ -285,12 +430,43 @@ static const struct ad7380_chip_info ad7384_4_chip_in= fo =3D { .timing_specs =3D &ad7380_4_timing, }; =20 +static const struct ad7380_chip_info ad7386_4_chip_info =3D { + .name =3D "ad7386-4", + .channels =3D ad7386_4_channels, + .num_channels =3D ARRAY_SIZE(ad7386_4_channels), + .num_simult_channels =3D 4, + .has_mux =3D true, + .available_scan_masks =3D ad7380_2x4_channel_scan_masks, + .timing_specs =3D &ad7380_4_timing, +}; + +static const struct ad7380_chip_info ad7387_4_chip_info =3D { + .name =3D "ad7387-4", + .channels =3D ad7387_4_channels, + .num_channels =3D ARRAY_SIZE(ad7387_4_channels), + .num_simult_channels =3D 4, + .has_mux =3D true, + .available_scan_masks =3D ad7380_2x4_channel_scan_masks, + .timing_specs =3D &ad7380_4_timing, +}; + +static const struct ad7380_chip_info ad7388_4_chip_info =3D { + .name =3D "ad7388-4", + .channels =3D ad7388_4_channels, + .num_channels =3D ARRAY_SIZE(ad7388_4_channels), + .num_simult_channels =3D 4, + .has_mux =3D true, + .available_scan_masks =3D ad7380_2x4_channel_scan_masks, + .timing_specs =3D &ad7380_4_timing, +}; + struct ad7380_state { const struct ad7380_chip_info *chip_info; struct spi_device *spi; struct regmap *regmap; unsigned int oversampling_ratio; bool resolution_boost_enabled; + unsigned int ch; unsigned int vref_mv; unsigned int vcm_mv[MAX_NUM_CHANNELS]; /* xfers, message an buffer for reading sample data */ @@ -388,6 +564,43 @@ static int ad7380_debugfs_reg_access(struct iio_dev *i= ndio_dev, u32 reg, unreachable(); } =20 +/* + * When switching channel, the ADC require an additional settling time. + * According to the datasheet, data is value on the third CS low. We alrea= dy + * have an extra toggle before each read (either direct reads or buffered = reads) + * to sample correct data, so we just add a single CS toggle at the end of= the + * register write. + */ +static int ad7380_set_ch(struct ad7380_state *st, unsigned int ch) +{ + struct spi_transfer xfer =3D { + .delay =3D { + .value =3D T_CONVERT_NS, + .unit =3D SPI_DELAY_UNIT_NSECS, + } + }; + int ret; + + if (st->ch =3D=3D ch) + return 0; + + ret =3D regmap_update_bits(st->regmap, + AD7380_REG_ADDR_CONFIG1, + AD7380_CONFIG1_CH, + FIELD_PREP(AD7380_CONFIG1_CH, ch)); + + if (ret) + return ret; + + st->ch =3D ch; + + if (st->oversampling_ratio > 1) + xfer.delay.value =3D T_CONVERT_0_NS + + T_CONVERT_X_NS * (st->oversampling_ratio - 1); + + return spi_sync_transfer(st->spi, &xfer, 1); +} + /** * ad7380_update_xfers - update the SPI transfers base on the current scan= type * @st: device instance specific state @@ -432,6 +645,24 @@ static int ad7380_triggered_buffer_preenable(struct ii= o_dev *indio_dev) if (IS_ERR(scan_type)) return PTR_ERR(scan_type); =20 + if (st->chip_info->has_mux) { + unsigned int index; + int ret; + + /* + * Depending on the requested scan_mask and current state, + * we need to change CH bit to sample correct data. + */ + ret =3D iio_active_scan_mask_index(indio_dev); + if (ret < 0) + return ret; + + index =3D ret; + ret =3D ad7380_set_ch(st, index); + if (ret) + return ret; + } + ad7380_update_xfers(st, scan_type); =20 return spi_optimize_message(st->spi, &st->msg); @@ -474,20 +705,43 @@ static irqreturn_t ad7380_trigger_handler(int irq, vo= id *p) static int ad7380_read_direct(struct ad7380_state *st, unsigned int scan_i= ndex, const struct iio_scan_type *scan_type, int *val) { + unsigned int index =3D scan_index; int ret; =20 + if (st->chip_info->has_mux) { + unsigned int ch =3D 0; + + if (index >=3D st->chip_info->num_simult_channels) { + index -=3D st->chip_info->num_simult_channels; + ch =3D 1; + } + + ret =3D ad7380_set_ch(st, ch); + if (ret) + return ret; + } + ad7380_update_xfers(st, scan_type); =20 ret =3D spi_sync(st->spi, &st->msg); if (ret < 0) return ret; =20 - if (scan_type->storagebits > 16) - *val =3D sign_extend32(*(u32 *)(st->scan_data + 4 * scan_index), - scan_type->realbits - 1); - else - *val =3D sign_extend32(*(u16 *)(st->scan_data + 2 * scan_index), - scan_type->realbits - 1); + if (scan_type->storagebits > 16) { + if (scan_type->sign =3D=3D 's') + *val =3D sign_extend32(*(u32 *)(st->scan_data + 4 * index), + scan_type->realbits - 1); + else + *val =3D *(u32 *)(st->scan_data + 4 * index) & + GENMASK(scan_type->realbits - 1, 0); + } else { + if (scan_type->sign =3D=3D 's') + *val =3D sign_extend32(*(u16 *)(st->scan_data + 2 * index), + scan_type->realbits - 1); + else + *val =3D *(u16 *)(st->scan_data + 2 * index) & + GENMASK(scan_type->realbits - 1, 0); + } =20 return IIO_VAL_INT; } @@ -664,6 +918,7 @@ static int ad7380_init(struct ad7380_state *st, struct = regulator *vref) =20 /* This is the default value after reset. */ st->oversampling_ratio =3D 1; + st->ch =3D 0; =20 /* SPI 1-wire mode */ return regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, @@ -807,10 +1062,16 @@ static const struct of_device_id ad7380_of_match_tab= le[] =3D { { .compatible =3D "adi,ad7381", .data =3D &ad7381_chip_info }, { .compatible =3D "adi,ad7383", .data =3D &ad7383_chip_info }, { .compatible =3D "adi,ad7384", .data =3D &ad7384_chip_info }, + { .compatible =3D "adi,ad7386", .data =3D &ad7386_chip_info }, + { .compatible =3D "adi,ad7387", .data =3D &ad7387_chip_info }, + { .compatible =3D "adi,ad7388", .data =3D &ad7388_chip_info }, { .compatible =3D "adi,ad7380-4", .data =3D &ad7380_4_chip_info }, { .compatible =3D "adi,ad7381-4", .data =3D &ad7381_4_chip_info }, { .compatible =3D "adi,ad7383-4", .data =3D &ad7383_4_chip_info }, { .compatible =3D "adi,ad7384-4", .data =3D &ad7384_4_chip_info }, + { .compatible =3D "adi,ad7386-4", .data =3D &ad7386_4_chip_info }, + { .compatible =3D "adi,ad7387-4", .data =3D &ad7387_4_chip_info }, + { .compatible =3D "adi,ad7388-4", .data =3D &ad7388_4_chip_info }, { } }; =20 @@ -819,10 +1080,16 @@ static const struct spi_device_id ad7380_id_table[] = =3D { { "ad7381", (kernel_ulong_t)&ad7381_chip_info }, { "ad7383", (kernel_ulong_t)&ad7383_chip_info }, { "ad7384", (kernel_ulong_t)&ad7384_chip_info }, + { "ad7386", (kernel_ulong_t)&ad7386_chip_info }, + { "ad7387", (kernel_ulong_t)&ad7387_chip_info }, + { "ad7388", (kernel_ulong_t)&ad7388_chip_info }, { "ad7380-4", (kernel_ulong_t)&ad7380_4_chip_info }, { "ad7381-4", (kernel_ulong_t)&ad7381_4_chip_info }, { "ad7383-4", (kernel_ulong_t)&ad7383_4_chip_info }, { "ad7384-4", (kernel_ulong_t)&ad7384_4_chip_info }, + { "ad7386-4", (kernel_ulong_t)&ad7386_4_chip_info }, + { "ad7387-4", (kernel_ulong_t)&ad7387_4_chip_info }, + { "ad7388-4", (kernel_ulong_t)&ad7388_4_chip_info }, { } }; MODULE_DEVICE_TABLE(spi, ad7380_id_table); --=20 2.45.1 From nobody Thu Sep 19 01:00:13 2024 Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6EDD1A76C4 for ; Wed, 31 Jul 2024 07:05:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722409562; cv=none; b=VwSSDAHlihPMe+xnuoiHuYx09DNnpuFzS1W/hrLIA3DZOmevJebUBHa3gY1Cvj8cXUZUZobic8Lyo85ayi6QPNjU3uWO509V4cVT9XE6xZ0xJOMWzDggjVdeT8rcShvl5NuWFFQHjt1CwCqWi/OHjdHbqzzDf8tSqwqakD2ml8A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722409562; c=relaxed/simple; bh=goLFX5mJFdEUFTzNMXZVHME3es4ynEqHdezi548BWHs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VFlxBneHjZeYViiH07VW5JjBpNAiS4z7yhcDxpiPsc1nCKs3SsL8ByyGhAi5HSrwsC9K2TJAvsQPWqA5iF3guQA5noDZqOL0+3ulHVaK0FKSKFN4mEIOGCefF7ch0ZLejL9Wz6nih2QmdVa6qK1yPpSN5LyVum7VrLdXz0kc5TI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=WMUlA8xb; arc=none smtp.client-ip=209.85.167.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="WMUlA8xb" Received: by mail-lf1-f54.google.com with SMTP id 2adb3069b0e04-52f00ad303aso8763334e87.2 for ; Wed, 31 Jul 2024 00:05:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1722409557; x=1723014357; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=oHaY16vQQryIhH+k5EF4MPXtMPGv2rNQp9CaSsAD0ko=; b=WMUlA8xbVlmLhM3B1O/Cmf7wScKKabqSD9ZGjXR0oLAl90nb6UZtkv4G8zRbqZ2YHt y1bsauMlkvbDs7sIo0cCw2vRGNPTL2kj1xwc/btZOpUFZgbAq4UQuP97z5LbziZDYAyb Kr/pS6uAZ4M6a9p4g1A+AmTiVABIXgieFrem/pioheAA3TBlgXBWAdn7hZ+VPXx5fR4Q P+plAX+3sp9L7BRPf+aNwQMFuadRjQOWRJs8ReBns+XHh5T+zcW8ignEbhsK6XUV3ajU ZFICheMm2yOKoF4Z6xe+MB/CIoXyxvMAj0UIzYOuQP7T1eD7ZW7YZJ7RU8Mrct40jS/9 lvYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722409557; x=1723014357; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oHaY16vQQryIhH+k5EF4MPXtMPGv2rNQp9CaSsAD0ko=; b=LVaPN1EIaWXsqSitQPJOUPJWFObSfq2zqyvLjGOG9ktO3G1QpptycHH6yGhtoNCbV8 ZuaRIgHTZE/rDrvLfnGsdOFH5MbcmZ0nergcpl/lbwqQ4vrMjjku+mj1ZLc/YyXm2WpF LFgb86GpbSly26HNPhc+T9zpY2jT9F+bWc0RLdV7Cir8ALBXnRCr5bjlyjwY6B5p+bye m83D/1+3kx8myzlcXZPsc3B8CsO8SwV1KlQoj0Uwi1Q9OuSIuZqRh6z60KYOpKXSeJ8r gxgSE7e0gYVUnnj3XFMKRbd7S9VjIP9X4WNHUXXzZHImxrq1fhGDtGYHtduSQbW2AcQ1 eolA== X-Forwarded-Encrypted: i=1; AJvYcCVlBervFYakwU32vgw463sF16GFjUTwIdckPFUA7atz2OHeYFdTeqIbqrd+RSUfbCRFEaEvP6K5x4CTBjYQw0dQOuVJ+CEFglQxOHPL X-Gm-Message-State: AOJu0YwcTTJ1CVt9PTBwSrLpMjFxfpZ5bpECrzr1abE0R4Nwj6id+rVX n8/1/DVl5pTtMoj6SMRvGfqCRVjd1XPt3GMpL8QtFrHZ8U1t3oX0zU7eqjezZQg= X-Google-Smtp-Source: AGHT+IFgysceqqUPLxcKuas2k9QPG9beRNBgeaGQsYtagKcy+ArO1e5R0azF7E/AbehHI/U/HCFReg== X-Received: by 2002:a05:6512:68f:b0:52c:ce28:82c8 with SMTP id 2adb3069b0e04-5309b2c54demr11138493e87.52.1722409556557; Wed, 31 Jul 2024 00:05:56 -0700 (PDT) Received: from [192.168.1.61] (2a02-842a-d52e-6101-6f8f-5617-c4b6-8627.rev.sfr.net. [2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4282b8a2593sm9953215e9.4.2024.07.31.00.05.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jul 2024 00:05:56 -0700 (PDT) From: Julien Stephan Date: Wed, 31 Jul 2024 09:05:47 +0200 Subject: [PATCH v2 6/7] iio: adc: ad7380: enable sequencer for single-ended parts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240731-ad7380-add-single-ended-chips-v2-6-cd63bf05744c@baylibre.com> References: <20240731-ad7380-add-single-ended-chips-v2-0-cd63bf05744c@baylibre.com> In-Reply-To: <20240731-ad7380-add-single-ended-chips-v2-0-cd63bf05744c@baylibre.com> To: Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Lars-Peter Clausen , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Cc: Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Julien Stephan X-Mailer: b4 0.13.0 ad7386/7/8(-4) single-ended parts have a 2:1 mux in front of each ADC. From an IIO point of view, all inputs are exported, i.e ad7386/7/8 export 4 channels and ad7386-4/7-4/8-4 export 8 channels. First inputs of muxes correspond to the first half of IIO channels (i.e 0-1 or 0-3) and second inputs correspond to second half (i.e 2-3 or 4-7) Currently, the driver supports only sampling first half OR second half of the IIO channels. To enable sampling all channels simultaneously, these parts have an internal sequencer that automatically cycles through the mux entries. When enabled, the maximum throughput is divided by two. Moreover, the ADCs need additional settling time, so we add an extra CS toggle to correctly propagate setting, and an additional spi transfer to read the second half. Signed-off-by: Julien Stephan Reviewed-by: David Lechner --- drivers/iio/adc/ad7380.c | 175 +++++++++++++++++++++++++++++++++++--------= ---- 1 file changed, 130 insertions(+), 45 deletions(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index 820df04b9eb2..e8bddfb0d07d 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -33,7 +33,7 @@ #include #include =20 -#define MAX_NUM_CHANNELS 4 +#define MAX_NUM_CHANNELS 8 /* 2.5V internal reference voltage */ #define AD7380_INTERNAL_REF_MV 2500 =20 @@ -52,6 +52,7 @@ #define AD7380_REG_ADDR_ALERT_HIGH_TH 0x5 =20 #define AD7380_CONFIG1_CH BIT(11) +#define AD7380_CONFIG1_SEQ BIT(10) #define AD7380_CONFIG1_OS_MODE BIT(9) #define AD7380_CONFIG1_OSR GENMASK(8, 6) #define AD7380_CONFIG1_CRC_W BIT(5) @@ -290,16 +291,28 @@ static const unsigned long ad7380_4_channel_scan_mask= s[] =3D { * * Since this is simultaneous sampling for AinX0 OR AinX1 we have two sepa= rate * scan masks. + * When sequencer mode is enabled, chip automatically cycles through + * AinX0 and AinX1 channels. From an IIO point of view, we ca enable all + * channels, at the cost of an extra read, thus dividing the maximum rate = by + * two. */ +enum { + AD7380_SCAN_MASK_CH_0, + AD7380_SCAN_MASK_CH_1, + AD7380_SCAN_MASK_SEQ, +}; + static const unsigned long ad7380_2x2_channel_scan_masks[] =3D { - GENMASK(1, 0), - GENMASK(3, 2), + [AD7380_SCAN_MASK_CH_0] =3D GENMASK(1, 0), + [AD7380_SCAN_MASK_CH_1] =3D GENMASK(3, 2), + [AD7380_SCAN_MASK_SEQ] =3D GENMASK(3, 0), 0 }; =20 static const unsigned long ad7380_2x4_channel_scan_masks[] =3D { - GENMASK(3, 0), - GENMASK(7, 4), + [AD7380_SCAN_MASK_CH_0] =3D GENMASK(3, 0), + [AD7380_SCAN_MASK_CH_1] =3D GENMASK(7, 4), + [AD7380_SCAN_MASK_SEQ] =3D GENMASK(7, 0), 0 }; =20 @@ -467,11 +480,14 @@ struct ad7380_state { unsigned int oversampling_ratio; bool resolution_boost_enabled; unsigned int ch; + bool seq; unsigned int vref_mv; unsigned int vcm_mv[MAX_NUM_CHANNELS]; /* xfers, message an buffer for reading sample data */ - struct spi_transfer xfer[2]; - struct spi_message msg; + struct spi_transfer normal_xfer[2]; + struct spi_message normal_msg; + struct spi_transfer seq_xfer[4]; + struct spi_message seq_msg; /* * DMA (thus cache coherency maintenance) requires the transfer buffers * to live in their own cache lines. @@ -609,33 +625,47 @@ static int ad7380_set_ch(struct ad7380_state *st, uns= igned int ch) static void ad7380_update_xfers(struct ad7380_state *st, const struct iio_scan_type *scan_type) { - /* - * First xfer only triggers conversion and has to be long enough for - * all conversions to complete, which can be multiple conversion in the - * case of oversampling. Technically T_CONVERT_X_NS is lower for some - * chips, but we use the maximum value for simplicity for now. - */ - if (st->oversampling_ratio > 1) - st->xfer[0].delay.value =3D T_CONVERT_0_NS + T_CONVERT_X_NS * - (st->oversampling_ratio - 1); - else - st->xfer[0].delay.value =3D T_CONVERT_NS; - - st->xfer[0].delay.unit =3D SPI_DELAY_UNIT_NSECS; + struct spi_transfer *xfer =3D st->seq ? st->seq_xfer : st->normal_xfer; + unsigned int t_convert =3D T_CONVERT_NS; =20 /* - * Second xfer reads all channels. Data size depends on if resolution - * boost is enabled or not. + * In the case of oversampling, conversion time is higher than in normal + * mode. Technically T_CONVERT_X_NS is lower for some chips, but we use + * the maximum value for simplicity for now. */ - st->xfer[1].bits_per_word =3D scan_type->realbits; - st->xfer[1].len =3D BITS_TO_BYTES(scan_type->storagebits) * - st->chip_info->num_simult_channels; + if (st->oversampling_ratio > 1) + t_convert =3D T_CONVERT_0_NS + T_CONVERT_X_NS * + (st->oversampling_ratio - 1); + + if (st->seq) { + xfer[0].delay.value =3D xfer[1].delay.value =3D t_convert; + xfer[0].delay.unit =3D xfer[1].delay.unit =3D SPI_DELAY_UNIT_NSECS; + xfer[2].bits_per_word =3D xfer[3].bits_per_word =3D + scan_type->realbits; + xfer[2].len =3D xfer[3].len =3D + BITS_TO_BYTES(scan_type->storagebits) * + st->chip_info->num_simult_channels; + xfer[3].rx_buf =3D xfer[2].rx_buf + xfer[2].len; + /* Additional delay required here when oversampling is enabled */ + if (st->oversampling_ratio > 1) + xfer[2].delay.value =3D t_convert; + else + xfer[2].delay.value =3D 0; + xfer[2].delay.unit =3D SPI_DELAY_UNIT_NSECS; + } else { + xfer[0].delay.value =3D t_convert; + xfer[0].delay.unit =3D SPI_DELAY_UNIT_NSECS; + xfer[1].bits_per_word =3D scan_type->realbits; + xfer[1].len =3D BITS_TO_BYTES(scan_type->storagebits) * + st->chip_info->num_simult_channels; + } } =20 static int ad7380_triggered_buffer_preenable(struct iio_dev *indio_dev) { struct ad7380_state *st =3D iio_priv(indio_dev); const struct iio_scan_type *scan_type; + struct spi_message *msg =3D &st->normal_msg; =20 /* * Currently, we always read all channels at the same time. The scan_type @@ -651,28 +681,57 @@ static int ad7380_triggered_buffer_preenable(struct i= io_dev *indio_dev) =20 /* * Depending on the requested scan_mask and current state, - * we need to change CH bit to sample correct data. + * we need to either change CH bit, or enable sequencer mode + * to sample correct data. + * Sequencer mode is enabled if active mask corresponds to all + * IIO channels enabled. Otherwise, CH bit is set. */ ret =3D iio_active_scan_mask_index(indio_dev); if (ret < 0) return ret; =20 index =3D ret; - ret =3D ad7380_set_ch(st, index); - if (ret) - return ret; + if (index =3D=3D AD7380_SCAN_MASK_SEQ) { + ret =3D regmap_update_bits(st->regmap, + AD7380_REG_ADDR_CONFIG1, + AD7380_CONFIG1_SEQ, + FIELD_PREP(AD7380_CONFIG1_SEQ, 1)); + if (ret) + return ret; + msg =3D &st->seq_msg; + st->seq =3D true; + } else { + ret =3D ad7380_set_ch(st, index); + if (ret) + return ret; + } + } =20 ad7380_update_xfers(st, scan_type); =20 - return spi_optimize_message(st->spi, &st->msg); + return spi_optimize_message(st->spi, msg); } =20 static int ad7380_triggered_buffer_postdisable(struct iio_dev *indio_dev) { struct ad7380_state *st =3D iio_priv(indio_dev); + struct spi_message *msg =3D &st->normal_msg; + int ret; + + if (st->seq) { + ret =3D regmap_update_bits(st->regmap, + AD7380_REG_ADDR_CONFIG1, + AD7380_CONFIG1_SEQ, + FIELD_PREP(AD7380_CONFIG1_SEQ, 0)); + if (ret) + return ret; + + msg =3D &st->seq_msg; + st->seq =3D false; + } =20 - spi_unoptimize_message(&st->msg); + spi_unoptimize_message(msg); =20 return 0; } @@ -687,9 +746,10 @@ static irqreturn_t ad7380_trigger_handler(int irq, voi= d *p) struct iio_poll_func *pf =3D p; struct iio_dev *indio_dev =3D pf->indio_dev; struct ad7380_state *st =3D iio_priv(indio_dev); + struct spi_message *msg =3D st->seq ? &st->seq_msg : &st->normal_msg; int ret; =20 - ret =3D spi_sync(st->spi, &st->msg); + ret =3D spi_sync(st->spi, msg); if (ret) goto out; =20 @@ -723,7 +783,7 @@ static int ad7380_read_direct(struct ad7380_state *st, = unsigned int scan_index, =20 ad7380_update_xfers(st, scan_type); =20 - ret =3D spi_sync(st->spi, &st->msg); + ret =3D spi_sync(st->spi, &st->normal_msg); if (ret < 0) return ret; =20 @@ -919,6 +979,7 @@ static int ad7380_init(struct ad7380_state *st, struct = regulator *vref) /* This is the default value after reset. */ st->oversampling_ratio =3D 1; st->ch =3D 0; + st->seq =3D false; =20 /* SPI 1-wire mode */ return regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, @@ -1020,21 +1081,45 @@ static int ad7380_probe(struct spi_device *spi) "failed to allocate register map\n"); =20 /* - * Setting up a low latency read for getting sample data. Used for both - * direct read an triggered buffer. Additional fields will be set up in - * ad7380_update_xfers() based on the current state of the driver at the - * time of the read. + * Setting up xfer structures for both normal and sequence mode. These + * struct are used for both direct read and triggered buffer. Additional + * fields will be set up in ad7380_update_xfers() based on the current + * state of the driver at the time of the read. */ =20 - /* toggle CS (no data xfer) to trigger a conversion */ - st->xfer[0].cs_change =3D 1; - st->xfer[0].cs_change_delay.value =3D st->chip_info->timing_specs->t_csh_= ns; - st->xfer[0].cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS; - - /* then do a second xfer to read the data */ - st->xfer[1].rx_buf =3D st->scan_data; + /* + * In normal mode a read is composed of two steps: + * - first, toggle CS (no data xfer) to trigger a conversion + * - then, read data + */ + st->normal_xfer[0].cs_change =3D 1; + st->normal_xfer[0].cs_change_delay.value =3D st->chip_info->timing_specs-= >t_csh_ns; + st->normal_xfer[0].cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS; + st->normal_xfer[1].rx_buf =3D st->scan_data; =20 - spi_message_init_with_transfers(&st->msg, st->xfer, ARRAY_SIZE(st->xfer)); + spi_message_init_with_transfers(&st->normal_msg, st->normal_xfer, + ARRAY_SIZE(st->normal_xfer)); + /* + * In sequencer mode a read is composed of four steps: + * - CS toggle (no data xfer) to get the right point in the sequence + * - CS toggle (no data xfer) to trigger a conversion of AinX0 and + * acquisition of AinX1 + * - 2 data reads, to read AinX0 and AinX1 + */ + st->seq_xfer[0].cs_change =3D 1; + st->seq_xfer[0].cs_change_delay.value =3D st->chip_info->timing_specs->t_= csh_ns; + st->seq_xfer[0].cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS; + st->seq_xfer[1].cs_change =3D 1; + st->seq_xfer[1].cs_change_delay.value =3D st->chip_info->timing_specs->t_= csh_ns; + st->seq_xfer[1].cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS; + + st->seq_xfer[2].rx_buf =3D st->scan_data; + st->seq_xfer[2].cs_change =3D 1; + st->seq_xfer[2].cs_change_delay.value =3D st->chip_info->timing_specs->t_= csh_ns; + st->seq_xfer[2].cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS; + + spi_message_init_with_transfers(&st->seq_msg, st->seq_xfer, + ARRAY_SIZE(st->seq_xfer)); =20 indio_dev->channels =3D st->chip_info->channels; indio_dev->num_channels =3D st->chip_info->num_channels; --=20 2.45.1 From nobody Thu Sep 19 01:00:13 2024 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06B0F1A4F33 for ; Wed, 31 Jul 2024 07:05:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722409561; cv=none; b=ZP0+6SWPvY+XNEi88bEI657Kw0PqrAfYlNl5p1Er0qTpMwNF0kA13ndywCJL8GvuCzhOxFzze+Qh4yeJuyIE018jMij4jGGHnJlni8+79tm78yBsVEBmZqtxeLsoyLGsWBSE8Zvn56av9hParwft5CoUeGDtnpLFnkwujqiVyfg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722409561; c=relaxed/simple; bh=7XD9EIzKfrzHxR8R1rUbV5Jj4bPwKwqrDZgXaJFs3os=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uUs8501QibudXRty699eBshEm2gIp2YqspYbeHOsT8LumbKvUKgEMa5NJendJC1YPqzkLwwzpD6hXgARls6WsWV+59veafsrHRcodZP7J8Ay9jt31JrwId64BlWQ0FDFzDyomLRFZFPXC5UTi6qxbzcMbiqwbY9DX9UaC7vgXTw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=EH0/0930; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="EH0/0930" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-428141be2ddso34280305e9.2 for ; Wed, 31 Jul 2024 00:05:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1722409557; x=1723014357; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=XWyBLNHlp9hCXozkWOndIbFuJnRj4rl0Qp1LlWnlIPI=; b=EH0/0930UrTTYLsNG8xu3L9fuVuRoKaUiyZsa88CzjEKYlGD2hr5T+oB/k+iBD5znM IDyuPgy1x4nFzsBFoY8cI1hhlQPa5kuOZX/ieA1Je3qKHoeAdUu9jJ02yJerpBHoWJFP TfnMkXjqt/K9k86cMdSRkpAn8e+Z40ypfBnVmpWTxv5GFPOOIshWD72kAlwkjYN+PKRs o1stTuJD3f8HZLmBXl1NGr5RVAAm8RZ1zQbvgo9rf/m7yjEJF+9kYO7ixdlqAZ7oKsZ0 WM1pnXCO2r+XIYyn3sr3qFZCdNvIyZwmayGrotPCdL5x1Smpt/CarSXppFLX4kjEaLut dLAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722409557; x=1723014357; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XWyBLNHlp9hCXozkWOndIbFuJnRj4rl0Qp1LlWnlIPI=; b=YLRE9iHr2xsQbT8Nx8BtwyL8JzEeAEwdANTK/JY36qEio+NdtnfaKIHERRyeLMzg3K nswKYpjs/77gnKwuHOYoZuUWE/c3xizJeCtOUcpUstd0BtrH00yb9x0htB7Qw1s97Pj0 9qCj8qJl4rszN6F4rWl93c3pRmn5zOnCf1JQGs44Hb8YEARutj4PjCro1y1ZBZRBbIXm T7evXGpBSLr4hjMspvGPNOiew0e6XK/w/xthwRSYf/3Wf67e0pJQ1PnAF7FNgg0KP6Jb KPJF/Q3cuE4vkJMVyEMSckyybcnj2u59AnXaeUJF1jEHJgXOSaxSpQkyTNpCl4xBdh9F yb1w== X-Forwarded-Encrypted: i=1; AJvYcCVG2mR9oGEKuJLmgwS1NqDL+vrCqUyhSnaiTzV0ioW55IqJVaxIXkVnrighzaha13XAnr4BLwwmQaLd61bbq+hvswkFBT5P/T0r8tjU X-Gm-Message-State: AOJu0YwRSQ2WLXnv84fR2Em+97dn+8ioUX5l3mHx+0AGF9IEf1sULeQs npTH9PFRuXNNd1eeaJxQ+ckSsCx3QIsfli+1j1kdM6VKm2Vfp648EBXipWPfXGg= X-Google-Smtp-Source: AGHT+IH10sHLkGAMAl3Q8EfCabIQTlCzo//xvraMgc7zTKLTmSclsI3goKn7cG5tDtZ67xA9JkON9Q== X-Received: by 2002:a05:600c:1da8:b0:426:6ead:5709 with SMTP id 5b1f17b1804b1-42811d8893fmr106640625e9.9.1722409557405; Wed, 31 Jul 2024 00:05:57 -0700 (PDT) Received: from [192.168.1.61] (2a02-842a-d52e-6101-6f8f-5617-c4b6-8627.rev.sfr.net. [2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4282b8a2593sm9953215e9.4.2024.07.31.00.05.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jul 2024 00:05:57 -0700 (PDT) From: Julien Stephan Date: Wed, 31 Jul 2024 09:05:48 +0200 Subject: [PATCH v2 7/7] docs: iio: ad7380: add support for single-ended parts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240731-ad7380-add-single-ended-chips-v2-7-cd63bf05744c@baylibre.com> References: <20240731-ad7380-add-single-ended-chips-v2-0-cd63bf05744c@baylibre.com> In-Reply-To: <20240731-ad7380-add-single-ended-chips-v2-0-cd63bf05744c@baylibre.com> To: Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Lars-Peter Clausen , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Cc: Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Julien Stephan X-Mailer: b4 0.13.0 The AD7380 family has some compatible single-ended chips: AD7386/7/8(-4). These single-ended chips have a 2:1 multiplexer in front of each ADC. They also include additional configuration registers that allow for either manual selection or automatic switching (sequencer mode), of the multiplexer inputs. Add a section to describe this. Signed-off-by: Julien Stephan Reviewed-by: David Lechner --- Documentation/iio/ad7380.rst | 42 ++++++++++++++++++++++++++++++++++++++++= ++ 1 file changed, 42 insertions(+) diff --git a/Documentation/iio/ad7380.rst b/Documentation/iio/ad7380.rst index 061cd632b5df..9c784c1e652e 100644 --- a/Documentation/iio/ad7380.rst +++ b/Documentation/iio/ad7380.rst @@ -17,10 +17,16 @@ The following chips are supported by this driver: * `AD7381 `_ * `AD7383 `_ * `AD7384 `_ +* `AD7386 `_ +* `AD7387 `_ +* `AD7388 `_ * `AD7380-4 `_ * `AD7381-4 `_ * `AD7383-4 `_ * `AD7384-4 `_ +* `AD7386-4 `_ +* `AD7387-4 `_ +* `AD7388-4 `_ =20 =20 Supported features @@ -69,6 +75,42 @@ must restart iiod using the following command: =20 root:~# systemctl restart iiod =20 +Channel selection and sequencer (single-end chips only) +------------------------------------------------------- + +Single-ended chips of this family (ad7386/7/8(-4)) have a 2:1 multiplexer = in +front of each ADC. They also include additional configuration registers th= at +allow for either manual selection or automatic switching (sequencer mode),= of +the multiplexer inputs. + +From an IIO point of view, all inputs are exported, i.e ad7386/7/8 +export 4 channels and ad7386-4/7-4/8-4 export 8 channels. + +Inputs ``AinX0`` of multiplexers correspond to the first half of IIO chann= els (i.e +0-1 or 0-3) and inputs ``AinX1`` correspond to second half (i.e 2-3 or 4-7= ). +Example for AD7386/7/8 (2 channels parts): + +.. code-block:: + + IIO | AD7386/7/8 + | +---------------------------- + | | _____ ______ + | | | | | | + voltage0 | AinA0 --|--->| | | | + | | | mux |----->| ADCA |--- + voltage2 | AinA1 --|--->| | | | + | | |_____| |_____ | + | | _____ ______ + | | | | | | + voltage1 | AinB0 --|--->| | | | + | | | mux |----->| ADCB |--- + voltage3 | AinB1 --|--->| | | | + | | |_____| |______| + | | + | +---------------------------- + + +When enabling sequencer mode, the effective sampling rate is divided by tw= o. =20 Unimplemented features ---------------------- --=20 2.45.1