From nobody Sun Feb 8 16:44:03 2026 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 103351974FE; Tue, 30 Jul 2024 14:34:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722350042; cv=none; b=N7qqdUlfpZn45f7s1j7dHKo2uUw2rDIA/4vEwjydOpTIFuCGEWwIhiEdP3OR9t3EKBAgXMp9btAM197QQl2O3Xwb2/aALum+NP9nY24azDePHtO7AX6avUt38zWV9jD9KS1kkjbpQnBRtIlpOYblb/1bOZV2+pkZKyFPe2i7HWk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722350042; c=relaxed/simple; bh=QntFGt347xXrOS+YXm75fiIXVZq1DpgEZhigVB4Ofqk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gqprjiKShvCB65UahgNfEUJ0FqSIc4uYvPviBUR9t2l4ClwOFC4wWgj2RRrxmaSVU/ffnq1dIGIoNolgqTBPBmATYkjXNoh2/wGXCbT8ZDjvlCRQDs5WwQdluZ9Rh36rYdKHqwb1YnurT4tyACfpTQiVK8920jFkrCmZdRblWxQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=j8swvWuM; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="j8swvWuM" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 46UEXsBw071998; Tue, 30 Jul 2024 09:33:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1722350034; bh=V7yVmENLwTwAaEZDAC7DlgO6gkCfyJeBQoy5yswINZM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=j8swvWuMIXDkvj+3bFhfRtxuV50okjwABv9QKhCLMb2a7CwgffimIWwjTcOoBdjCI k21IWlDbkx95l/SIHTzSiV5JacxDTGhT5XpZuj0AceFOS81+iVBxp5U42AQIleWzWp JEPhqc2B3xShzsvmwYsbRLAGcBgDzxz8Epucy3AU= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 46UEXsLo002830 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Jul 2024 09:33:54 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 30 Jul 2024 09:33:54 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 30 Jul 2024 09:33:53 -0500 Received: from localhost (uda0499903.dhcp.ti.com [128.247.81.191]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 46UEXrlt113107; Tue, 30 Jul 2024 09:33:53 -0500 From: Jared McArthur To: Conor Dooley , Krzysztof Kozlowski , Rob Herring CC: , , , Tero Kristo , Vignesh Raghavendra , Nishanth Menon , Jared McArthur Subject: [PATCH 1/3] arm64: dts: ti: k3-am62p: Add gpio-ranges for mcu_gpio0 Date: Tue, 30 Jul 2024 09:33:22 -0500 Message-ID: <20240730143324.114146-2-j-mcarthur@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240730143324.114146-1-j-mcarthur@ti.com> References: <20240730143324.114146-1-j-mcarthur@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Commit d72d73a44c3c ("arm64: dts: ti: k3-am62p: Add gpio-ranges properties") introduced pinmux range definition for gpio-ranges, however missed introducing the range description for the mcu_gpio0 node. As a result, automatic mapping of GPIO to pin control for mcu gpios is broken. Fix this by introducing the proper ranges. Fixes: d72d73a44c3c ("arm64: dts: ti: k3-am62p: Add gpio-ranges properties") Signed-off-by: Jared McArthur --- arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi b/arch/a= rm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi index e65db6ce02bf..c0bdbd00dc23 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi @@ -146,6 +146,9 @@ mcu_gpio0: gpio@4201000 { power-domains =3D <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 79 0>; clock-names =3D "gpio"; + gpio-ranges =3D <&mcu_pmx0 0 0 21>, <&mcu_pmx0 21 23 1>, + <&mcu_pmx0 22 32 2>; + ti,ngpio =3D <24>; }; =20 mcu_rti0: watchdog@4880000 { --=20 2.34.1 From nobody Sun Feb 8 16:44:03 2026 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 462571A01A6; Tue, 30 Jul 2024 14:34:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722350043; cv=none; b=AtnpCW18wsxPIqkiqhdW9DHDmuOdKIg77LgNV/TyiG7mdthRekqgFexfR8E6M2Z3x66MFHXcpZjEXXeqO9zx9h/O66+WAhBPsi8GTKRN5vUNVps/RYszbi7LFkjBH+gsDEOLNfYgpdANnwad/Mg58CplY/1n0Yv6u4Lmdm21BCM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722350043; c=relaxed/simple; bh=+nr1GoI3Frwa2RPsqcvt0siBVMwHXphw8PHqGZBiqEg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=paTMTgJy8MgRcGpDi2KVqJKCDksB/I5OVjuTILHRyTgYoQosOReOPk4+SYTb64aWp2k0w41HBgoPY5eKbLTFmIH1tFiStSEbgjEPC6kquu//zeppi8WI2N7semaGggpEQKl7wH2LDbVrWXXqElGZN44Hxn0jC+pL1SNISfWS194= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=jlixLmzP; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="jlixLmzP" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 46UEXsNB084540; Tue, 30 Jul 2024 09:33:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1722350034; bh=EMtiORd66vlEJH6ZRaH09TTPb066amp8TYtcY2yIZQE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jlixLmzPxPqDtf+ut+WTB6xPttyFHp/hNZcVsfqqAeMff9pMvuMW7yrxkG6HjBtFJ 3L3l6u61fcSgMvfLfRxFi9IvwWxsR1XGBml3BDccjDYHF80fkPaDW3ZdTSmIJM8fIx JMQX+/uDU8NtmDFwY7CMWAXy5IW2VnLc3b4w0yzQ= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 46UEXsQU113730 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Jul 2024 09:33:54 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 30 Jul 2024 09:33:53 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 30 Jul 2024 09:33:53 -0500 Received: from localhost (uda0499903.dhcp.ti.com [128.247.81.191]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 46UEXrHe047206; Tue, 30 Jul 2024 09:33:53 -0500 From: Jared McArthur To: Conor Dooley , Krzysztof Kozlowski , Rob Herring CC: , , , Tero Kristo , Vignesh Raghavendra , Nishanth Menon , Jared McArthur Subject: [PATCH 2/3] arm64: dts: ti: k3-am62p: Fix gpio-range for main_pmx0 Date: Tue, 30 Jul 2024 09:33:23 -0500 Message-ID: <20240730143324.114146-3-j-mcarthur@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240730143324.114146-1-j-mcarthur@ti.com> References: <20240730143324.114146-1-j-mcarthur@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Commit d72d73a44c3c ("arm64: dts: ti: k3-am62p: Add gpio-ranges properties") introduced pinmux range definition for gpio-ranges, however missed a hole within gpio-range for main_pmx0. As a result, automatic mapping of GPIO to pin control for gpios within the main_pmx0 domain is broken. Fix this by correcting the gpio-range. Fixes: d72d73a44c3c ("arm64: dts: ti: k3-am62p: Add gpio-ranges properties") Signed-off-by: Jared McArthur --- arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-am62p-main.dtsi index 57383bd2eaeb..0ce9721b4176 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -45,7 +45,8 @@ &inta_main_dmss { &main_pmx0 { pinctrl-single,gpio-range =3D <&main_pmx0_range 0 32 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 33 92 PIN_GPIO_RANGE_IOPAD>, + <&main_pmx0_range 33 38 PIN_GPIO_RANGE_IOPAD>, + <&main_pmx0_range 72 22 PIN_GPIO_RANGE_IOPAD>, <&main_pmx0_range 137 5 PIN_GPIO_RANGE_IOPAD>, <&main_pmx0_range 143 3 PIN_GPIO_RANGE_IOPAD>, <&main_pmx0_range 149 2 PIN_GPIO_RANGE_IOPAD>; --=20 2.34.1 From nobody Sun Feb 8 16:44:03 2026 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34C611A00CB; Tue, 30 Jul 2024 14:34:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722350043; cv=none; b=onVwEh3AI5W2dPQDyNBGe+WXdU9hsPez9in/+Cjla0TEa3OUHg8EydmtKwshEClygyc8OxSDjbFSqw3CPuKHB3ZjvQYwqrvs3haUFJFzrvaXbi6OcQDzHWD9N7tNN5BVEzwFxYViytROaNvhyArrAs8OIHiI1vOuZ7J1oxrQciM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722350043; c=relaxed/simple; bh=x5BAaeHjkk+lKClu962uxrP1nFjlgB9fZzFrGKxn1fQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tzEmbnJL6xiKt3O5a0XkXACbMWpJ2Uaj3c2d2tU1BSE33GOxymV0eDuHWYoluQ5uKeqJRyAhj1MObOMNI9SltiHsIguIePT1U6a0U4zPD2S4QEZcGwIwRgkwvN7Bt2MDrTd/HvRhN2xisXe3m1YeuNOCI8tP6ievaAmTktDP1EM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=fWG/LIxM; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="fWG/LIxM" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 46UEXsGl064603; Tue, 30 Jul 2024 09:33:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1722350034; bh=BWF0D90J2h4jZsDlwi8UwuzmBVysVZiKD6+jRBfjcKk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=fWG/LIxM0qQkG7pwC3jJ8SzUDNAicUiSfG6ZhEzHe7SJi082bAvO/6//bvLJ2i0Mi ejnuc3+SvYOAh9q51PZCSJcnpfwDEZ2apy0oDTKVxSnE3vZmzdCAnzGfhE9fMjZGtF 9rXjqS/xdieTzapHGdEBqzZz9WEPlTk32+W7zkxg= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 46UEXsrR032584 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Jul 2024 09:33:54 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 30 Jul 2024 09:33:54 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 30 Jul 2024 09:33:53 -0500 Received: from localhost (uda0499903.dhcp.ti.com [128.247.81.191]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 46UEXrOO047209; Tue, 30 Jul 2024 09:33:53 -0500 From: Jared McArthur To: Conor Dooley , Krzysztof Kozlowski , Rob Herring CC: , , , Tero Kristo , Vignesh Raghavendra , Nishanth Menon , Jared McArthur Subject: [PATCH 3/3] arm64: dts: ti: k3-j722s: Fix gpio-range for main_pmx0 Date: Tue, 30 Jul 2024 09:33:24 -0500 Message-ID: <20240730143324.114146-4-j-mcarthur@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240730143324.114146-1-j-mcarthur@ti.com> References: <20240730143324.114146-1-j-mcarthur@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Commit 5e5c50964e2e ("arm64: dts: ti: k3-j722s: Add gpio-ranges properties") introduced pinmux range definition for gpio-ranges, however missed a hole within gpio-range for main_pmx0. As a result, automatic mapping of GPIO to pin control for gpios within the main_pmx0 domain is broken. Fix this by correcting the gpio-range. Fixes: 5e5c50964e2e ("arm64: dts: ti: k3-j722s: Add gpio-ranges properties") Signed-off-by: Jared McArthur --- arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j722s-main.dtsi index c797980528ec..dde4bd5c6645 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -193,7 +193,8 @@ &inta_main_dmss { &main_pmx0 { pinctrl-single,gpio-range =3D <&main_pmx0_range 0 32 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 33 55 PIN_GPIO_RANGE_IOPAD>, + <&main_pmx0_range 33 38 PIN_GPIO_RANGE_IOPAD>, + <&main_pmx0_range 72 17 PIN_GPIO_RANGE_IOPAD>, <&main_pmx0_range 101 25 PIN_GPIO_RANGE_IOPAD>, <&main_pmx0_range 137 5 PIN_GPIO_RANGE_IOPAD>, <&main_pmx0_range 143 3 PIN_GPIO_RANGE_IOPAD>, --=20 2.34.1