From nobody Fri Dec 19 03:44:54 2025 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F0BAA23 for ; Tue, 30 Jul 2024 01:38:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.187 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722303522; cv=none; b=QSqiZIKWtYj9+bR04mqH0cQNTAiiRhqb0+M+4f8zdllYhSax5ZMB4lwKrU9sV5VNUAEnT7jGgtJVhElLLAnoqSeof1ojKY1xkiNh+E+mcMxQfkKr2eQdMOmYACcMPfHq11atzq82fX98j2dACqFKePUuDueyWMovgxOcJEtuTxk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722303522; c=relaxed/simple; bh=/eA8ziZCHEGbM2sWoGb6gjWzwYjOTBwK0ePdfEz/jn8=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=gDXWraBmJCmvl888G1YY1In8krW9+CMUxeLwGUHrm66JvpmTTuatQ/6kXFWLcCVe74m9PnYxocbsFGmn5bYpGi5ISKQpnrNdA0AASvlyxfrlDEvTQYJ0mVeCkkXaHFni4Gj4Eky8r57raLggbCtGLBNQbLDvuZZldmM+FEYiQHg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.187 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.252]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4WXyRn2pvmzyNyw; Tue, 30 Jul 2024 09:33:41 +0800 (CST) Received: from kwepemg200002.china.huawei.com (unknown [7.202.181.29]) by mail.maildlp.com (Postfix) with ESMTPS id 31AC51800A2; Tue, 30 Jul 2024 09:38:38 +0800 (CST) Received: from huawei.com (10.90.53.73) by kwepemg200002.china.huawei.com (7.202.181.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 30 Jul 2024 09:38:37 +0800 From: Yipeng Zou To: , , , , , CC: Subject: [PATCH v2] irqchip/mbigen: Fix mbigen node address layout Date: Tue, 30 Jul 2024 09:44:00 +0800 Message-ID: <20240730014400.1751530-1-zouyipeng@huawei.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To kwepemg200002.china.huawei.com (7.202.181.29) Content-Type: text/plain; charset="utf-8" The mbigen interrupt chip has its per node registers located in a contiguous region of page sized chunks. The code maps them into virtual address space as a contiguous region and determines the address of a node by using the node ID as index. mbigen chip |-----------------|------------|--------------| mgn_node_0 mgn_node_1 ... mgn_node_i |--------------| |--------------| |----------------------| [0x0000, 0x1000) [0x1000, 0x2000) [i*0x1000, (i+1)*0x1000) This works correctly up to 10 nodes, but then fails because the 11th's array slot is used for the MGN_CLEAR registers. mbigen chip |-----------|--------|--------|---------------|--------| mgn_node_0 mgn_node_1 ... mgn_clear_register ... mgn_node_i |-----------------| [0xA000, 0xB000) Skip the MGN_CLEAR register space when calculating the offset for node IDs greater or equal to ten. Fixes: a6c2f87b8820 ("irqchip/mbigen: Implement the mbigen irq chip operati= on functions") Signed-off-by: Yipeng Zou --- drivers/irqchip/irq-mbigen.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c index 093fd42893a7..53cc08387588 100644 --- a/drivers/irqchip/irq-mbigen.c +++ b/drivers/irqchip/irq-mbigen.c @@ -64,6 +64,20 @@ struct mbigen_device { void __iomem *base; }; =20 +static inline unsigned int get_mbigen_node_offset(unsigned int nid) +{ + unsigned int offset =3D nid * MBIGEN_NODE_OFFSET; + + /* + * To avoid touched clear register in unexpected way, we need to directly + * skip clear register when access to more than 10 mbigen nodes. + */ + if (nid >=3D (REG_MBIGEN_CLEAR_OFFSET / MBIGEN_NODE_OFFSET)) + offset +=3D MBIGEN_NODE_OFFSET; + + return offset; +} + static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq) { unsigned int nid, pin; @@ -72,8 +86,7 @@ static inline unsigned int get_mbigen_vec_reg(irq_hw_numb= er_t hwirq) nid =3D hwirq / IRQS_PER_MBIGEN_NODE + 1; pin =3D hwirq % IRQS_PER_MBIGEN_NODE; =20 - return pin * 4 + nid * MBIGEN_NODE_OFFSET - + REG_MBIGEN_VEC_OFFSET; + return pin * 4 + get_mbigen_node_offset(nid) + REG_MBIGEN_VEC_OFFSET; } =20 static inline void get_mbigen_type_reg(irq_hw_number_t hwirq, @@ -88,8 +101,7 @@ static inline void get_mbigen_type_reg(irq_hw_number_t h= wirq, *mask =3D 1 << (irq_ofst % 32); ofst =3D irq_ofst / 32 * 4; =20 - *addr =3D ofst + nid * MBIGEN_NODE_OFFSET - + REG_MBIGEN_TYPE_OFFSET; + *addr =3D ofst + get_mbigen_node_offset(nid) + REG_MBIGEN_TYPE_OFFSET; } =20 static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq, --=20 2.34.1