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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Robert Moore , Conor Dooley , Andrew Jones , Haibo Xu , Atish Kumar Patra , Drew Fustini , Sunil V L Subject: [PATCH v7 13/17] irqchip/riscv-intc: Add ACPI support for AIA Date: Mon, 29 Jul 2024 19:52:35 +0530 Message-ID: <20240729142241.733357-14-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240729142241.733357-1-sunilvl@ventanamicro.com> References: <20240729142241.733357-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RINTC subtype structure in MADT also has information about other interrupt controllers. Save this information and provide interfaces to retrieve them when required by corresponding drivers. Signed-off-by: Sunil V L Reviewed-by: Anup Patel --- arch/riscv/include/asm/irq.h | 33 ++++++++++++ drivers/irqchip/irq-riscv-intc.c | 90 ++++++++++++++++++++++++++++++++ 2 files changed, 123 insertions(+) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index 44a0b128c602..51d86f0b80d2 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -12,6 +12,8 @@ =20 #include =20 +#define INVALID_CONTEXT UINT_MAX + void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)); =20 struct fwnode_handle *riscv_get_intc_hwnode(void); @@ -28,6 +30,11 @@ enum riscv_irqchip_type { int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base, u32 *id, u32 *nr_irqs, u32 *nr_idcs); struct fwnode_handle *riscv_acpi_get_gsi_domain_id(u32 gsi); +unsigned long acpi_get_intc_index_hartid(u32 index); +unsigned long acpi_get_ext_intc_parent_hartid(unsigned int plic_id, unsign= ed int ctxt_idx); +unsigned int acpi_get_plic_nr_contexts(unsigned int plic_id); +unsigned int acpi_get_plic_context(unsigned int plic_id, unsigned int ctxt= _idx); +int __init acpi_get_imsic_mmio_info(u32 index, struct resource *res); =20 #else static inline int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u3= 2 *gsi_base, @@ -36,6 +43,32 @@ static inline int riscv_acpi_get_gsi_info(struct fwnode_= handle *fwnode, u32 *gsi return 0; } =20 +static inline unsigned long acpi_get_intc_index_hartid(u32 index) +{ + return INVALID_HARTID; +} + +static inline unsigned long acpi_get_ext_intc_parent_hartid(unsigned int p= lic_id, + unsigned int ctxt_idx) +{ + return INVALID_HARTID; +} + +static inline unsigned int acpi_get_plic_nr_contexts(unsigned int plic_id) +{ + return INVALID_CONTEXT; +} + +static inline unsigned int acpi_get_plic_context(unsigned int plic_id, uns= igned int ctxt_idx) +{ + return INVALID_CONTEXT; +} + +static inline int __init acpi_get_imsic_mmio_info(u32 index, struct resour= ce *res) +{ + return 0; +} + #endif /* CONFIG_ACPI */ =20 #endif /* _ASM_RISCV_IRQ_H */ diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index 47f3200476da..5ddb12ce8b97 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -250,6 +250,85 @@ IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_int= c_init); =20 #ifdef CONFIG_ACPI =20 +struct rintc_data { + union { + u32 ext_intc_id; + struct { + u32 context_id : 16, + reserved : 8, + aplic_plic_id : 8; + }; + }; + unsigned long hart_id; + u64 imsic_addr; + u32 imsic_size; +}; + +static u32 nr_rintc; +static struct rintc_data *rintc_acpi_data[NR_CPUS]; + +#define for_each_matching_plic(_plic_id) \ + unsigned int _plic; \ + \ + for (_plic =3D 0; _plic < nr_rintc; _plic++) \ + if (rintc_acpi_data[_plic]->aplic_plic_id !=3D _plic_id) \ + continue; \ + else + +unsigned int acpi_get_plic_nr_contexts(unsigned int plic_id) +{ + unsigned int nctx =3D 0; + + for_each_matching_plic(plic_id) + nctx++; + + return nctx; +} + +static struct rintc_data *get_plic_context(unsigned int plic_id, unsigned = int ctxt_idx) +{ + unsigned int ctxt =3D 0; + + for_each_matching_plic(plic_id) { + if (ctxt =3D=3D ctxt_idx) + return rintc_acpi_data[_plic]; + + ctxt++; + } + + return NULL; +} + +unsigned long acpi_get_ext_intc_parent_hartid(unsigned int plic_id, unsign= ed int ctxt_idx) +{ + struct rintc_data *data =3D get_plic_context(plic_id, ctxt_idx); + + return data ? data->hart_id : INVALID_HARTID; +} + +unsigned int acpi_get_plic_context(unsigned int plic_id, unsigned int ctxt= _idx) +{ + struct rintc_data *data =3D get_plic_context(plic_id, ctxt_idx); + + return data ? data->context_id : INVALID_CONTEXT; +} + +unsigned long acpi_get_intc_index_hartid(u32 index) +{ + return index >=3D nr_rintc ? INVALID_HARTID : rintc_acpi_data[index]->har= t_id; +} + +int acpi_get_imsic_mmio_info(u32 index, struct resource *res) +{ + if (index >=3D nr_rintc) + return -1; + + res->start =3D rintc_acpi_data[index]->imsic_addr; + res->end =3D res->start + rintc_acpi_data[index]->imsic_size - 1; + res->flags =3D IORESOURCE_MEM; + return 0; +} + static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header, const unsigned long end) { @@ -258,6 +337,15 @@ static int __init riscv_intc_acpi_init(union acpi_subt= able_headers *header, int rc; =20 rintc =3D (struct acpi_madt_rintc *)header; + rintc_acpi_data[nr_rintc] =3D kzalloc(sizeof(*rintc_acpi_data[0]), GFP_KE= RNEL); + if (!rintc_acpi_data[nr_rintc]) + return -ENOMEM; + + rintc_acpi_data[nr_rintc]->ext_intc_id =3D rintc->ext_intc_id; + rintc_acpi_data[nr_rintc]->hart_id =3D rintc->hart_id; + rintc_acpi_data[nr_rintc]->imsic_addr =3D rintc->imsic_addr; + rintc_acpi_data[nr_rintc]->imsic_size =3D rintc->imsic_size; + nr_rintc++; =20 /* * The ACPI MADT will have one INTC for each CPU (or HART) @@ -277,6 +365,8 @@ static int __init riscv_intc_acpi_init(union acpi_subta= ble_headers *header, rc =3D riscv_intc_init_common(fn, &riscv_intc_chip); if (rc) irq_domain_free_fwnode(fn); + else + acpi_set_irq_model(ACPI_IRQ_MODEL_RINTC, riscv_acpi_get_gsi_domain_id); =20 return rc; } --=20 2.43.0