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Each component of PCIe communication have the following control signals: PERST, WAKE, CLKREQ, and REFCLK. These signals work to generate high-speed signals and communicate with other PCIe devices. Used by root complex to endpoint depending on the power state. PERST# is referred to as a fundamental reset. PERST should be held low until all the power rails in the system and the reference clock are stable. A transition from low to high in this signal usually indicates the beginning of link initialization. WAKE# signal is an active-low signal that is used to return the PCIe interface to an active state when in a low-power state. CLKREQ# signal is also an active-low signal and is used to request the reference clock. L1 sub-states is providing a digital signal (CLKREQ#) for PHYs to use to wake up and resume normal operation. Signed-off-by: Anand Moon --- v5: Merged all 3 patch into single patch, reabse on master Fix the $subject and commit message. Drop the RK_FUNC_GPIO for WAKE and CLKREQ as these seignal are ment for was introduced to allow PCI Express devices to enter even deeper power savings states (=E2=80=9CL1.1=E2=80=9D and =E2=80=9CL= 1.2=E2=80=9D) while still appearing to legacy software to be in the =E2=80=9CL1=E2=80=9D state --- .../boot/dts/rockchip/rk3588-rock-5b.dts | 46 +++++++++++++------ 1 file changed, 33 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/b= oot/dts/rockchip/rk3588-rock-5b.dts index 966bbc582d89..a1e83546f1be 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -318,7 +318,7 @@ map2 { =20 &pcie2x1l0 { pinctrl-names =3D "default"; - pinctrl-0 =3D <&pcie2_0_rst>; + pinctrl-0 =3D <&pcie30x1_pins>; reset-gpios =3D <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; vpcie3v3-supply =3D <&vcc3v3_pcie2x1l0>; status =3D "okay"; @@ -326,7 +326,7 @@ &pcie2x1l0 { =20 &pcie2x1l2 { pinctrl-names =3D "default"; - pinctrl-0 =3D <&pcie2_2_rst>; + pinctrl-0 =3D <&pcie20x12_pins>; reset-gpios =3D <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; vpcie3v3-supply =3D <&vcc3v3_pcie2x1l2>; status =3D "okay"; @@ -338,7 +338,7 @@ &pcie30phy { =20 &pcie3x4 { pinctrl-names =3D "default"; - pinctrl-0 =3D <&pcie3_rst>; + pinctrl-0 =3D <&pcie30x4_pins>; reset-gpios =3D <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply =3D <&vcc3v3_pcie30>; status =3D "okay"; @@ -363,28 +363,48 @@ hp_detect: hp-detect { }; }; =20 - pcie2 { - pcie2_0_rst: pcie2-0-rst { - rockchip,pins =3D <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + pcie20x1 { + pcie20x12_pins: pcie20x12-pins { + rockchip,pins =3D + /* PCIE20_1_2_CLKREQn_M1_L */ + <3 RK_PC7 4 &pcfg_pull_up>, + /* PCIE_PERST_L */ + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, + /* PCIE20_1_2_WAKEn_M1_L */ + <3 RK_PD0 4 &pcfg_pull_up>; }; + }; =20 + pcie30x1 { pcie2_0_vcc3v3_en: pcie2-0-vcc-en { rockchip,pins =3D <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; }; =20 - pcie2_2_rst: pcie2-2-rst { - rockchip,pins =3D <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + pcie30x1_pins: pcie30x1-pins { + rockchip,pins =3D + /* PCIE30x1_0_CLKREQn_M1_L */ + <4 RK_PA3 4 &pcfg_pull_down>, + /* PCIE30x1_0_PERSTn_M1_L */ + <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>, + /* PCIE30x1_0_WAKEn_M1_L */ + <4 RK_PA4 4 &pcfg_pull_down>; }; }; =20 - pcie3 { - pcie3_rst: pcie3-rst { - rockchip,pins =3D <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - + pcie30x4 { pcie3_vcc3v3_en: pcie3-vcc3v3-en { rockchip,pins =3D <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; }; + + pcie30x4_pins: pcie30x4-pins { + rockchip,pins =3D + /* PCIE30X4_CLKREQn_M1_L */ + <4 RK_PB4 4 &pcfg_pull_up>, + /* PCIE30X4_PERSTn_M1_L */ + <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>, + /* PCIE30X4_WAKEn_M1_L */ + <4 RK_PB5 4 &pcfg_pull_down>; + }; }; =20 usb { base-commit: dc1c8034e31b14a2e5e212104ec508aec44ce1b9 --=20 2.44.0