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Received: by exim-smtp-868bf69f6c-zg7fr with esmtpa (envelope-from ) id 1sYKuF-00000000275-38KR; Mon, 29 Jul 2024 10:34:56 +0300 From: Arseniy Velikanov To: mturquette@baylibre.com, sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, sean.wang@kernel.org, linus.walleij@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, frank.li@vivo.com, jiasheng@iscas.ac.cn, mars.cheng@mediatek.com, owen.chen@mediatek.com, macpaul.lin@mediatek.com, zh.chen@mediatek.com, argus.lin@mediatek.com Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Arseniy Velikanov Subject: [PATCH 1/5] dt-bindings: clock: mt6765: Add missing PMIC clock Date: Mon, 29 Jul 2024 11:34:24 +0400 Message-ID: <20240729073428.28983-2-me@adomerle.xyz> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240729073428.28983-1-me@adomerle.xyz> References: <20240729073428.28983-1-me@adomerle.xyz> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mailru-Src: smtp X-7564579A: B8F34718100C35BD X-77F55803: 4F1203BC0FB41BD9000B6812E77BE1C6F0D221D1B7CB84E2160E2B5FE815AD3B182A05F538085040EF34FD0AB11A37C53DE06ABAFEAF67050A0C1D41407711BE303324A9B5BFDD3258986F725C2A4283 X-7FA49CB5: FF5795518A3D127A4AD6D5ED66289B5278DA827A17800CE793089AEA09EF102BEA1F7E6F0F101C67BD4B6F7A4D31EC0BCC500DACC3FED6E28638F802B75D45FF8AA50765F790063745B6F93C788775E78638F802B75D45FF36EB9D2243A4F8B5A6FCA7DBDB1FC311F39EFFDF887939037866D6147AF826D8EAFA047CD450D65583832EE758E1DF54FD86F243095BA4A5CC7F00164DA146DAFE8445B8C89999728AA50765F7900637028599BB38096F4F389733CBF5DBD5E9C8A9BA7A39EFB766F5D81C698A659EA7CC7F00164DA146DA9985D098DBDEAEC8D2A98E5A6551E3E5117882F4460429728AD0CFFFB425014E868A13BD56FB6657D81D268191BDAD3DC09775C1D3CA48CF055A3127ECEB1CB3BA3038C0950A5D36C8A9BA7A39EFB766D91E3A1F190DE8FDBA3038C0950A5D36D5E8D9A59859A8B61FFDF4B5E34157C176E601842F6C81A1F004C906525384303E02D724532EE2C3F43C7A68FF6260569E8FC8737B5C2249EC8D19AE6D49635B68655334FD4449CB9ECD01F8117BC8BEAAAE862A0553A39223F8577A6DFFEA7C5E1C53F199C2BB95B5C8C57E37DE458BEDA766A37F9254B7 X-C1DE0DAB: 0D63561A33F958A5F5DB60828C4BA8AE5002B1117B3ED6961D04A7459567D2FFBFF4097FFC9E796F823CB91A9FED034534781492E4B8EEAD9CFA8CFAC159CE19C79554A2A72441328621D336A7BC284946AD531847A6065A535571D14F44ED41 X-C8649E89: 1C3962B70DF3F0ADE00A9FD3E00BEEDF77DD89D51EBB7742D3581295AF09D3DF87807E0823442EA2ED31085941D9CD0AF7F820E7B07EA4CFC35B71914E27C0DF66C6FC9A8988FE5A15CC854EA8CCEF6E2AD8E098005480FBB0F06D2F9487D0FC67C7AAC6E25A2086F0B81A1E795561CBFEDD108130C0427CA96BF36F8852DE3522BA058254B804A102C26D483E81D6BE44BE0F8B58F75087CBB04030989F1EE011FE023E09B2D9C0 X-D57D3AED: 3ZO7eAau8CL7WIMRKs4sN3D3tLDjz0dLbV79QFUyzQ2Ujvy7cMT6pYYqY16iZVKkSc3dCLJ7zSJH7+u4VD18S7Vl4ZUrpaVfd2+vE6kuoey4m4VkSEu530nj6fImhcD4MUrOEAnl0W826KZ9Q+tr5ycPtXkTV4k65bRjmOUUP8cvGozZ33TWg5HZplvhhXbhDGzqmQDTd6OAevLeAnq3Ra9uf7zvY2zzsIhlcp/Y7m53TZgf2aB4JOg4gkr2biojX2k8aL79D6Uopk33/Q/B+g== X-Mailru-Sender: 5DE64BD8B4008F63F32F89B2E510BB548372E88CF31825DAB951B70A5BD4BD8EADFCC5A6732EA59FF1FEA02A07AA46D63B9265ADAFE7D7E06F53C80213D1719CA6FC796F43705345A9EF9D9C6A90DD94D3D6663D5D4272A7B4A721A3011E896F X-Mras: Ok X-7564579A: 646B95376F6C166E X-77F55803: 6242723A09DB00B431B8944160407DD089A7AE0D179B51619F9534A46E763EF368F3CF0E9FE49B69BA651B92B2A570CD43AB70617FBFEEA7B40AA28FE4929FBFE23D54027332D046 X-7FA49CB5: 0D63561A33F958A51EC06C8DC4B0EDD370EFA612254C0AEBA143497BDFABF0948941B15DA834481FA18204E546F3947C7893FB2F108C49E4F6B57BC7E64490618DEB871D839B7333395957E7521B51C2DFABB839C843B9C08941B15DA834481F8AA50765F790063780B3000F7A6F2D7A389733CBF5DBD5E9B5C8C57E37DE458BD96E472CDF7238E0725E5C173C3A84C3DD19ECFA348986C535872C767BF85DA2F004C90652538430E4A6367B16DE6309 X-D57D3AED: 3ZO7eAau8CL7WIMRKs4sN3D3tLDjz0dLbV79QFUyzQ2Ujvy7cMT6pYYqY16iZVKkSc3dCLJ7zSJH7+u4VD18S7Vl4ZUrpaVfd2+vE6kuoey4m4VkSEu530nj6fImhcD4MUrOEAnl0W826KZ9Q+tr5ycPtXkTV4k65bRjmOUUP8cvGozZ33TWg5HZplvhhXbhDGzqmQDTd6OAevLeAnq3Ra9uf7zvY2zzsIhlcp/Y7m53TZgf2aB4JOg4gkr2biojX2k8aL79D6Uemu3hPbpjWQ== X-Mailru-MI: 8000000000000800 X-Mras: Ok Content-Type: text/plain; charset="utf-8" Add PWRAP clock binding and shift the following ones Fixes: eb7beb65ac30 ("clk: mediatek: add mt6765 clock IDs") Signed-off-by: Arseniy Velikanov --- include/dt-bindings/clock/mt6765-clk.h | 131 +++++++++++++------------ 1 file changed, 66 insertions(+), 65 deletions(-) diff --git a/include/dt-bindings/clock/mt6765-clk.h b/include/dt-bindings/c= lock/mt6765-clk.h index eb97e568518e..5d3a603a0d36 100644 --- a/include/dt-bindings/clock/mt6765-clk.h +++ b/include/dt-bindings/clock/mt6765-clk.h @@ -161,71 +161,72 @@ #define CLK_TOP_NR_CLK 126 =20 /* INFRACFG */ -#define CLK_IFR_ICUSB 0 -#define CLK_IFR_GCE 1 -#define CLK_IFR_THERM 2 -#define CLK_IFR_I2C_AP 3 -#define CLK_IFR_I2C_CCU 4 -#define CLK_IFR_I2C_SSPM 5 -#define CLK_IFR_I2C_RSV 6 -#define CLK_IFR_PWM_HCLK 7 -#define CLK_IFR_PWM1 8 -#define CLK_IFR_PWM2 9 -#define CLK_IFR_PWM3 10 -#define CLK_IFR_PWM4 11 -#define CLK_IFR_PWM5 12 -#define CLK_IFR_PWM 13 -#define CLK_IFR_UART0 14 -#define CLK_IFR_UART1 15 -#define CLK_IFR_GCE_26M 16 -#define CLK_IFR_CQ_DMA_FPC 17 -#define CLK_IFR_BTIF 18 -#define CLK_IFR_SPI0 19 -#define CLK_IFR_MSDC0 20 -#define CLK_IFR_MSDC1 21 -#define CLK_IFR_TRNG 22 -#define CLK_IFR_AUXADC 23 -#define CLK_IFR_CCIF1_AP 24 -#define CLK_IFR_CCIF1_MD 25 -#define CLK_IFR_AUXADC_MD 26 -#define CLK_IFR_AP_DMA 27 -#define CLK_IFR_DEVICE_APC 28 -#define CLK_IFR_CCIF_AP 29 -#define CLK_IFR_AUDIO 30 -#define CLK_IFR_CCIF_MD 31 -#define CLK_IFR_RG_PWM_FBCLK6 32 -#define CLK_IFR_DISP_PWM 33 -#define CLK_IFR_CLDMA_BCLK 34 -#define CLK_IFR_AUDIO_26M_BCLK 35 -#define CLK_IFR_SPI1 36 -#define CLK_IFR_I2C4 37 -#define CLK_IFR_SPI2 38 -#define CLK_IFR_SPI3 39 -#define CLK_IFR_I2C5 40 -#define CLK_IFR_I2C5_ARBITER 41 -#define CLK_IFR_I2C5_IMM 42 -#define CLK_IFR_I2C1_ARBITER 43 -#define CLK_IFR_I2C1_IMM 44 -#define CLK_IFR_I2C2_ARBITER 45 -#define CLK_IFR_I2C2_IMM 46 -#define CLK_IFR_SPI4 47 -#define CLK_IFR_SPI5 48 -#define CLK_IFR_CQ_DMA 49 -#define CLK_IFR_FAES_FDE 50 -#define CLK_IFR_MSDC0_SELF 51 -#define CLK_IFR_MSDC1_SELF 52 -#define CLK_IFR_I2C6 53 -#define CLK_IFR_AP_MSDC0 54 -#define CLK_IFR_MD_MSDC0 55 -#define CLK_IFR_MSDC0_SRC 56 -#define CLK_IFR_MSDC1_SRC 57 -#define CLK_IFR_AES_TOP0_BCLK 58 -#define CLK_IFR_MCU_PM_BCLK 59 -#define CLK_IFR_CCIF2_AP 60 -#define CLK_IFR_CCIF2_MD 61 -#define CLK_IFR_CCIF3_AP 62 -#define CLK_IFR_CCIF3_MD 63 -#define CLK_IFR_NR_CLK 64 +#define CLK_IFR_PMIC_AP 0 +#define CLK_IFR_ICUSB 1 +#define CLK_IFR_GCE 2 +#define CLK_IFR_THERM 3 +#define CLK_IFR_I2C_AP 4 +#define CLK_IFR_I2C_CCU 5 +#define CLK_IFR_I2C_SSPM 6 +#define CLK_IFR_I2C_RSV 7 +#define CLK_IFR_PWM_HCLK 8 +#define CLK_IFR_PWM1 9 +#define CLK_IFR_PWM2 10 +#define CLK_IFR_PWM3 11 +#define CLK_IFR_PWM4 12 +#define CLK_IFR_PWM5 13 +#define CLK_IFR_PWM 14 +#define CLK_IFR_UART0 15 +#define CLK_IFR_UART1 16 +#define CLK_IFR_GCE_26M 17 +#define CLK_IFR_CQ_DMA_FPC 18 +#define CLK_IFR_BTIF 19 +#define CLK_IFR_SPI0 20 +#define CLK_IFR_MSDC0 21 +#define CLK_IFR_MSDC1 22 +#define CLK_IFR_TRNG 23 +#define CLK_IFR_AUXADC 24 +#define CLK_IFR_CCIF1_AP 25 +#define CLK_IFR_CCIF1_MD 26 +#define CLK_IFR_AUXADC_MD 27 +#define CLK_IFR_AP_DMA 28 +#define CLK_IFR_DEVICE_APC 29 +#define CLK_IFR_CCIF_AP 30 +#define CLK_IFR_AUDIO 31 +#define CLK_IFR_CCIF_MD 32 +#define CLK_IFR_RG_PWM_FBCLK6 33 +#define CLK_IFR_DISP_PWM 34 +#define CLK_IFR_CLDMA_BCLK 35 +#define CLK_IFR_AUDIO_26M_BCLK 36 +#define CLK_IFR_SPI1 37 +#define CLK_IFR_I2C4 38 +#define CLK_IFR_SPI2 39 +#define CLK_IFR_SPI3 40 +#define CLK_IFR_I2C5 41 +#define CLK_IFR_I2C5_ARBITER 42 +#define CLK_IFR_I2C5_IMM 43 +#define CLK_IFR_I2C1_ARBITER 44 +#define CLK_IFR_I2C1_IMM 45 +#define CLK_IFR_I2C2_ARBITER 46 +#define CLK_IFR_I2C2_IMM 47 +#define CLK_IFR_SPI4 48 +#define CLK_IFR_SPI5 49 +#define CLK_IFR_CQ_DMA 50 +#define CLK_IFR_FAES_FDE 51 +#define CLK_IFR_MSDC0_SELF 52 +#define CLK_IFR_MSDC1_SELF 53 +#define CLK_IFR_I2C6 54 +#define CLK_IFR_AP_MSDC0 55 +#define CLK_IFR_MD_MSDC0 56 +#define CLK_IFR_MSDC0_SRC 57 +#define CLK_IFR_MSDC1_SRC 58 +#define CLK_IFR_AES_TOP0_BCLK 59 +#define CLK_IFR_MCU_PM_BCLK 60 +#define CLK_IFR_CCIF2_AP 61 +#define CLK_IFR_CCIF2_MD 62 +#define CLK_IFR_CCIF3_AP 63 +#define CLK_IFR_CCIF3_MD 64 +#define CLK_IFR_NR_CLK 65 =20 /* AUDIO */ #define CLK_AUDIO_AFE 0 --=20 2.45.2 From nobody Thu Sep 19 23:10:36 2024 Received: from fallback24.i.mail.ru (fallback24.i.mail.ru [79.137.243.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2B548405D; 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Mon, 29 Jul 2024 10:35:34 +0300 From: Arseniy Velikanov To: mturquette@baylibre.com, sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, sean.wang@kernel.org, linus.walleij@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, frank.li@vivo.com, jiasheng@iscas.ac.cn, mars.cheng@mediatek.com, owen.chen@mediatek.com, macpaul.lin@mediatek.com, zh.chen@mediatek.com, argus.lin@mediatek.com Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Arseniy Velikanov Subject: [PATCH 2/5] clk: mediatek: mt6765: Add missing PMIC clock Date: Mon, 29 Jul 2024 11:34:25 +0400 Message-ID: <20240729073428.28983-3-me@adomerle.xyz> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240729073428.28983-1-me@adomerle.xyz> References: <20240729073428.28983-1-me@adomerle.xyz> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mailru-Src: smtp X-7564579A: 78E4E2B564C1792B X-77F55803: 4F1203BC0FB41BD9000B6812E77BE1C61A13D99F4944E7212A013F29C7F5C920182A05F5380850404D53ABDB57B21B8F3DE06ABAFEAF6705BAD916B310CA54E9303324A9B5BFDD325DA98F1BEDE0FAFA X-7FA49CB5: FF5795518A3D127A4AD6D5ED66289B5278DA827A17800CE7956F10FFCC7409BAEA1F7E6F0F101C67BD4B6F7A4D31EC0BCC500DACC3FED6E28638F802B75D45FF8AA50765F79006373103A56A89D9083FEA1F7E6F0F101C6723150C8DA25C47586E58E00D9D99D84E1BDDB23E98D2D38B043BF0FB74779F364D9CEBC3CFD6B8DC8B0FA825F8A70847059FB8DEF563170EA471835C12D1D9774AD6D5ED66289B5278DA827A17800CE71DD432BB81541BCF9FA2833FD35BB23D2EF20D2F80756B5F868A13BD56FB6657A471835C12D1D977725E5C173C3A84C3BD39A56654533F91117882F4460429728AD0CFFFB425014E868A13BD56FB6657D81D268191BDAD3DC09775C1D3CA48CF8C9B7DB6C49B7CEFBA3038C0950A5D36C8A9BA7A39EFB766D91E3A1F190DE8FDBA3038C0950A5D36D5E8D9A59859A8B69D9A99123495817A76E601842F6C81A1F004C906525384303E02D724532EE2C3F43C7A68FF6260569E8FC8737B5C2249EC8D19AE6D49635B68655334FD4449CB9ECD01F8117BC8BEAAAE862A0553A39223F8577A6DFFEA7CB23BE56FCC6FEFED43847C11F186F3C59DAA53EE0834AAEE X-C1DE0DAB: 0D63561A33F958A5975FF99ACDBD4C1C5002B1117B3ED6961C112C838BE192DA69995D676B7B4CBE823CB91A9FED034534781492E4B8EEAD69BF13FED57427F1C79554A2A72441328621D336A7BC284946AD531847A6065A535571D14F44ED41 X-C8649E89: 1C3962B70DF3F0ADE00A9FD3E00BEEDF77DD89D51EBB7742D3581295AF09D3DF87807E0823442EA2ED31085941D9CD0AF7F820E7B07EA4CF339F6C03A655D4025E4C9CB6EC7E2D2E0436D35C90D4EF0AFEBB18B2B510D9E0ECCBE4C437D6579C67C7AAC6E25A208678E18BF391248B5AFEDD108130C0427CFAB615D4A583E39522BA058254B804A102C26D483E81D6BE44BE0F8B58F75087CBB04030989F1EE011FE023E09B2D9C0 X-D57D3AED: 3ZO7eAau8CL7WIMRKs4sN3D3tLDjz0dLbV79QFUyzQ2Ujvy7cMT6pYYqY16iZVKkSc3dCLJ7zSJH7+u4VD18S7Vl4ZUrpaVfd2+vE6kuoey4m4VkSEu530nj6fImhcD4MUrOEAnl0W826KZ9Q+tr5ycPtXkTV4k65bRjmOUUP8cvGozZ33TWg5HZplvhhXbhDGzqmQDTd6OAevLeAnq3Ra9uf7zvY2zzsIhlcp/Y7m53TZgf2aB4JOg4gkr2biojX2k8aL79D6ULtCaxUqIPEQ== X-Mailru-Sender: 5DE64BD8B4008F63F32F89B2E510BB542337E882BFF2C65DB951B70A5BD4BD8E8E87E983BFFB9F4DB9A8FEFFB5F7F2D53B9265ADAFE7D7E06F53C80213D1719CA6FC796F43705345A9EF9D9C6A90DD94D3D6663D5D4272A7B4A721A3011E896F X-Mras: Ok X-7564579A: 646B95376F6C166E X-77F55803: 6242723A09DB00B431B8944160407DD0558ADADE14CD5136C862D2A3006641E368F3CF0E9FE49B69BA651B92B2A570CD9187EB2F77E968FB8F265BACD459A333ED86E6C7479721EA X-7FA49CB5: 0D63561A33F958A587EC2158EBC1702CA1C8A1B6B60FCE89C09569DA583CB3248941B15DA834481FA18204E546F3947CBA7556051D6825FBF6B57BC7E64490618DEB871D839B7333395957E7521B51C2DFABB839C843B9C08941B15DA834481F8AA50765F7900637889750A55773577B389733CBF5DBD5E9B5C8C57E37DE458BD96E472CDF7238E0725E5C173C3A84C3DD19ECFA348986C535872C767BF85DA2F004C90652538430E4A6367B16DE6309 X-D57D3AED: 3ZO7eAau8CL7WIMRKs4sN3D3tLDjz0dLbV79QFUyzQ2Ujvy7cMT6pYYqY16iZVKkSc3dCLJ7zSJH7+u4VD18S7Vl4ZUrpaVfd2+vE6kuoey4m4VkSEu530nj6fImhcD4MUrOEAnl0W826KZ9Q+tr5ycPtXkTV4k65bRjmOUUP8cvGozZ33TWg5HZplvhhXbhDGzqmQDTd6OAevLeAnq3Ra9uf7zvY2zzsIhlcp/Y7m53TZgf2aB4JOg4gkr2biojX2k8aL79D6WItejNFuIZdQ== X-Mailru-MI: 8000000000000800 X-Mras: Ok Content-Type: text/plain; charset="utf-8" Add PWRAP gate Fixes: 1aca9939bf72 ("clk: mediatek: Add MT6765 clock support") Signed-off-by: Arseniy Velikanov --- drivers/clk/mediatek/clk-mt6765.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-m= t6765.c index d53731e7933f..4f03a0df4ff0 100644 --- a/drivers/clk/mediatek/clk-mt6765.c +++ b/drivers/clk/mediatek/clk-mt6765.c @@ -559,6 +559,7 @@ static const struct mtk_gate ifr_clks[] =3D { /* INFRA_TOPAXI */ /* INFRA PERI */ /* INFRA mode 0 */ + GATE_IFR2(CLK_IFR_PMIC_AP, "ifr_pmic_ap", "axi_ck", 1), GATE_IFR2(CLK_IFR_ICUSB, "ifr_icusb", "axi_ck", 8), GATE_IFR2(CLK_IFR_GCE, "ifr_gce", "axi_ck", 9), GATE_IFR2(CLK_IFR_THERM, "ifr_therm", "axi_ck", 10), --=20 2.45.2 From nobody Thu Sep 19 23:10:36 2024 Received: from fallback23.i.mail.ru (fallback23.i.mail.ru [79.137.243.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 117EA8405D; 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Mon, 29 Jul 2024 10:35:54 +0300 From: Arseniy Velikanov To: mturquette@baylibre.com, sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, sean.wang@kernel.org, linus.walleij@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, frank.li@vivo.com, jiasheng@iscas.ac.cn, mars.cheng@mediatek.com, owen.chen@mediatek.com, macpaul.lin@mediatek.com, zh.chen@mediatek.com, argus.lin@mediatek.com Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Arseniy Velikanov Subject: [PATCH 3/5] pinctrl: mediatek: mt6765: Add virtual GPIOs Date: Mon, 29 Jul 2024 11:34:26 +0400 Message-ID: <20240729073428.28983-4-me@adomerle.xyz> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240729073428.28983-1-me@adomerle.xyz> References: <20240729073428.28983-1-me@adomerle.xyz> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mailru-Src: smtp X-7564579A: B8F34718100C35BD X-77F55803: 4F1203BC0FB41BD9000B6812E77BE1C6F0D221D1B7CB84E2160E2B5FE815AD3B182A05F53808504070ED64680FE505633DE06ABAFEAF6705569D5C545E49AD31303324A9B5BFDD32B323337538F1B82C X-7FA49CB5: FF5795518A3D127A4AD6D5ED66289B5278DA827A17800CE70EEC24FFE855BCBBC2099A533E45F2D0395957E7521B51C2CFCAF695D4D8E9FCEA1F7E6F0F101C6778DA827A17800CE74CC7A12EE14DE72EEA1F7E6F0F101C6723150C8DA25C47586E58E00D9D99D84E1BDDB23E98D2D38B043BF0FB74779F36D7040FD6C795E0D58B0FA825F8A708479DF002D5AC07DD35A471835C12D1D9774AD6D5ED66289B5278DA827A17800CE7212612128AA291179FA2833FD35BB23D2EF20D2F80756B5F868A13BD56FB6657A471835C12D1D977725E5C173C3A84C3CF36E64A7E3F8E58117882F4460429728AD0CFFFB425014E868A13BD56FB6657D81D268191BDAD3DC09775C1D3CA48CF043DDA2F55BC478EBA3038C0950A5D36C8A9BA7A39EFB766D91E3A1F190DE8FDBA3038C0950A5D36D5E8D9A59859A8B6A44FC0728E0BEE5076E601842F6C81A1F004C906525384303E02D724532EE2C3F43C7A68FF6260569E8FC8737B5C2249EC8D19AE6D49635B68655334FD4449CB9ECD01F8117BC8BEAAAE862A0553A39223F8577A6DFFEA7CB23BE56FCC6FEFED43847C11F186F3C59DAA53EE0834AAEE X-C1DE0DAB: 0D63561A33F958A57D5381FE4AFA73195002B1117B3ED696AEADDBF43329A05C715D9AB585B0EB04823CB91A9FED034534781492E4B8EEAD9CFA8CFAC159CE19C79554A2A72441328621D336A7BC284946AD531847A6065A535571D14F44ED41 X-C8649E89: 1C3962B70DF3F0ADE00A9FD3E00BEEDF77DD89D51EBB7742D3581295AF09D3DF87807E0823442EA2ED31085941D9CD0AF7F820E7B07EA4CF9917B871B94905D69EECD606C3E2E4C9B2A5DCBF1DDA7D096B07566F282BD1DACBE0296D7E8D7E7C67C7AAC6E25A208654E82B7864EB9E77FEDD108130C0427CA650E05A2CE5F5DC22BA058254B804A102C26D483E81D6BE44BE0F8B58F75087CBB04030989F1EE011FE023E09B2D9C0 X-D57D3AED: 3ZO7eAau8CL7WIMRKs4sN3D3tLDjz0dLbV79QFUyzQ2Ujvy7cMT6pYYqY16iZVKkSc3dCLJ7zSJH7+u4VD18S7Vl4ZUrpaVfd2+vE6kuoey4m4VkSEu530nj6fImhcD4MUrOEAnl0W826KZ9Q+tr5ycPtXkTV4k65bRjmOUUP8cvGozZ33TWg5HZplvhhXbhDGzqmQDTd6OAevLeAnq3Ra9uf7zvY2zzsIhlcp/Y7m53TZgf2aB4JOg4gkr2biojX2k8aL79D6WItejNFuIZdQ== X-Mailru-Sender: 5DE64BD8B4008F63F32F89B2E510BB54953AE6F1ABEFA2EDB951B70A5BD4BD8EAAC38112D6C17A550D95629463F16A6A3B9265ADAFE7D7E06F53C80213D1719CA6FC796F43705345A9EF9D9C6A90DD94D3D6663D5D4272A7B4A721A3011E896F X-Mras: Ok X-7564579A: 646B95376F6C166E X-77F55803: 6242723A09DB00B431B8944160407DD0C2EAA1E6BA7F9BE034EB9672DF358C7268F3CF0E9FE49B69BA651B92B2A570CDFA13EC145ADEB46B10EC71622DD18A7315255483CB426599 X-7FA49CB5: 0D63561A33F958A589323A742A0C511558D4370723787B0B6D208F3F2A12F1508941B15DA834481FA18204E546F3947CFE0D02E6309259D2F6B57BC7E64490618DEB871D839B7333395957E7521B51C2DFABB839C843B9C08941B15DA834481F8AA50765F79006371E900BC921822949389733CBF5DBD5E9B5C8C57E37DE458BD96E472CDF7238E0725E5C173C3A84C3BAD564E72A87595935872C767BF85DA2F004C90652538430E4A6367B16DE6309 X-D57D3AED: 3ZO7eAau8CL7WIMRKs4sN3D3tLDjz0dLbV79QFUyzQ2Ujvy7cMT6pYYqY16iZVKkSc3dCLJ7zSJH7+u4VD18S7Vl4ZUrpaVfd2+vE6kuoey4m4VkSEu530nj6fImhcD4MUrOEAnl0W826KZ9Q+tr5ycPtXkTV4k65bRjmOUUP8cvGozZ33TWg5HZplvhhXbhDGzqmQDTd6OAevLeAnq3Ra9uf7zvY2zzsIhlcp/Y7m53TZgf2aB4JOg4gkr2biojX2k8aL79D6XZ5YEio6WQfw== X-Mailru-MI: 8000000000000800 X-Mras: Ok Content-Type: text/plain; charset="utf-8" Add EINT-only virtual GPIOs as done for MT6735 These pins are needed at least for PWRAP Fixes: 477fecee7ca9 ("pinctrl: mediatek: add MT6765 pinctrl driver") Signed-off-by: Arseniy Velikanov --- drivers/pinctrl/mediatek/pinctrl-mtk-mt6765.h | 66 +++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6765.h b/drivers/pinctr= l/mediatek/pinctrl-mtk-mt6765.h index 772563720461..070af420333b 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6765.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6765.h @@ -1749,6 +1749,72 @@ static struct mtk_pin_desc mtk_pins_mt6765[] =3D { DRV_GRP4, MTK_FUNCTION(0, "GPIO179") ), + MTK_PIN( + 180, "GPIO180", + MTK_EINT_FUNCTION(0, 144), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 181, "GPIO181", + MTK_EINT_FUNCTION(0, 145), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 182, "GPIO182", + MTK_EINT_FUNCTION(0, 152), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 183, "GPIO183", + MTK_EINT_FUNCTION(0, 153), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 184, "GPIO184", + MTK_EINT_FUNCTION(0, 154), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 185, "GPIO185", + MTK_EINT_FUNCTION(0, 155), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 186, "GPIO186", + MTK_EINT_FUNCTION(0, 156), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 187, "GPIO187", + MTK_EINT_FUNCTION(0, 157), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 188, "GPIO188", + MTK_EINT_FUNCTION(0, 158), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 189, "GPIO189", + MTK_EINT_FUNCTION(0, 159), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 190, "GPIO190", + MTK_EINT_FUNCTION(0, 147), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), }; 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Received: by exim-smtp-868bf69f6c-zg7fr with esmtpa (envelope-from ) id 1sYKvP-00000000275-0PCY; Mon, 29 Jul 2024 10:36:07 +0300 From: Arseniy Velikanov To: mturquette@baylibre.com, sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, sean.wang@kernel.org, linus.walleij@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, frank.li@vivo.com, jiasheng@iscas.ac.cn, mars.cheng@mediatek.com, owen.chen@mediatek.com, macpaul.lin@mediatek.com, zh.chen@mediatek.com, argus.lin@mediatek.com Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Arseniy Velikanov Subject: [PATCH 4/5] dt-bindings: pinctrl: mediatek: Add bindings for MT6765 pin controller Date: Mon, 29 Jul 2024 11:34:27 +0400 Message-ID: <20240729073428.28983-5-me@adomerle.xyz> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240729073428.28983-1-me@adomerle.xyz> References: <20240729073428.28983-1-me@adomerle.xyz> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mailru-Src: smtp X-7564579A: B8F34718100C35BD X-77F55803: 4F1203BC0FB41BD9000B6812E77BE1C65D76B8F852291B0987B035B9E54BA07F182A05F5380850402AF60E02BEF481B63DE06ABAFEAF6705DF43CA416A8E8F76303324A9B5BFDD32F84BCC1498F71492 X-7FA49CB5: FF5795518A3D127A4AD6D5ED66289B5278DA827A17800CE73394B2E44CDCD4BFEA1F7E6F0F101C67BD4B6F7A4D31EC0BCC500DACC3FED6E28638F802B75D45FF8AA50765F7900637EFBEC025CA971C75EA1F7E6F0F101C6723150C8DA25C47586E58E00D9D99D84E1BDDB23E98D2D38B043BF0FB74779F36D8F50C743EBC7DDD8B0FA825F8A70847A53C6DE59553C0BCA471835C12D1D9774AD6D5ED66289B5278DA827A17800CE77E7E81EEA8A9722B8941B15DA834481FCF19DD082D7633A0EF3E4896CB9E6436389733CBF5DBD5E9D5E8D9A59859A8B6E232F00D8D26902CA471835C12D1D977C4224003CC836476EB9C4185024447017B076A6E789B0E975F5C1EE8F4F765FCA94E62DB9D9E192FD81D268191BDAD3DBD4B6F7A4D31EC0BE2F48590F00D11D6D81D268191BDAD3D78DA827A17800CE76FBA8D0025B7BC2CCD04E86FAF290E2DB606B96278B59C421DD303D21008E29813377AFFFEAFD269A417C69337E82CC2E827F84554CEF50127C277FBC8AE2E8BA83251EDC214901ED5E8D9A59859A8B6C44E7F8E725E999E089D37D7C0E48F6C5571747095F342E88FB05168BE4CE3AF X-C1DE0DAB: 0D63561A33F958A577E565F8ACFA91BE5002B1117B3ED696E92EC14BEEFE1333CCE9A60C8CB01D7C823CB91A9FED034534781492E4B8EEAD32B039D842AF0B7EF36E2E0160E5C55395B8A2A0B6518DF68C46860778A80D548E8926FB43031F38 X-C8649E89: 1C3962B70DF3F0ADE00A9FD3E00BEEDF77DD89D51EBB7742D3581295AF09D3DF87807E0823442EA2ED31085941D9CD0AF7F820E7B07EA4CFD3449D6920BCE9A23454FF8B837CEB5B40AB1EC9A7F1209DC49FB1C8B4E73C12C150D9F1A636644567C7AAC6E25A20865798CE78BB208F19FEDD108130C0427C8648C8147595DBE922BA058254B804A102C26D483E81D6BE44BE0F8B58F75087CBB04030989F1EE011FE023E09B2D9C0 X-D57D3AED: 3ZO7eAau8CL7WIMRKs4sN3D3tLDjz0dLbV79QFUyzQ2Ujvy7cMT6pYYqY16iZVKkSc3dCLJ7zSJH7+u4VD18S7Vl4ZUrpaVfd2+vE6kuoey4m4VkSEu530nj6fImhcD4MUrOEAnl0W826KZ9Q+tr5ycPtXkTV4k65bRjmOUUP8cvGozZ33TWg5HZplvhhXbhDGzqmQDTd6OAevLeAnq3Ra9uf7zvY2zzsIhlcp/Y7m53TZgf2aB4JOg4gkr2biojX2k8aL79D6VfjMduo+5ntQ== X-Mailru-Sender: 5DE64BD8B4008F63F32F89B2E510BB54BB09E8D1052A36F9B951B70A5BD4BD8E038A0AEC56329D40E28E2421BF3B429A3B9265ADAFE7D7E06F53C80213D1719CA6FC796F43705345A9EF9D9C6A90DD94D3D6663D5D4272A7B4A721A3011E896F X-Mras: Ok X-7564579A: B8F34718100C35BD X-77F55803: 6242723A09DB00B431B8944160407DD089A7AE0D179B51610CF417BBF57F2AD368F3CF0E9FE49B69BA651B92B2A570CD6BFBBF9BFDB5FAB4EA3F48EEFBC85EB079327D12C2A9DDC0 X-7FA49CB5: 0D63561A33F958A57BF9EAE4CF7431BB6371CF55DAB3C129A53A788858683E388941B15DA834481FA18204E546F3947C062BEEFFB5F8EA3EF6B57BC7E64490618DEB871D839B7333395957E7521B51C2DFABB839C843B9C08941B15DA834481F8AA50765F7900637D0FEED2715E18529389733CBF5DBD5E9B5C8C57E37DE458BD96E472CDF7238E0725E5C173C3A84C306E3C6E93C569A9E089D37D7C0E48F6C5571747095F342E88FB05168BE4CE3AF X-D57D3AED: 3ZO7eAau8CL7WIMRKs4sN3D3tLDjz0dLbV79QFUyzQ2Ujvy7cMT6pYYqY16iZVKkSc3dCLJ7zSJH7+u4VD18S7Vl4ZUrpaVfd2+vE6kuoey4m4VkSEu530nj6fImhcD4MUrOEAnl0W826KZ9Q+tr5ycPtXkTV4k65bRjmOUUP8cvGozZ33TWg5HZplvhhXbhDGzqmQDTd6OAevLeAnq3Ra9uf7zvY2zzsIhlcp/Y7m53TZgf2aB4JOg4gkr2biojX2k8aL79D6WagkjG00DScQ== X-Mailru-MI: 8000000000000800 X-Mras: Ok Content-Type: text/plain; charset="utf-8" Add DT bindings for the MT6765 pin controller, which consist of macros to be used as values for the pinmux property. Each macro corresponds to a unique possible pin-function combinations. Signed-off-by: Arseniy Velikanov Reviewed-by: AngeloGioacchino Del Regno --- .../pinctrl/mediatek,mt6765-pinfunc.h | 1025 +++++++++++++++++ 1 file changed, 1025 insertions(+) create mode 100644 include/dt-bindings/pinctrl/mediatek,mt6765-pinfunc.h diff --git a/include/dt-bindings/pinctrl/mediatek,mt6765-pinfunc.h b/includ= e/dt-bindings/pinctrl/mediatek,mt6765-pinfunc.h new file mode 100644 index 000000000000..3f261cadc174 --- /dev/null +++ b/include/dt-bindings/pinctrl/mediatek,mt6765-pinfunc.h @@ -0,0 +1,1025 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 Arseniy Velikanov + */ + +#ifndef __MEDIATEK_MT6765_PINFUNC_H +#define __MEDIATEK_MT6765_PINFUNC_H + +#include "mt65xx.h" + +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define PINMUX_GPIO0__FUNC_UTXD1 (MTK_PIN_NO(0) | 1) +#define PINMUX_GPIO0__FUNC_CLKM0 (MTK_PIN_NO(0) | 2) +#define PINMUX_GPIO0__FUNC_MD_INT0 (MTK_PIN_NO(0) | 3) +#define PINMUX_GPIO0__FUNC_I2S0_MCK (MTK_PIN_NO(0) | 4) +#define PINMUX_GPIO0__FUNC_MD_UTXD1 (MTK_PIN_NO(0) | 5) +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 6) +#define PINMUX_GPIO0__FUNC_DBG_MON_B9 (MTK_PIN_NO(0) | 7) + +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define PINMUX_GPIO1__FUNC_URXD1 (MTK_PIN_NO(1) | 1) +#define PINMUX_GPIO1__FUNC_CLKM1 (MTK_PIN_NO(1) | 2) +#define PINMUX_GPIO1__FUNC_I2S0_BCK (MTK_PIN_NO(1) | 4) +#define PINMUX_GPIO1__FUNC_MD_URXD1 (MTK_PIN_NO(1) | 5) +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 6) +#define PINMUX_GPIO1__FUNC_DBG_MON_B10 (MTK_PIN_NO(1) | 7) + +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define PINMUX_GPIO2__FUNC_UCTS0 (MTK_PIN_NO(2) | 1) +#define PINMUX_GPIO2__FUNC_CLKM2 (MTK_PIN_NO(2) | 2) +#define PINMUX_GPIO2__FUNC_UTXD1 (MTK_PIN_NO(2) | 3) +#define PINMUX_GPIO2__FUNC_I2S0_LRCK (MTK_PIN_NO(2) | 4) +#define PINMUX_GPIO2__FUNC_ANT_SEL6 (MTK_PIN_NO(2) | 5) +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 6) +#define PINMUX_GPIO2__FUNC_DBG_MON_B11 (MTK_PIN_NO(2) | 7) + +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define PINMUX_GPIO3__FUNC_URTS0 (MTK_PIN_NO(3) | 1) +#define PINMUX_GPIO3__FUNC_CLKM3 (MTK_PIN_NO(3) | 2) +#define PINMUX_GPIO3__FUNC_URXD1 (MTK_PIN_NO(3) | 3) +#define PINMUX_GPIO3__FUNC_I2S0_DI (MTK_PIN_NO(3) | 4) +#define PINMUX_GPIO3__FUNC_ANT_SEL7 (MTK_PIN_NO(3) | 5) +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 6) +#define PINMUX_GPIO3__FUNC_DBG_MON_B12 (MTK_PIN_NO(3) | 7) + +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define PINMUX_GPIO4__FUNC_SPI1_B_MI (MTK_PIN_NO(4) | 1) +#define PINMUX_GPIO4__FUNC_SCP_SPI1_MI (MTK_PIN_NO(4) | 2) +#define PINMUX_GPIO4__FUNC_UCTS0 (MTK_PIN_NO(4) | 3) +#define PINMUX_GPIO4__FUNC_I2S3_MCK (MTK_PIN_NO(4) | 4) +#define PINMUX_GPIO4__FUNC_SSPM_URXD_AO (MTK_PIN_NO(4) | 5) +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6) + +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define PINMUX_GPIO5__FUNC_SPI1_B_CSB (MTK_PIN_NO(5) | 1) +#define PINMUX_GPIO5__FUNC_SCP_SPI1_CS (MTK_PIN_NO(5) | 2) +#define PINMUX_GPIO5__FUNC_URTS0 (MTK_PIN_NO(5) | 3) +#define PINMUX_GPIO5__FUNC_I2S3_BCK (MTK_PIN_NO(5) | 4) +#define PINMUX_GPIO5__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(5) | 5) +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6) + +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define PINMUX_GPIO6__FUNC_SPI1_B_MO (MTK_PIN_NO(6) | 1) +#define PINMUX_GPIO6__FUNC_SCP_SPI1_MO (MTK_PIN_NO(6) | 2) +#define PINMUX_GPIO6__FUNC_PWM0 (MTK_PIN_NO(6) | 3) +#define PINMUX_GPIO6__FUNC_I2S3_LRCK (MTK_PIN_NO(6) | 4) +#define PINMUX_GPIO6__FUNC_MD_UTXD0 (MTK_PIN_NO(6) | 5) +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6) + +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define PINMUX_GPIO7__FUNC_SPI1_B_CLK (MTK_PIN_NO(7) | 1) +#define PINMUX_GPIO7__FUNC_SCP_SPI1_CK (MTK_PIN_NO(7) | 2) +#define PINMUX_GPIO7__FUNC_PWM1 (MTK_PIN_NO(7) | 3) +#define PINMUX_GPIO7__FUNC_I2S3_DO (MTK_PIN_NO(7) | 4) +#define PINMUX_GPIO7__FUNC_MD_URXD0 (MTK_PIN_NO(7) | 5) +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6) + +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define PINMUX_GPIO8__FUNC_UTXD1 (MTK_PIN_NO(8) | 1) +#define PINMUX_GPIO8__FUNC_SRCLKENAI0 (MTK_PIN_NO(8) | 2) +#define PINMUX_GPIO8__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(8) | 3) +#define PINMUX_GPIO8__FUNC_ANT_SEL3 (MTK_PIN_NO(8) | 4) +#define PINMUX_GPIO8__FUNC_MFG_JTAG_TRSTN (MTK_PIN_NO(8) | 5) +#define PINMUX_GPIO8__FUNC_I2S2_MCK (MTK_PIN_NO(8) | 6) +#define PINMUX_GPIO8__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(8) | 7) + +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define PINMUX_GPIO9__FUNC_MD_INT0 (MTK_PIN_NO(9) | 1) +#define PINMUX_GPIO9__FUNC_CMMCLK2 (MTK_PIN_NO(9) | 2) +#define PINMUX_GPIO9__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(9) | 3) +#define PINMUX_GPIO9__FUNC_IDDIG (MTK_PIN_NO(9) | 4) +#define PINMUX_GPIO9__FUNC_SDA_6306 (MTK_PIN_NO(9) | 5) +#define PINMUX_GPIO9__FUNC_MCUPM_JTAG_TRSTN (MTK_PIN_NO(9) | 6) +#define PINMUX_GPIO9__FUNC_DBG_MON_B22 (MTK_PIN_NO(9) | 7) + +#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define PINMUX_GPIO10__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(10) | 1) +#define PINMUX_GPIO10__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(10) | 3) +#define PINMUX_GPIO10__FUNC_SRCLKENAI1 (MTK_PIN_NO(10) | 4) +#define PINMUX_GPIO10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(10) | 5) +#define PINMUX_GPIO10__FUNC_CMVREF1 (MTK_PIN_NO(10) | 6) +#define PINMUX_GPIO10__FUNC_DBG_MON_B23 (MTK_PIN_NO(10) | 7) + +#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define PINMUX_GPIO11__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(11) | 1) +#define PINMUX_GPIO11__FUNC_CLKM3 (MTK_PIN_NO(11) | 2) +#define PINMUX_GPIO11__FUNC_ANT_SEL6 (MTK_PIN_NO(11) | 3) +#define PINMUX_GPIO11__FUNC_SRCLKENAI0 (MTK_PIN_NO(11) | 4) +#define PINMUX_GPIO11__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(11) | 5) +#define PINMUX_GPIO11__FUNC_UCTS1 (MTK_PIN_NO(11) | 6) +#define PINMUX_GPIO11__FUNC_DBG_MON_B24 (MTK_PIN_NO(11) | 7) + +#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define PINMUX_GPIO12__FUNC_PWM0 (MTK_PIN_NO(12) | 1) +#define PINMUX_GPIO12__FUNC_SRCLKENAI1 (MTK_PIN_NO(12) | 2) +#define PINMUX_GPIO12__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(12) | 3) +#define PINMUX_GPIO12__FUNC_MD_INT0 (MTK_PIN_NO(12) | 4) +#define PINMUX_GPIO12__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(12) | 5) +#define PINMUX_GPIO12__FUNC_URTS1 (MTK_PIN_NO(12) | 6) + +#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define PINMUX_GPIO13__FUNC_ANT_SEL0 (MTK_PIN_NO(13) | 1) +#define PINMUX_GPIO13__FUNC_SPI4_MI (MTK_PIN_NO(13) | 2) +#define PINMUX_GPIO13__FUNC_SCP_SPI0_MI (MTK_PIN_NO(13) | 3) +#define PINMUX_GPIO13__FUNC_MD_URXD0 (MTK_PIN_NO(13) | 4) +#define PINMUX_GPIO13__FUNC_CLKM0 (MTK_PIN_NO(13) | 5) +#define PINMUX_GPIO13__FUNC_I2S0_MCK (MTK_PIN_NO(13) | 6) +#define PINMUX_GPIO13__FUNC_DBG_MON_A0 (MTK_PIN_NO(13) | 7) + +#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define PINMUX_GPIO14__FUNC_ANT_SEL1 (MTK_PIN_NO(14) | 1) +#define PINMUX_GPIO14__FUNC_SPI4_CSB (MTK_PIN_NO(14) | 2) +#define PINMUX_GPIO14__FUNC_SCP_SPI0_CS (MTK_PIN_NO(14) | 3) +#define PINMUX_GPIO14__FUNC_MD_UTXD0 (MTK_PIN_NO(14) | 4) +#define PINMUX_GPIO14__FUNC_CLKM1 (MTK_PIN_NO(14) | 5) +#define PINMUX_GPIO14__FUNC_I2S0_BCK (MTK_PIN_NO(14) | 6) +#define PINMUX_GPIO14__FUNC_DBG_MON_A1 (MTK_PIN_NO(14) | 7) + +#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define PINMUX_GPIO15__FUNC_ANT_SEL2 (MTK_PIN_NO(15) | 1) +#define PINMUX_GPIO15__FUNC_SPI4_MO (MTK_PIN_NO(15) | 2) +#define PINMUX_GPIO15__FUNC_SCP_SPI0_MO (MTK_PIN_NO(15) | 3) +#define PINMUX_GPIO15__FUNC_MD_URXD1 (MTK_PIN_NO(15) | 4) +#define PINMUX_GPIO15__FUNC_CLKM2 (MTK_PIN_NO(15) | 5) +#define PINMUX_GPIO15__FUNC_I2S0_LRCK (MTK_PIN_NO(15) | 6) +#define PINMUX_GPIO15__FUNC_DBG_MON_A2 (MTK_PIN_NO(15) | 7) + +#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define PINMUX_GPIO16__FUNC_ANT_SEL3 (MTK_PIN_NO(16) | 1) +#define PINMUX_GPIO16__FUNC_SPI4_CLK (MTK_PIN_NO(16) | 2) +#define PINMUX_GPIO16__FUNC_SCP_SPI0_CK (MTK_PIN_NO(16) | 3) +#define PINMUX_GPIO16__FUNC_MD_UTXD1 (MTK_PIN_NO(16) | 4) +#define PINMUX_GPIO16__FUNC_CLKM3 (MTK_PIN_NO(16) | 5) +#define PINMUX_GPIO16__FUNC_I2S3_MCK (MTK_PIN_NO(16) | 6) +#define PINMUX_GPIO16__FUNC_DBG_MON_A3 (MTK_PIN_NO(16) | 7) + +#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define PINMUX_GPIO17__FUNC_ANT_SEL4 (MTK_PIN_NO(17) | 1) +#define PINMUX_GPIO17__FUNC_SPI2_MO (MTK_PIN_NO(17) | 2) +#define PINMUX_GPIO17__FUNC_SCP_SPI0_MO (MTK_PIN_NO(17) | 3) +#define PINMUX_GPIO17__FUNC_PWM1 (MTK_PIN_NO(17) | 4) +#define PINMUX_GPIO17__FUNC_IDDIG (MTK_PIN_NO(17) | 5) +#define PINMUX_GPIO17__FUNC_I2S0_DI (MTK_PIN_NO(17) | 6) +#define PINMUX_GPIO17__FUNC_DBG_MON_A4 (MTK_PIN_NO(17) | 7) + +#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define PINMUX_GPIO18__FUNC_ANT_SEL5 (MTK_PIN_NO(18) | 1) +#define PINMUX_GPIO18__FUNC_SPI2_CLK (MTK_PIN_NO(18) | 2) +#define PINMUX_GPIO18__FUNC_SCP_SPI0_CK (MTK_PIN_NO(18) | 3) +#define PINMUX_GPIO18__FUNC_MD_INT0 (MTK_PIN_NO(18) | 4) +#define PINMUX_GPIO18__FUNC_USB_DRVVBUS (MTK_PIN_NO(18) | 5) +#define PINMUX_GPIO18__FUNC_I2S3_BCK (MTK_PIN_NO(18) | 6) +#define PINMUX_GPIO18__FUNC_DBG_MON_A5 (MTK_PIN_NO(18) | 7) + +#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define PINMUX_GPIO19__FUNC_ANT_SEL6 (MTK_PIN_NO(19) | 1) +#define PINMUX_GPIO19__FUNC_SPI2_MI (MTK_PIN_NO(19) | 2) +#define PINMUX_GPIO19__FUNC_SCP_SPI0_MI (MTK_PIN_NO(19) | 3) +#define PINMUX_GPIO19__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(19) | 4) +#define PINMUX_GPIO19__FUNC_I2S3_LRCK (MTK_PIN_NO(19) | 6) +#define PINMUX_GPIO19__FUNC_DBG_MON_A6 (MTK_PIN_NO(19) | 7) + +#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define PINMUX_GPIO20__FUNC_ANT_SEL7 (MTK_PIN_NO(20) | 1) +#define PINMUX_GPIO20__FUNC_SPI2_CSB (MTK_PIN_NO(20) | 2) +#define PINMUX_GPIO20__FUNC_SCP_SPI0_CS (MTK_PIN_NO(20) | 3) +#define PINMUX_GPIO20__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(20) | 4) +#define PINMUX_GPIO20__FUNC_CMMCLK3 (MTK_PIN_NO(20) | 5) +#define PINMUX_GPIO20__FUNC_I2S3_DO (MTK_PIN_NO(20) | 6) +#define PINMUX_GPIO20__FUNC_DBG_MON_A7 (MTK_PIN_NO(20) | 7) + +#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define PINMUX_GPIO21__FUNC_SPI3_MI (MTK_PIN_NO(21) | 1) +#define PINMUX_GPIO21__FUNC_SRCLKENAI1 (MTK_PIN_NO(21) | 2) +#define PINMUX_GPIO21__FUNC_DAP_MD32_SWD (MTK_PIN_NO(21) | 3) +#define PINMUX_GPIO21__FUNC_CMVREF0 (MTK_PIN_NO(21) | 4) +#define PINMUX_GPIO21__FUNC_SCP_SPI0_MI (MTK_PIN_NO(21) | 5) +#define PINMUX_GPIO21__FUNC_I2S2_MCK (MTK_PIN_NO(21) | 6) +#define PINMUX_GPIO21__FUNC_DBG_MON_A8 (MTK_PIN_NO(21) | 7) + +#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define PINMUX_GPIO22__FUNC_SPI3_CSB (MTK_PIN_NO(22) | 1) +#define PINMUX_GPIO22__FUNC_SRCLKENAI0 (MTK_PIN_NO(22) | 2) +#define PINMUX_GPIO22__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(22) | 3) +#define PINMUX_GPIO22__FUNC_CMVREF1 (MTK_PIN_NO(22) | 4) +#define PINMUX_GPIO22__FUNC_SCP_SPI0_CS (MTK_PIN_NO(22) | 5) +#define PINMUX_GPIO22__FUNC_I2S2_BCK (MTK_PIN_NO(22) | 6) +#define PINMUX_GPIO22__FUNC_DBG_MON_A9 (MTK_PIN_NO(22) | 7) + +#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define PINMUX_GPIO23__FUNC_SPI3_MO (MTK_PIN_NO(23) | 1) +#define PINMUX_GPIO23__FUNC_PWM0 (MTK_PIN_NO(23) | 2) +#define PINMUX_GPIO23__FUNC_KPROW7 (MTK_PIN_NO(23) | 3) +#define PINMUX_GPIO23__FUNC_ANT_SEL3 (MTK_PIN_NO(23) | 4) +#define PINMUX_GPIO23__FUNC_SCP_SPI0_MO (MTK_PIN_NO(23) | 5) +#define PINMUX_GPIO23__FUNC_I2S2_LRCK (MTK_PIN_NO(23) | 6) +#define PINMUX_GPIO23__FUNC_DBG_MON_A10 (MTK_PIN_NO(23) | 7) + +#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define PINMUX_GPIO24__FUNC_SPI3_CLK (MTK_PIN_NO(24) | 1) +#define PINMUX_GPIO24__FUNC_UDI_TCK (MTK_PIN_NO(24) | 2) +#define PINMUX_GPIO24__FUNC_IO_JTAG_TCK (MTK_PIN_NO(24) | 3) +#define PINMUX_GPIO24__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(24) | 4) +#define PINMUX_GPIO24__FUNC_SCP_SPI0_CK (MTK_PIN_NO(24) | 5) +#define PINMUX_GPIO24__FUNC_I2S2_DI (MTK_PIN_NO(24) | 6) +#define PINMUX_GPIO24__FUNC_DBG_MON_A11 (MTK_PIN_NO(24) | 7) + +#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define PINMUX_GPIO25__FUNC_SPI1_A_MI (MTK_PIN_NO(25) | 1) +#define PINMUX_GPIO25__FUNC_UDI_TMS (MTK_PIN_NO(25) | 2) +#define PINMUX_GPIO25__FUNC_IO_JTAG_TMS (MTK_PIN_NO(25) | 3) +#define PINMUX_GPIO25__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(25) | 4) +#define PINMUX_GPIO25__FUNC_KPROW3 (MTK_PIN_NO(25) | 5) +#define PINMUX_GPIO25__FUNC_I2S1_MCK (MTK_PIN_NO(25) | 6) +#define PINMUX_GPIO25__FUNC_DBG_MON_A12 (MTK_PIN_NO(25) | 7) + +#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define PINMUX_GPIO26__FUNC_SPI1_A_CSB (MTK_PIN_NO(26) | 1) +#define PINMUX_GPIO26__FUNC_UDI_TDI (MTK_PIN_NO(26) | 2) +#define PINMUX_GPIO26__FUNC_IO_JTAG_TDI (MTK_PIN_NO(26) | 3) +#define PINMUX_GPIO26__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(26) | 4) +#define PINMUX_GPIO26__FUNC_KPROW4 (MTK_PIN_NO(26) | 5) +#define PINMUX_GPIO26__FUNC_I2S1_BCK (MTK_PIN_NO(26) | 6) +#define PINMUX_GPIO26__FUNC_DBG_MON_A13 (MTK_PIN_NO(26) | 7) + +#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define PINMUX_GPIO27__FUNC_SPI1_A_MO (MTK_PIN_NO(27) | 1) +#define PINMUX_GPIO27__FUNC_UDI_TDO (MTK_PIN_NO(27) | 2) +#define PINMUX_GPIO27__FUNC_IO_JTAG_TDO (MTK_PIN_NO(27) | 3) +#define PINMUX_GPIO27__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(27) | 4) +#define PINMUX_GPIO27__FUNC_KPROW5 (MTK_PIN_NO(27) | 5) +#define PINMUX_GPIO27__FUNC_I2S1_LRCK (MTK_PIN_NO(27) | 6) +#define PINMUX_GPIO27__FUNC_DBG_MON_A14 (MTK_PIN_NO(27) | 7) + +#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define PINMUX_GPIO28__FUNC_SPI1_A_CLK (MTK_PIN_NO(28) | 1) +#define PINMUX_GPIO28__FUNC_UDI_NTRST (MTK_PIN_NO(28) | 2) +#define PINMUX_GPIO28__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(28) | 3) +#define PINMUX_GPIO28__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(28) | 4) +#define PINMUX_GPIO28__FUNC_KPROW6 (MTK_PIN_NO(28) | 5) +#define PINMUX_GPIO28__FUNC_I2S1_DO (MTK_PIN_NO(28) | 6) +#define PINMUX_GPIO28__FUNC_DBG_MON_A15 (MTK_PIN_NO(28) | 7) + +#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define PINMUX_GPIO29__FUNC_MSDC1_CLK (MTK_PIN_NO(29) | 1) +#define PINMUX_GPIO29__FUNC_IO_JTAG_TCK (MTK_PIN_NO(29) | 2) +#define PINMUX_GPIO29__FUNC_UDI_TCK (MTK_PIN_NO(29) | 3) +#define PINMUX_GPIO29__FUNC_CONN_DSP_JCK (MTK_PIN_NO(29) | 4) +#define PINMUX_GPIO29__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(29) | 5) +#define PINMUX_GPIO29__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(29) | 6) +#define PINMUX_GPIO29__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(29) | 7) + +#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define PINMUX_GPIO30__FUNC_MSDC1_CMD (MTK_PIN_NO(30) | 1) +#define PINMUX_GPIO30__FUNC_IO_JTAG_TMS (MTK_PIN_NO(30) | 2) +#define PINMUX_GPIO30__FUNC_UDI_TMS (MTK_PIN_NO(30) | 3) +#define PINMUX_GPIO30__FUNC_CONN_DSP_JMS (MTK_PIN_NO(30) | 4) +#define PINMUX_GPIO30__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(30) | 5) +#define PINMUX_GPIO30__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(30) | 6) +#define PINMUX_GPIO30__FUNC_DAP_MD32_SWD (MTK_PIN_NO(30) | 7) + +#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define PINMUX_GPIO31__FUNC_MSDC1_DAT3 (MTK_PIN_NO(31) | 1) + +#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define PINMUX_GPIO32__FUNC_MSDC1_DAT0 (MTK_PIN_NO(32) | 1) +#define PINMUX_GPIO32__FUNC_IO_JTAG_TDI (MTK_PIN_NO(32) | 2) +#define PINMUX_GPIO32__FUNC_UDI_TDI (MTK_PIN_NO(32) | 3) +#define PINMUX_GPIO32__FUNC_CONN_DSP_JDI (MTK_PIN_NO(32) | 4) +#define PINMUX_GPIO32__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(32) | 5) + +#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define PINMUX_GPIO33__FUNC_MSDC1_DAT2 (MTK_PIN_NO(33) | 1) +#define PINMUX_GPIO33__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(33) | 2) +#define PINMUX_GPIO33__FUNC_UDI_NTRST (MTK_PIN_NO(33) | 3) +#define PINMUX_GPIO33__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(33) | 4) +#define PINMUX_GPIO33__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(33) | 5) + +#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define PINMUX_GPIO34__FUNC_MSDC1_DAT1 (MTK_PIN_NO(34) | 1) +#define PINMUX_GPIO34__FUNC_IO_JTAG_TDO (MTK_PIN_NO(34) | 2) +#define PINMUX_GPIO34__FUNC_UDI_TDO (MTK_PIN_NO(34) | 3) +#define PINMUX_GPIO34__FUNC_CONN_DSP_JDO (MTK_PIN_NO(34) | 4) +#define PINMUX_GPIO34__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(34) | 5) + +#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define PINMUX_GPIO35__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(35) | 1) +#define PINMUX_GPIO35__FUNC_CCU_JTAG_TDO (MTK_PIN_NO(35) | 2) +#define PINMUX_GPIO35__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(35) | 3) +#define PINMUX_GPIO35__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(35) | 5) +#define PINMUX_GPIO35__FUNC_CONN_DSP_JDO (MTK_PIN_NO(35) | 6) +#define PINMUX_GPIO35__FUNC_DBG_MON_A16 (MTK_PIN_NO(35) | 7) + +#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define PINMUX_GPIO36__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(36) | 1) +#define PINMUX_GPIO36__FUNC_CCU_JTAG_TMS (MTK_PIN_NO(36) | 2) +#define PINMUX_GPIO36__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(36) | 3) +#define PINMUX_GPIO36__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(36) | 4) +#define PINMUX_GPIO36__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(36) | 5) +#define PINMUX_GPIO36__FUNC_CONN_DSP_JMS (MTK_PIN_NO(36) | 6) +#define PINMUX_GPIO36__FUNC_DBG_MON_A17 (MTK_PIN_NO(36) | 7) + +#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define PINMUX_GPIO37__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(37) | 1) +#define PINMUX_GPIO37__FUNC_CCU_JTAG_TDI (MTK_PIN_NO(37) | 2) +#define PINMUX_GPIO37__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(37) | 3) +#define PINMUX_GPIO37__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(37) | 5) +#define PINMUX_GPIO37__FUNC_CONN_DSP_JDI (MTK_PIN_NO(37) | 6) +#define PINMUX_GPIO37__FUNC_DBG_MON_A18 (MTK_PIN_NO(37) | 7) + +#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define PINMUX_GPIO38__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(38) | 1) +#define PINMUX_GPIO38__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(38) | 3) +#define PINMUX_GPIO38__FUNC_DBG_MON_A19 (MTK_PIN_NO(38) | 7) + +#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define PINMUX_GPIO39__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(39) | 1) +#define PINMUX_GPIO39__FUNC_CCU_JTAG_TCK (MTK_PIN_NO(39) | 2) +#define PINMUX_GPIO39__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(39) | 3) +#define PINMUX_GPIO39__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(39) | 4) +#define PINMUX_GPIO39__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(39) | 5) +#define PINMUX_GPIO39__FUNC_CONN_DSP_JCK (MTK_PIN_NO(39) | 6) +#define PINMUX_GPIO39__FUNC_DBG_MON_A20 (MTK_PIN_NO(39) | 7) + +#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define PINMUX_GPIO40__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(40) | 1) +#define PINMUX_GPIO40__FUNC_CCU_JTAG_TRST (MTK_PIN_NO(40) | 2) +#define PINMUX_GPIO40__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(40) | 3) +#define PINMUX_GPIO40__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(40) | 5) +#define PINMUX_GPIO40__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(40) | 6) +#define PINMUX_GPIO40__FUNC_DBG_MON_A21 (MTK_PIN_NO(40) | 7) + +#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define PINMUX_GPIO41__FUNC_IDDIG (MTK_PIN_NO(41) | 1) +#define PINMUX_GPIO41__FUNC_URXD1 (MTK_PIN_NO(41) | 2) +#define PINMUX_GPIO41__FUNC_UCTS0 (MTK_PIN_NO(41) | 3) +#define PINMUX_GPIO41__FUNC_KPCOL2 (MTK_PIN_NO(41) | 4) +#define PINMUX_GPIO41__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(41) | 5) +#define PINMUX_GPIO41__FUNC_MD_INT0 (MTK_PIN_NO(41) | 6) +#define PINMUX_GPIO41__FUNC_DBG_MON_A22 (MTK_PIN_NO(41) | 7) + +#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define PINMUX_GPIO42__FUNC_USB_DRVVBUS (MTK_PIN_NO(42) | 1) +#define PINMUX_GPIO42__FUNC_UTXD1 (MTK_PIN_NO(42) | 2) +#define PINMUX_GPIO42__FUNC_URTS0 (MTK_PIN_NO(42) | 3) +#define PINMUX_GPIO42__FUNC_KPROW2 (MTK_PIN_NO(42) | 4) +#define PINMUX_GPIO42__FUNC_SSPM_URXD_AO (MTK_PIN_NO(42) | 5) +#define PINMUX_GPIO42__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(42) | 6) +#define PINMUX_GPIO42__FUNC_DBG_MON_A23 (MTK_PIN_NO(42) | 7) + +#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define PINMUX_GPIO43__FUNC_DISP_PWM (MTK_PIN_NO(43) | 1) +#define PINMUX_GPIO43__FUNC_DBG_MON_A24 (MTK_PIN_NO(43) | 7) + +#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define PINMUX_GPIO44__FUNC_DSI_TE (MTK_PIN_NO(44) | 1) +#define PINMUX_GPIO44__FUNC_DBG_MON_A25 (MTK_PIN_NO(44) | 7) + +#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define PINMUX_GPIO45__FUNC_LCM_RST (MTK_PIN_NO(45) | 1) +#define PINMUX_GPIO45__FUNC_DBG_MON_A26 (MTK_PIN_NO(45) | 7) + +#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define PINMUX_GPIO46__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(46) | 1) +#define PINMUX_GPIO46__FUNC_UCTS0 (MTK_PIN_NO(46) | 2) +#define PINMUX_GPIO46__FUNC_UCTS1 (MTK_PIN_NO(46) | 3) +#define PINMUX_GPIO46__FUNC_IDDIG (MTK_PIN_NO(46) | 4) +#define PINMUX_GPIO46__FUNC_SCL_6306 (MTK_PIN_NO(46) | 5) +#define PINMUX_GPIO46__FUNC_TP_UCTS1_AO (MTK_PIN_NO(46) | 6) +#define PINMUX_GPIO46__FUNC_DBG_MON_A27 (MTK_PIN_NO(46) | 7) + +#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define PINMUX_GPIO47__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(47) | 1) +#define PINMUX_GPIO47__FUNC_URTS0 (MTK_PIN_NO(47) | 2) +#define PINMUX_GPIO47__FUNC_URTS1 (MTK_PIN_NO(47) | 3) +#define PINMUX_GPIO47__FUNC_USB_DRVVBUS (MTK_PIN_NO(47) | 4) +#define PINMUX_GPIO47__FUNC_SDA_6306 (MTK_PIN_NO(47) | 5) +#define PINMUX_GPIO47__FUNC_TP_URTS1_AO (MTK_PIN_NO(47) | 6) +#define PINMUX_GPIO47__FUNC_DBG_MON_A28 (MTK_PIN_NO(47) | 7) + +#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define PINMUX_GPIO48__FUNC_SCL5 (MTK_PIN_NO(48) | 1) +#define PINMUX_GPIO48__FUNC_DBG_MON_A29 (MTK_PIN_NO(48) | 7) + +#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define PINMUX_GPIO49__FUNC_SDA5 (MTK_PIN_NO(49) | 1) +#define PINMUX_GPIO49__FUNC_DBG_MON_A30 (MTK_PIN_NO(49) | 7) + +#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define PINMUX_GPIO50__FUNC_SCL3 (MTK_PIN_NO(50) | 1) +#define PINMUX_GPIO50__FUNC_URXD1 (MTK_PIN_NO(50) | 2) +#define PINMUX_GPIO50__FUNC_MD_URXD1 (MTK_PIN_NO(50) | 3) +#define PINMUX_GPIO50__FUNC_SSPM_URXD_AO (MTK_PIN_NO(50) | 4) +#define PINMUX_GPIO50__FUNC_IDDIG (MTK_PIN_NO(50) | 5) +#define PINMUX_GPIO50__FUNC_TP_URXD1_AO (MTK_PIN_NO(50) | 6) +#define PINMUX_GPIO50__FUNC_DBG_MON_A31 (MTK_PIN_NO(50) | 7) + +#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define PINMUX_GPIO51__FUNC_SDA3 (MTK_PIN_NO(51) | 1) +#define PINMUX_GPIO51__FUNC_UTXD1 (MTK_PIN_NO(51) | 2) +#define PINMUX_GPIO51__FUNC_MD_UTXD1 (MTK_PIN_NO(51) | 3) +#define PINMUX_GPIO51__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(51) | 4) +#define PINMUX_GPIO51__FUNC_USB_DRVVBUS (MTK_PIN_NO(51) | 5) +#define PINMUX_GPIO51__FUNC_TP_UTXD1_AO (MTK_PIN_NO(51) | 6) +#define PINMUX_GPIO51__FUNC_DBG_MON_A32 (MTK_PIN_NO(51) | 7) + +#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define PINMUX_GPIO52__FUNC_BPI_BUS15 (MTK_PIN_NO(52) | 1) + +#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define PINMUX_GPIO53__FUNC_BPI_BUS13 (MTK_PIN_NO(53) | 1) + +#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define PINMUX_GPIO54__FUNC_BPI_BUS12 (MTK_PIN_NO(54) | 1) + +#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define PINMUX_GPIO55__FUNC_BPI_BUS8 (MTK_PIN_NO(55) | 1) + +#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define PINMUX_GPIO56__FUNC_BPI_BUS9 (MTK_PIN_NO(56) | 1) +#define PINMUX_GPIO56__FUNC_SCL_6306 (MTK_PIN_NO(56) | 2) + +#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define PINMUX_GPIO57__FUNC_BPI_BUS10 (MTK_PIN_NO(57) | 1) +#define PINMUX_GPIO57__FUNC_SDA_6306 (MTK_PIN_NO(57) | 2) + +#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define PINMUX_GPIO58__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(58) | 1) + +#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define PINMUX_GPIO59__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(59) | 1) + +#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define PINMUX_GPIO60__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(60) | 1) + +#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define PINMUX_GPIO61__FUNC_MIPI1_SDATA (MTK_PIN_NO(61) | 1) + +#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define PINMUX_GPIO62__FUNC_MIPI1_SCLK (MTK_PIN_NO(62) | 1) + +#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define PINMUX_GPIO63__FUNC_MIPI0_SDATA (MTK_PIN_NO(63) | 1) + +#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define PINMUX_GPIO64__FUNC_MIPI0_SCLK (MTK_PIN_NO(64) | 1) + +#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define PINMUX_GPIO65__FUNC_MIPI3_SDATA (MTK_PIN_NO(65) | 1) +#define PINMUX_GPIO65__FUNC_BPI_BUS16 (MTK_PIN_NO(65) | 2) + +#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define PINMUX_GPIO66__FUNC_MIPI3_SCLK (MTK_PIN_NO(66) | 1) +#define PINMUX_GPIO66__FUNC_BPI_BUS17 (MTK_PIN_NO(66) | 2) + +#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define PINMUX_GPIO67__FUNC_MIPI2_SDATA (MTK_PIN_NO(67) | 1) + +#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define PINMUX_GPIO68__FUNC_MIPI2_SCLK (MTK_PIN_NO(68) | 1) + +#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define PINMUX_GPIO69__FUNC_BPI_BUS7 (MTK_PIN_NO(69) | 1) + +#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define PINMUX_GPIO70__FUNC_BPI_BUS6 (MTK_PIN_NO(70) | 1) + +#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define PINMUX_GPIO71__FUNC_BPI_BUS5 (MTK_PIN_NO(71) | 1) + +#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define PINMUX_GPIO72__FUNC_BPI_BUS4 (MTK_PIN_NO(72) | 1) + +#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define PINMUX_GPIO73__FUNC_BPI_BUS3 (MTK_PIN_NO(73) | 1) + +#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define PINMUX_GPIO74__FUNC_BPI_BUS2 (MTK_PIN_NO(74) | 1) + +#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define PINMUX_GPIO75__FUNC_BPI_BUS1 (MTK_PIN_NO(75) | 1) + +#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define PINMUX_GPIO76__FUNC_BPI_BUS0 (MTK_PIN_NO(76) | 1) + +#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define PINMUX_GPIO77__FUNC_BPI_BUS14 (MTK_PIN_NO(77) | 1) + +#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define PINMUX_GPIO78__FUNC_BPI_BUS11 (MTK_PIN_NO(78) | 1) + +#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define PINMUX_GPIO79__FUNC_BPI_PA_VM1 (MTK_PIN_NO(79) | 1) +#define PINMUX_GPIO79__FUNC_MIPI4_SDATA (MTK_PIN_NO(79) | 2) + +#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define PINMUX_GPIO80__FUNC_BPI_PA_VM0 (MTK_PIN_NO(80) | 1) +#define PINMUX_GPIO80__FUNC_MIPI4_SCLK (MTK_PIN_NO(80) | 2) + +#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define PINMUX_GPIO81__FUNC_SDA1 (MTK_PIN_NO(81) | 1) +#define PINMUX_GPIO81__FUNC_DBG_MON_B0 (MTK_PIN_NO(81) | 7) + +#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define PINMUX_GPIO82__FUNC_SDA0 (MTK_PIN_NO(82) | 1) +#define PINMUX_GPIO82__FUNC_DBG_MON_B1 (MTK_PIN_NO(82) | 7) + +#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define PINMUX_GPIO83__FUNC_SCL0 (MTK_PIN_NO(83) | 1) +#define PINMUX_GPIO83__FUNC_DBG_MON_B2 (MTK_PIN_NO(83) | 7) + +#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define PINMUX_GPIO84__FUNC_SCL1 (MTK_PIN_NO(84) | 1) +#define PINMUX_GPIO84__FUNC_DBG_MON_B3 (MTK_PIN_NO(84) | 7) + +#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define PINMUX_GPIO85__FUNC_RFIC0_BSI_EN (MTK_PIN_NO(85) | 1) + +#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define PINMUX_GPIO86__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(86) | 1) + +#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define PINMUX_GPIO87__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(87) | 2) +#define PINMUX_GPIO87__FUNC_CMVREF0 (MTK_PIN_NO(87) | 3) +#define PINMUX_GPIO87__FUNC_MD_URXD0 (MTK_PIN_NO(87) | 4) +#define PINMUX_GPIO87__FUNC_AGPS_SYNC (MTK_PIN_NO(87) | 5) +#define PINMUX_GPIO87__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(87) | 6) + +#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define PINMUX_GPIO88__FUNC_CMMCLK3 (MTK_PIN_NO(88) | 1) +#define PINMUX_GPIO88__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(88) | 2) +#define PINMUX_GPIO88__FUNC_CMVREF1 (MTK_PIN_NO(88) | 3) +#define PINMUX_GPIO88__FUNC_MD_UTXD0 (MTK_PIN_NO(88) | 4) +#define PINMUX_GPIO88__FUNC_AGPS_SYNC (MTK_PIN_NO(88) | 5) +#define PINMUX_GPIO88__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(88) | 6) + +#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define PINMUX_GPIO89__FUNC_SRCLKENAI0 (MTK_PIN_NO(89) | 1) +#define PINMUX_GPIO89__FUNC_PWM2 (MTK_PIN_NO(89) | 2) +#define PINMUX_GPIO89__FUNC_MD_INT0 (MTK_PIN_NO(89) | 3) +#define PINMUX_GPIO89__FUNC_USB_DRVVBUS (MTK_PIN_NO(89) | 4) +#define PINMUX_GPIO89__FUNC_SCL_6306 (MTK_PIN_NO(89) | 5) +#define PINMUX_GPIO89__FUNC_TP_GPIO4_AO (MTK_PIN_NO(89) | 6) +#define PINMUX_GPIO89__FUNC_DBG_MON_B21 (MTK_PIN_NO(89) | 7) + +#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define PINMUX_GPIO90__FUNC_URXD1 (MTK_PIN_NO(90) | 1) +#define PINMUX_GPIO90__FUNC_PWM0 (MTK_PIN_NO(90) | 2) +#define PINMUX_GPIO90__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(90) | 3) +#define PINMUX_GPIO90__FUNC_ANT_SEL4 (MTK_PIN_NO(90) | 4) +#define PINMUX_GPIO90__FUNC_USB_DRVVBUS (MTK_PIN_NO(90) | 5) +#define PINMUX_GPIO90__FUNC_I2S2_BCK (MTK_PIN_NO(90) | 6) +#define PINMUX_GPIO90__FUNC_DBG_MON_B4 (MTK_PIN_NO(90) | 7) + +#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define PINMUX_GPIO91__FUNC_KPROW1 (MTK_PIN_NO(91) | 1) +#define PINMUX_GPIO91__FUNC_PWM2 (MTK_PIN_NO(91) | 2) +#define PINMUX_GPIO91__FUNC_MD_INT0 (MTK_PIN_NO(91) | 3) +#define PINMUX_GPIO91__FUNC_ANT_SEL5 (MTK_PIN_NO(91) | 4) +#define PINMUX_GPIO91__FUNC_IDDIG (MTK_PIN_NO(91) | 5) +#define PINMUX_GPIO91__FUNC_I2S2_LRCK (MTK_PIN_NO(91) | 6) +#define PINMUX_GPIO91__FUNC_DBG_MON_B5 (MTK_PIN_NO(91) | 7) + +#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define PINMUX_GPIO92__FUNC_KPROW0 (MTK_PIN_NO(92) | 1) +#define PINMUX_GPIO92__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(92) | 5) +#define PINMUX_GPIO92__FUNC_I2S2_DI (MTK_PIN_NO(92) | 6) +#define PINMUX_GPIO92__FUNC_DBG_MON_B6 (MTK_PIN_NO(92) | 7) + +#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define PINMUX_GPIO93__FUNC_KPCOL0 (MTK_PIN_NO(93) | 1) +#define PINMUX_GPIO93__FUNC_DBG_MON_B7 (MTK_PIN_NO(93) | 7) + +#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define PINMUX_GPIO94__FUNC_KPCOL1 (MTK_PIN_NO(94) | 1) +#define PINMUX_GPIO94__FUNC_CMFLASH (MTK_PIN_NO(94) | 5) +#define PINMUX_GPIO94__FUNC_CMVREF0 (MTK_PIN_NO(94) | 6) +#define PINMUX_GPIO94__FUNC_DBG_MON_B8 (MTK_PIN_NO(94) | 7) + +#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define PINMUX_GPIO95__FUNC_URXD0 (MTK_PIN_NO(95) | 1) +#define PINMUX_GPIO95__FUNC_UTXD0 (MTK_PIN_NO(95) | 2) +#define PINMUX_GPIO95__FUNC_MD_URXD0 (MTK_PIN_NO(95) | 3) +#define PINMUX_GPIO95__FUNC_PTA_RXD (MTK_PIN_NO(95) | 4) +#define PINMUX_GPIO95__FUNC_SSPM_URXD_AO (MTK_PIN_NO(95) | 5) +#define PINMUX_GPIO95__FUNC_WIFI_RXD (MTK_PIN_NO(95) | 6) + +#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define PINMUX_GPIO96__FUNC_UTXD0 (MTK_PIN_NO(96) | 1) +#define PINMUX_GPIO96__FUNC_URXD0 (MTK_PIN_NO(96) | 2) +#define PINMUX_GPIO96__FUNC_MD_UTXD0 (MTK_PIN_NO(96) | 3) +#define PINMUX_GPIO96__FUNC_PTA_TXD (MTK_PIN_NO(96) | 4) +#define PINMUX_GPIO96__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(96) | 5) +#define PINMUX_GPIO96__FUNC_WIFI_TXD (MTK_PIN_NO(96) | 6) + +#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define PINMUX_GPIO97__FUNC_UCTS0 (MTK_PIN_NO(97) | 1) +#define PINMUX_GPIO97__FUNC_I2S1_MCK (MTK_PIN_NO(97) | 2) +#define PINMUX_GPIO97__FUNC_CONN_MCU_TDO (MTK_PIN_NO(97) | 3) +#define PINMUX_GPIO97__FUNC_SPI5_MI (MTK_PIN_NO(97) | 4) +#define PINMUX_GPIO97__FUNC_SCL_6306 (MTK_PIN_NO(97) | 5) +#define PINMUX_GPIO97__FUNC_MCUPM_JTAG_TDO (MTK_PIN_NO(97) | 6) +#define PINMUX_GPIO97__FUNC_DBG_MON_B15 (MTK_PIN_NO(97) | 7) + +#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define PINMUX_GPIO98__FUNC_URTS0 (MTK_PIN_NO(98) | 1) +#define PINMUX_GPIO98__FUNC_I2S1_BCK (MTK_PIN_NO(98) | 2) +#define PINMUX_GPIO98__FUNC_CONN_MCU_TMS (MTK_PIN_NO(98) | 3) +#define PINMUX_GPIO98__FUNC_SPI5_CSB (MTK_PIN_NO(98) | 4) +#define PINMUX_GPIO98__FUNC_MCUPM_JTAG_TMS (MTK_PIN_NO(98) | 6) +#define PINMUX_GPIO98__FUNC_DBG_MON_B16 (MTK_PIN_NO(98) | 7) + +#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define PINMUX_GPIO99__FUNC_CMMCLK0 (MTK_PIN_NO(99) | 1) +#define PINMUX_GPIO99__FUNC_AUXIF_CLK (MTK_PIN_NO(99) | 4) +#define PINMUX_GPIO99__FUNC_PTA_RXD (MTK_PIN_NO(99) | 5) +#define PINMUX_GPIO99__FUNC_CONN_UART0_RXD (MTK_PIN_NO(99) | 6) +#define PINMUX_GPIO99__FUNC_DBG_MON_B17 (MTK_PIN_NO(99) | 7) + +#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define PINMUX_GPIO100__FUNC_CMMCLK1 (MTK_PIN_NO(100) | 1) +#define PINMUX_GPIO100__FUNC_AUXIF_ST (MTK_PIN_NO(100) | 4) +#define PINMUX_GPIO100__FUNC_PTA_TXD (MTK_PIN_NO(100) | 5) +#define PINMUX_GPIO100__FUNC_CONN_UART0_TXD (MTK_PIN_NO(100) | 6) +#define PINMUX_GPIO100__FUNC_DBG_MON_B18 (MTK_PIN_NO(100) | 7) + +#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define PINMUX_GPIO101__FUNC_CMFLASH (MTK_PIN_NO(101) | 1) +#define PINMUX_GPIO101__FUNC_I2S1_LRCK (MTK_PIN_NO(101) | 2) +#define PINMUX_GPIO101__FUNC_CONN_MCU_TCK (MTK_PIN_NO(101) | 3) +#define PINMUX_GPIO101__FUNC_SPI5_MO (MTK_PIN_NO(101) | 4) +#define PINMUX_GPIO101__FUNC_MCUPM_JTAG_TCK (MTK_PIN_NO(101) | 6) +#define PINMUX_GPIO101__FUNC_DBG_MON_B19 (MTK_PIN_NO(101) | 7) + +#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define PINMUX_GPIO102__FUNC_CMVREF0 (MTK_PIN_NO(102) | 1) +#define PINMUX_GPIO102__FUNC_I2S1_DO (MTK_PIN_NO(102) | 2) +#define PINMUX_GPIO102__FUNC_CONN_MCU_TDI (MTK_PIN_NO(102) | 3) +#define PINMUX_GPIO102__FUNC_SPI5_CLK (MTK_PIN_NO(102) | 4) +#define PINMUX_GPIO102__FUNC_AGPS_SYNC (MTK_PIN_NO(102) | 5) +#define PINMUX_GPIO102__FUNC_MCUPM_JTAG_TDI (MTK_PIN_NO(102) | 6) +#define PINMUX_GPIO102__FUNC_DBG_MON_B20 (MTK_PIN_NO(102) | 7) + +#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define PINMUX_GPIO103__FUNC_SCL2 (MTK_PIN_NO(103) | 1) +#define PINMUX_GPIO103__FUNC_TP_UTXD1_AO (MTK_PIN_NO(103) | 2) +#define PINMUX_GPIO103__FUNC_MD_UTXD0 (MTK_PIN_NO(103) | 3) +#define PINMUX_GPIO103__FUNC_MD_UTXD1 (MTK_PIN_NO(103) | 4) +#define PINMUX_GPIO103__FUNC_TP_URTS2_AO (MTK_PIN_NO(103) | 5) +#define PINMUX_GPIO103__FUNC_WIFI_TXD (MTK_PIN_NO(103) | 6) +#define PINMUX_GPIO103__FUNC_DBG_MON_B25 (MTK_PIN_NO(103) | 7) + +#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define PINMUX_GPIO104__FUNC_SDA2 (MTK_PIN_NO(104) | 1) +#define PINMUX_GPIO104__FUNC_TP_URXD1_AO (MTK_PIN_NO(104) | 2) +#define PINMUX_GPIO104__FUNC_MD_URXD0 (MTK_PIN_NO(104) | 3) +#define PINMUX_GPIO104__FUNC_MD_URXD1 (MTK_PIN_NO(104) | 4) +#define PINMUX_GPIO104__FUNC_TP_UCTS2_AO (MTK_PIN_NO(104) | 5) +#define PINMUX_GPIO104__FUNC_WIFI_RXD (MTK_PIN_NO(104) | 6) +#define PINMUX_GPIO104__FUNC_DBG_MON_B26 (MTK_PIN_NO(104) | 7) + +#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define PINMUX_GPIO105__FUNC_SCL4 (MTK_PIN_NO(105) | 1) +#define PINMUX_GPIO105__FUNC_MD_UTXD1 (MTK_PIN_NO(105) | 3) +#define PINMUX_GPIO105__FUNC_MD_UTXD0 (MTK_PIN_NO(105) | 4) +#define PINMUX_GPIO105__FUNC_TP_UTXD2_AO (MTK_PIN_NO(105) | 5) +#define PINMUX_GPIO105__FUNC_PTA_TXD (MTK_PIN_NO(105) | 6) +#define PINMUX_GPIO105__FUNC_DBG_MON_B27 (MTK_PIN_NO(105) | 7) + +#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define PINMUX_GPIO106__FUNC_SDA4 (MTK_PIN_NO(106) | 1) +#define PINMUX_GPIO106__FUNC_MD_URXD1 (MTK_PIN_NO(106) | 3) +#define PINMUX_GPIO106__FUNC_MD_URXD0 (MTK_PIN_NO(106) | 4) +#define PINMUX_GPIO106__FUNC_TP_URXD2_AO (MTK_PIN_NO(106) | 5) +#define PINMUX_GPIO106__FUNC_PTA_RXD (MTK_PIN_NO(106) | 6) +#define PINMUX_GPIO106__FUNC_DBG_MON_B28 (MTK_PIN_NO(106) | 7) + +#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define PINMUX_GPIO107__FUNC_UTXD1 (MTK_PIN_NO(107) | 1) +#define PINMUX_GPIO107__FUNC_MD_UTXD0 (MTK_PIN_NO(107) | 2) +#define PINMUX_GPIO107__FUNC_SDA_6306 (MTK_PIN_NO(107) | 3) +#define PINMUX_GPIO107__FUNC_KPCOL3 (MTK_PIN_NO(107) | 4) +#define PINMUX_GPIO107__FUNC_CMVREF0 (MTK_PIN_NO(107) | 5) +#define PINMUX_GPIO107__FUNC_URTS0 (MTK_PIN_NO(107) | 6) +#define PINMUX_GPIO107__FUNC_DBG_MON_B29 (MTK_PIN_NO(107) | 7) + +#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define PINMUX_GPIO108__FUNC_CMMCLK2 (MTK_PIN_NO(108) | 1) +#define PINMUX_GPIO108__FUNC_MD_INT0 (MTK_PIN_NO(108) | 2) +#define PINMUX_GPIO108__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(108) | 3) +#define PINMUX_GPIO108__FUNC_KPCOL4 (MTK_PIN_NO(108) | 4) +#define PINMUX_GPIO108__FUNC_I2S3_MCK (MTK_PIN_NO(108) | 6) +#define PINMUX_GPIO108__FUNC_DBG_MON_B30 (MTK_PIN_NO(108) | 7) + +#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define PINMUX_GPIO109__FUNC_URXD1 (MTK_PIN_NO(109) | 1) +#define PINMUX_GPIO109__FUNC_MD_URXD0 (MTK_PIN_NO(109) | 2) +#define PINMUX_GPIO109__FUNC_ANT_SEL7 (MTK_PIN_NO(109) | 3) +#define PINMUX_GPIO109__FUNC_KPCOL5 (MTK_PIN_NO(109) | 4) +#define PINMUX_GPIO109__FUNC_CMVREF1 (MTK_PIN_NO(109) | 5) +#define PINMUX_GPIO109__FUNC_UCTS0 (MTK_PIN_NO(109) | 6) +#define PINMUX_GPIO109__FUNC_DBG_MON_B31 (MTK_PIN_NO(109) | 7) + +#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define PINMUX_GPIO110__FUNC_ANT_SEL0 (MTK_PIN_NO(110) | 1) +#define PINMUX_GPIO110__FUNC_CLKM0 (MTK_PIN_NO(110) | 2) +#define PINMUX_GPIO110__FUNC_PWM3 (MTK_PIN_NO(110) | 3) +#define PINMUX_GPIO110__FUNC_MD_INT0 (MTK_PIN_NO(110) | 4) +#define PINMUX_GPIO110__FUNC_IDDIG (MTK_PIN_NO(110) | 5) +#define PINMUX_GPIO110__FUNC_I2S3_BCK (MTK_PIN_NO(110) | 6) +#define PINMUX_GPIO110__FUNC_DBG_MON_B13 (MTK_PIN_NO(110) | 7) + +#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define PINMUX_GPIO111__FUNC_ANT_SEL1 (MTK_PIN_NO(111) | 1) +#define PINMUX_GPIO111__FUNC_CLKM1 (MTK_PIN_NO(111) | 2) +#define PINMUX_GPIO111__FUNC_PWM4 (MTK_PIN_NO(111) | 3) +#define PINMUX_GPIO111__FUNC_PTA_RXD (MTK_PIN_NO(111) | 4) +#define PINMUX_GPIO111__FUNC_CMVREF0 (MTK_PIN_NO(111) | 5) +#define PINMUX_GPIO111__FUNC_I2S3_LRCK (MTK_PIN_NO(111) | 6) +#define PINMUX_GPIO111__FUNC_DBG_MON_B14 (MTK_PIN_NO(111) | 7) + +#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define PINMUX_GPIO112__FUNC_ANT_SEL2 (MTK_PIN_NO(112) | 1) +#define PINMUX_GPIO112__FUNC_CLKM2 (MTK_PIN_NO(112) | 2) +#define PINMUX_GPIO112__FUNC_PWM5 (MTK_PIN_NO(112) | 3) +#define PINMUX_GPIO112__FUNC_PTA_TXD (MTK_PIN_NO(112) | 4) +#define PINMUX_GPIO112__FUNC_CMVREF1 (MTK_PIN_NO(112) | 5) +#define PINMUX_GPIO112__FUNC_I2S3_DO (MTK_PIN_NO(112) | 6) + +#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define PINMUX_GPIO113__FUNC_CONN_TOP_CLK (MTK_PIN_NO(113) | 1) + +#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define PINMUX_GPIO114__FUNC_CONN_TOP_DATA (MTK_PIN_NO(114) | 1) + +#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define PINMUX_GPIO115__FUNC_CONN_BT_CLK (MTK_PIN_NO(115) | 1) + +#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define PINMUX_GPIO116__FUNC_CONN_BT_DATA (MTK_PIN_NO(116) | 1) + +#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define PINMUX_GPIO117__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(117) | 1) + +#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define PINMUX_GPIO118__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(118) | 1) + +#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define PINMUX_GPIO119__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(119) | 1) + +#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define PINMUX_GPIO120__FUNC_CONN_WB_PTA (MTK_PIN_NO(120) | 1) + +#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define PINMUX_GPIO121__FUNC_CONN_HRST_B (MTK_PIN_NO(121) | 1) + +#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define PINMUX_GPIO122__FUNC_AUX1_MSDC0_CMD (MTK_PIN_NO(122) | 1) +#define PINMUX_GPIO122__FUNC_AUX2_MSDC0_CMD (MTK_PIN_NO(122) | 2) + +#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define PINMUX_GPIO123__FUNC_MSDC0_DAT0 (MTK_PIN_NO(123) | 1) +#define PINMUX_GPIO123__FUNC_MSDC0_DAT4 (MTK_PIN_NO(123) | 2) + +#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define PINMUX_GPIO124__FUNC_AUX1_MSDC0_CLK (MTK_PIN_NO(124) | 1) +#define PINMUX_GPIO124__FUNC_AUX2_MSDC0_CLK (MTK_PIN_NO(124) | 2) + +#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define PINMUX_GPIO125__FUNC_MSDC0_DAT2 (MTK_PIN_NO(125) | 1) +#define PINMUX_GPIO125__FUNC_MSDC0_DAT5 (MTK_PIN_NO(125) | 2) + +#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define PINMUX_GPIO126__FUNC_MSDC0_DAT4 (MTK_PIN_NO(126) | 1) +#define PINMUX_GPIO126__FUNC_MSDC0_DAT2 (MTK_PIN_NO(126) | 2) + +#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define PINMUX_GPIO127__FUNC_MSDC0_DAT6 (MTK_PIN_NO(127) | 1) +#define PINMUX_GPIO127__FUNC_MSDC0_DAT1 (MTK_PIN_NO(127) | 2) + +#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define PINMUX_GPIO128__FUNC_MSDC0_DAT1 (MTK_PIN_NO(128) | 1) +#define PINMUX_GPIO128__FUNC_MSDC0_DAT6 (MTK_PIN_NO(128) | 2) + +#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define PINMUX_GPIO129__FUNC_MSDC0_DAT5 (MTK_PIN_NO(129) | 1) +#define PINMUX_GPIO129__FUNC_MSDC0_DAT0 (MTK_PIN_NO(129) | 2) + +#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define PINMUX_GPIO130__FUNC_AUX1_MSDC0_DAT7 (MTK_PIN_NO(130) | 1) +#define PINMUX_GPIO130__FUNC_AUX2_MSDC0_DAT7 (MTK_PIN_NO(130) | 2) + +#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define PINMUX_GPIO131__FUNC_AUX1_MSDC0_DSL (MTK_PIN_NO(131) | 1) +#define PINMUX_GPIO131__FUNC_AUX2_MSDC0_DSL (MTK_PIN_NO(131) | 2) + +#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define PINMUX_GPIO132__FUNC_AUX1_MSDC0_DAT3 (MTK_PIN_NO(132) | 1) +#define PINMUX_GPIO132__FUNC_AUX2_MSDC0_DAT3 (MTK_PIN_NO(132) | 2) + +#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define PINMUX_GPIO133__FUNC_AUX1_MSDC0_RSTB (MTK_PIN_NO(133) | 1) +#define PINMUX_GPIO133__FUNC_AUX2_MSDC0_RSTB (MTK_PIN_NO(133) | 2) + +#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define PINMUX_GPIO134__FUNC_RTC32K_CK (MTK_PIN_NO(134) | 1) + +#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define PINMUX_GPIO135__FUNC_WATCHDOG (MTK_PIN_NO(135) | 1) + +#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define PINMUX_GPIO136__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(136) | 1) +#define PINMUX_GPIO136__FUNC_AUD_CLK_MISO (MTK_PIN_NO(136) | 2) +#define PINMUX_GPIO136__FUNC_I2S1_MCK (MTK_PIN_NO(136) | 3) + +#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(137) | 1) +#define PINMUX_GPIO137__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(137) | 2) +#define PINMUX_GPIO137__FUNC_I2S1_BCK (MTK_PIN_NO(137) | 3) + +#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(138) | 1) +#define PINMUX_GPIO138__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(138) | 2) +#define PINMUX_GPIO138__FUNC_I2S1_LRCK (MTK_PIN_NO(138) | 3) + +#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(139) | 1) +#define PINMUX_GPIO139__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(139) | 2) +#define PINMUX_GPIO139__FUNC_I2S1_DO (MTK_PIN_NO(139) | 3) + +#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define PINMUX_GPIO140__FUNC_AUD_CLK_MISO (MTK_PIN_NO(140) | 1) +#define PINMUX_GPIO140__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(140) | 2) +#define PINMUX_GPIO140__FUNC_I2S2_MCK (MTK_PIN_NO(140) | 3) + +#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define PINMUX_GPIO141__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(141) | 1) +#define PINMUX_GPIO141__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(141) | 2) +#define PINMUX_GPIO141__FUNC_I2S2_BCK (MTK_PIN_NO(141) | 3) + +#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define PINMUX_GPIO142__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(142) | 1) +#define PINMUX_GPIO142__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(142) | 2) +#define PINMUX_GPIO142__FUNC_I2S2_LRCK (MTK_PIN_NO(142) | 3) + +#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define PINMUX_GPIO143__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(143) | 1) +#define PINMUX_GPIO143__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(143) | 2) +#define PINMUX_GPIO143__FUNC_I2S2_DI (MTK_PIN_NO(143) | 3) + +#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define PINMUX_GPIO144__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(144) | 1) +#define PINMUX_GPIO144__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(144) | 2) + +#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define PINMUX_GPIO145__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(145) | 1) + +#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define PINMUX_GPIO146__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(146) | 1) +#define PINMUX_GPIO146__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(146) | 2) + +#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define PINMUX_GPIO147__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(147) | 1) + +#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define PINMUX_GPIO148__FUNC_SRCLKENA0 (MTK_PIN_NO(148) | 1) + +#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define PINMUX_GPIO149__FUNC_SRCLKENA1 (MTK_PIN_NO(149) | 1) + +#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define PINMUX_GPIO150__FUNC_PWM0 (MTK_PIN_NO(150) | 1) +#define PINMUX_GPIO150__FUNC_CMFLASH (MTK_PIN_NO(150) | 2) +#define PINMUX_GPIO150__FUNC_ANT_SEL3 (MTK_PIN_NO(150) | 3) +#define PINMUX_GPIO150__FUNC_MD_URXD0 (MTK_PIN_NO(150) | 5) +#define PINMUX_GPIO150__FUNC_TP_URXD2_AO (MTK_PIN_NO(150) | 6) + +#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define PINMUX_GPIO151__FUNC_PWM1 (MTK_PIN_NO(151) | 1) +#define PINMUX_GPIO151__FUNC_CMVREF0 (MTK_PIN_NO(151) | 2) +#define PINMUX_GPIO151__FUNC_ANT_SEL4 (MTK_PIN_NO(151) | 3) +#define PINMUX_GPIO151__FUNC_MD_UTXD0 (MTK_PIN_NO(151) | 5) +#define PINMUX_GPIO151__FUNC_TP_UTXD2_AO (MTK_PIN_NO(151) | 6) + +#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define PINMUX_GPIO152__FUNC_PWM2 (MTK_PIN_NO(152) | 1) +#define PINMUX_GPIO152__FUNC_CMVREF1 (MTK_PIN_NO(152) | 2) +#define PINMUX_GPIO152__FUNC_ANT_SEL5 (MTK_PIN_NO(152) | 3) +#define PINMUX_GPIO152__FUNC_MD_URXD1 (MTK_PIN_NO(152) | 5) +#define PINMUX_GPIO152__FUNC_TP_UCTS1_AO (MTK_PIN_NO(152) | 6) + +#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define PINMUX_GPIO153__FUNC_PWM3 (MTK_PIN_NO(153) | 1) +#define PINMUX_GPIO153__FUNC_CLKM0 (MTK_PIN_NO(153) | 2) +#define PINMUX_GPIO153__FUNC_ANT_SEL6 (MTK_PIN_NO(153) | 3) +#define PINMUX_GPIO153__FUNC_MD_UTXD1 (MTK_PIN_NO(153) | 5) +#define PINMUX_GPIO153__FUNC_TP_URTS1_AO (MTK_PIN_NO(153) | 6) + +#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define PINMUX_GPIO154__FUNC_PWM5 (MTK_PIN_NO(154) | 1) +#define PINMUX_GPIO154__FUNC_CLKM2 (MTK_PIN_NO(154) | 2) +#define PINMUX_GPIO154__FUNC_USB_DRVVBUS (MTK_PIN_NO(154) | 3) +#define PINMUX_GPIO154__FUNC_PTA_TXD (MTK_PIN_NO(154) | 5) +#define PINMUX_GPIO154__FUNC_CONN_UART0_TXD (MTK_PIN_NO(154) | 6) + +#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +#define PINMUX_GPIO155__FUNC_SPI0_MI (MTK_PIN_NO(155) | 1) +#define PINMUX_GPIO155__FUNC_IDDIG (MTK_PIN_NO(155) | 2) +#define PINMUX_GPIO155__FUNC_AGPS_SYNC (MTK_PIN_NO(155) | 3) +#define PINMUX_GPIO155__FUNC_TP_GPIO0_AO (MTK_PIN_NO(155) | 4) +#define PINMUX_GPIO155__FUNC_MFG_JTAG_TDO (MTK_PIN_NO(155) | 5) +#define PINMUX_GPIO155__FUNC_DFD_TDO (MTK_PIN_NO(155) | 6) +#define PINMUX_GPIO155__FUNC_JTDO_SEL1 (MTK_PIN_NO(155) | 7) + +#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +#define PINMUX_GPIO156__FUNC_SPI0_CSB (MTK_PIN_NO(156) | 1) +#define PINMUX_GPIO156__FUNC_USB_DRVVBUS (MTK_PIN_NO(156) | 2) +#define PINMUX_GPIO156__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(156) | 3) +#define PINMUX_GPIO156__FUNC_TP_GPIO1_AO (MTK_PIN_NO(156) | 4) +#define PINMUX_GPIO156__FUNC_MFG_JTAG_TMS (MTK_PIN_NO(156) | 5) +#define PINMUX_GPIO156__FUNC_DFD_TMS (MTK_PIN_NO(156) | 6) +#define PINMUX_GPIO156__FUNC_JTMS_SEL1 (MTK_PIN_NO(156) | 7) + +#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +#define PINMUX_GPIO157__FUNC_SPI0_MO (MTK_PIN_NO(157) | 1) +#define PINMUX_GPIO157__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(157) | = 2) +#define PINMUX_GPIO157__FUNC_CLKM0 (MTK_PIN_NO(157) | 3) +#define PINMUX_GPIO157__FUNC_TP_GPIO2_AO (MTK_PIN_NO(157) | 4) +#define PINMUX_GPIO157__FUNC_MFG_JTAG_TDI (MTK_PIN_NO(157) | 5) +#define PINMUX_GPIO157__FUNC_DFD_TDI (MTK_PIN_NO(157) | 6) +#define PINMUX_GPIO157__FUNC_JTDI_SEL1 (MTK_PIN_NO(157) | 7) + +#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +#define PINMUX_GPIO158__FUNC_SPI0_CLK (MTK_PIN_NO(158) | 1) +#define PINMUX_GPIO158__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(158) | = 2) +#define PINMUX_GPIO158__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(158) | 3) +#define PINMUX_GPIO158__FUNC_TP_GPIO3_AO (MTK_PIN_NO(158) | 4) +#define PINMUX_GPIO158__FUNC_MFG_JTAG_TCK (MTK_PIN_NO(158) | 5) +#define PINMUX_GPIO158__FUNC_DFD_TCK_XI (MTK_PIN_NO(158) | 6) +#define PINMUX_GPIO158__FUNC_JTCK_SEL1 (MTK_PIN_NO(158) | 7) + +#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +#define PINMUX_GPIO159__FUNC_PWM4 (MTK_PIN_NO(159) | 1) +#define PINMUX_GPIO159__FUNC_CLKM1 (MTK_PIN_NO(159) | 2) +#define PINMUX_GPIO159__FUNC_ANT_SEL7 (MTK_PIN_NO(159) | 3) +#define PINMUX_GPIO159__FUNC_PTA_RXD (MTK_PIN_NO(159) | 5) +#define PINMUX_GPIO159__FUNC_CONN_UART0_RXD (MTK_PIN_NO(159) | 6) + +#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +#define PINMUX_GPIO160__FUNC_CLKM0 (MTK_PIN_NO(160) | 1) +#define PINMUX_GPIO160__FUNC_PWM2 (MTK_PIN_NO(160) | 2) +#define PINMUX_GPIO160__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(160) | 3) +#define PINMUX_GPIO160__FUNC_TP_GPIO5_AO (MTK_PIN_NO(160) | 4) +#define PINMUX_GPIO160__FUNC_AGPS_SYNC (MTK_PIN_NO(160) | 5) +#define PINMUX_GPIO160__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(160) | 6) + +#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +#define PINMUX_GPIO161__FUNC_SCL6 (MTK_PIN_NO(161) | 1) +#define PINMUX_GPIO161__FUNC_SCL_6306 (MTK_PIN_NO(161) | 2) +#define PINMUX_GPIO161__FUNC_TP_GPIO6_AO (MTK_PIN_NO(161) | 3) +#define PINMUX_GPIO161__FUNC_KPCOL6 (MTK_PIN_NO(161) | 4) +#define PINMUX_GPIO161__FUNC_PTA_RXD (MTK_PIN_NO(161) | 5) +#define PINMUX_GPIO161__FUNC_CONN_UART0_RXD (MTK_PIN_NO(161) | 6) + +#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +#define PINMUX_GPIO162__FUNC_SDA6 (MTK_PIN_NO(162) | 1) +#define PINMUX_GPIO162__FUNC_SDA_6306 (MTK_PIN_NO(162) | 2) +#define PINMUX_GPIO162__FUNC_TP_GPIO7_AO (MTK_PIN_NO(162) | 3) +#define PINMUX_GPIO162__FUNC_KPCOL7 (MTK_PIN_NO(162) | 4) +#define PINMUX_GPIO162__FUNC_PTA_TXD (MTK_PIN_NO(162) | 5) +#define PINMUX_GPIO162__FUNC_CONN_UART0_TXD (MTK_PIN_NO(162) | 6) + +#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) + +#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) + +#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) + +#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) + +#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) + +#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) + +#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) + +#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) + +#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) + +#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) + +#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) + +#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) + +#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) + +#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) + +#define 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FF5795518A3D127A4AD6D5ED66289B5278DA827A17800CE760302A529BCAAAFCEA1F7E6F0F101C67BD4B6F7A4D31EC0BCC500DACC3FED6E28638F802B75D45FF8AA50765F7900637B28E90C11C329EF18638F802B75D45FF36EB9D2243A4F8B5A6FCA7DBDB1FC311F39EFFDF887939037866D6147AF826D82570FCA53F16511A83832EE758E1DF5414DF00F3BD1EAAA9CC7F00164DA146DAFE8445B8C89999728AA50765F79006374F374FBCC9EDB495389733CBF5DBD5E9C8A9BA7A39EFB766F5D81C698A659EA7CC7F00164DA146DA9985D098DBDEAEC8D2DCF9CF1F528DBCF6B57BC7E6449061A352F6E88A58FB86F5D81C698A659EA73AA81AA40904B5D9A18204E546F3947C643FE6A0CAC512C72D242C3BD2E3F4C64AD6D5ED66289B523666184CF4C3C14F6136E347CC761E07725E5C173C3A84C3E4A64BF2429643C8BA3038C0950A5D36B5C8C57E37DE458B330BD67F2E7D9AF16D1867E19FE14079C09775C1D3CA48CF3D321E7403792E342EB15956EA79C166A417C69337E82CC275ECD9A6C639B01B78DA827A17800CE77F095E679B220E0C731C566533BA786AA5CC5B56E945C8DA X-C1DE0DAB: 0D63561A33F958A5905487F9E6F6BD445002B1117B3ED696151B13FE362816443D2BBC1EF78EDEBE823CB91A9FED034534781492E4B8EEAD69BF13FED57427F1C79554A2A72441328621D336A7BC284946AD531847A6065A535571D14F44ED41 X-C8649E89: 1C3962B70DF3F0ADE00A9FD3E00BEEDF77DD89D51EBB7742D3581295AF09D3DF87807E0823442EA2ED31085941D9CD0AF7F820E7B07EA4CF92F0962FFBA62BF51607CC140B3088954361740219701A828057699EB7BCCB91EEB2523CC0526E3F67C7AAC6E25A2086B57C1B32712EB477FEDD108130C0427C97E10C581ADD9E9322BA058254B804A102C26D483E81D6BE44BE0F8B58F75087CBB04030989F1EE011FE023E09B2D9C0 X-D57D3AED: 3ZO7eAau8CL7WIMRKs4sN3D3tLDjz0dLbV79QFUyzQ2Ujvy7cMT6pYYqY16iZVKkSc3dCLJ7zSJH7+u4VD18S7Vl4ZUrpaVfd2+vE6kuoey4m4VkSEu530nj6fImhcD4MUrOEAnl0W826KZ9Q+tr5ycPtXkTV4k65bRjmOUUP8cvGozZ33TWg5HZplvhhXbhDGzqmQDTd6OAevLeAnq3Ra9uf7zvY2zzsIhlcp/Y7m53TZgf2aB4JOg4gkr2biojX2k8aL79D6WzePG3zjDDEw== X-Mailru-Sender: 5DE64BD8B4008F63F32F89B2E510BB5456122DE473CB4F5AB951B70A5BD4BD8EDDDCE20488194853C479C2914A57FB1F3B9265ADAFE7D7E06F53C80213D1719CA6FC796F43705345A9EF9D9C6A90DD94D3D6663D5D4272A7B4A721A3011E896F X-Mras: Ok X-7564579A: 646B95376F6C166E X-77F55803: 6242723A09DB00B431B8944160407DD0C2EAA1E6BA7F9BE034EB9672DF358C7268F3CF0E9FE49B69BA651B92B2A570CDF7F174742BA51ED9A3F6D35AA5AFD3FB9DAB4D0B271CB4B0 X-7FA49CB5: 0D63561A33F958A5813E036B878CC046BCB23413696EEAD02DEC6E588680D74D8941B15DA834481FA18204E546F3947CC824672CB62AFFF2F6B57BC7E64490618DEB871D839B7333395957E7521B51C2DFABB839C843B9C08941B15DA834481F8AA50765F79006378E5B25976F539216389733CBF5DBD5E9B5C8C57E37DE458BD96E472CDF7238E0725E5C173C3A84C306E3C6E93C569A9E089D37D7C0E48F6C5571747095F342E88FB05168BE4CE3AF X-D57D3AED: 3ZO7eAau8CL7WIMRKs4sN3D3tLDjz0dLbV79QFUyzQ2Ujvy7cMT6pYYqY16iZVKkSc3dCLJ7zSJH7+u4VD18S7Vl4ZUrpaVfd2+vE6kuoey4m4VkSEu530nj6fImhcD4MUrOEAnl0W826KZ9Q+tr5ycPtXkTV4k65bRjmOUUP8cvGozZ33TWg5HZplvhhXbhDGzqmQDTd6OAevLeAnq3Ra9uf7zvY2zzsIhlcp/Y7m53TZgf2aB4JOg4gkr2biojX2k8aL79D6XVMRrxXEaqpQ== X-Mailru-MI: 8000000000000800 X-Mras: Ok Content-Type: text/plain; charset="utf-8" None of the MT6765 reset-controllers have PWRAP reset, so remove the requirement of it Fixes: 12b079b0fe8b ("soc: mediatek: pwrap: add pwrap driver for mt6765 SoC= s") Signed-off-by: Arseniy Velikanov --- drivers/soc/mediatek/mtk-pmic-wrap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mt= k-pmic-wrap.c index efd9cae212dc..30d74279e27f 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -2288,7 +2288,7 @@ static const struct pmic_wrapper_type pwrap_mt6765 = =3D { .int_en_all =3D 0xffffffff, .spi_w =3D PWRAP_MAN_CMD_SPI_WRITE, .wdt_src =3D PWRAP_WDT_SRC_MASK_ALL, - .caps =3D PWRAP_CAP_RESET | PWRAP_CAP_DCM, + .caps =3D PWRAP_CAP_DCM, .init_reg_clock =3D pwrap_common_init_reg_clock, .init_soc_specific =3D NULL, }; --=20 2.45.2