From nobody Thu Sep 19 23:14:02 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4EBCE43AAB; Mon, 29 Jul 2024 07:06:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236797; cv=none; b=HN3itWeTwuClwo9fGdgspPlOlQboovLvnC7tQvwGR9XRPt7IxXQlfNcJ2nf1uz4zuuQs6Pr51kuDSBvZhk8/7bU8IsiF3RAVzZdHZxHKSo3gIQArKFAJKphY8HVM6yLKa4fEFQQK1pzu94RxTptSYXqot2MImPf72p8Lu5JpiaI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236797; c=relaxed/simple; bh=QRI0nR/CG7Adw5rChLp9HDCOcBuhHZs1uFOHuPs9fuE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TBTJLwvdyHfF3gagjhl00Q8/1VfncxmNHv/Ea/trkEjYCbyNP1HBPCETk7ZAyIw/rwR3OCMmpFIV1nXUJzYRWdZhM8vDO5B+3Z/aIShffE84hhYaFKhEnY0UDYdhMhcjYxrlBXHdpdNx1d4+HCUU1ZEpnJvnX7vg42CG9y4PgNY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=lk+TjvCz; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="lk+TjvCz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1722236795; x=1753772795; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QRI0nR/CG7Adw5rChLp9HDCOcBuhHZs1uFOHuPs9fuE=; b=lk+TjvCzuEcDBaNWOUHYUaapUIFy52ATP08MkhOYtZ/fFQ1mOlf5PDXb P7i45mSfpvx/0ZBv1rgKDJYkFSML6/l/wko6/t3JpPLytpB2Uo9M+OKH/ 64IcBcKZ8bt+x79tfECMdknr0CxJ0XBD/MLz3cC28TXgUFt77TMGP9eSE Bpz/I9O5v2ulBhoXfsFTbt/5t13vkpqqTRYma+kui8Kv5vGEnAtNfRUCs qNzOznrxUdg8E6qcA+KLrBzUHRCyfIxfnOmgi0qzAIbFMQJgN9KpglJCD 3BO3DnK+bJpbtxkH7eUjGk8Uo260svIvJbouDQa2isINO2iJfdaXf6CLd w==; X-CSE-ConnectionGUID: dbvVkR59Tgaty9Rjj1qKOQ== X-CSE-MsgGUID: DxV5YsByR/iwxA7iJAd0iw== X-IronPort-AV: E=Sophos;i="6.09,245,1716274800"; d="scan'208";a="30453968" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 29 Jul 2024 00:06:34 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 29 Jul 2024 00:06:02 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 29 Jul 2024 00:05:58 -0700 From: Varshini Rajendran To: , , , , , , , , , , , CC: Krzysztof Kozlowski Subject: [PATCH v6 01/27] dt-bindings: atmel-sysreg: add sam9x7 Date: Mon, 29 Jul 2024 12:35:43 +0530 Message-ID: <20240729070543.1990209-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729065603.1986074-1-varshini.rajendran@microchip.com> References: <20240729065603.1986074-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add RAM controller & PIT64 DT bindings. Signed-off-by: Varshini Rajendran Acked-by: Krzysztof Kozlowski --- Changes in v6: - Removed sfr compatible from the previous version patch as the syscon devices compatible are moved to a different file. Did not remove the Acked-by tag as there is no additional changes, only a change that is removed. -- Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Docu= mentation/devicetree/bindings/arm/atmel-sysregs.txt index 7374beb5a613..76e2b7978250 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -11,7 +11,8 @@ PIT Timer required properties: shared across all System Controller members. =20 PIT64B Timer required properties: -- compatible: Should be "microchip,sam9x60-pit64b" +- compatible: Should be "microchip,sam9x60-pit64b" or + "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b" - reg: Should contain registers location and length - interrupts: Should contain interrupt for PIT64B timer - clocks: Should contain the available clock sources for PIT64B timer. @@ -31,7 +32,8 @@ RAMC SDRAM/DDR Controller required properties: "atmel,at91sam9g45-ddramc", "atmel,sama5d3-ddramc", "microchip,sam9x60-ddramc", - "microchip,sama7g5-uddrc" + "microchip,sama7g5-uddrc", + "microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc". - reg: Should contain registers location and length =20 Examples: --=20 2.25.1 From nobody Thu Sep 19 23:14:02 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33A3F7D3EC; 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X-CSE-ConnectionGUID: MnTnLLroRF2oCkj0nuokmg== X-CSE-MsgGUID: 5TKxq8NwQEm1E1f6fiybtA== X-IronPort-AV: E=Sophos;i="6.09,245,1716274800"; d="scan'208";a="32596747" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 29 Jul 2024 00:06:53 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 29 Jul 2024 00:06:28 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 29 Jul 2024 00:06:23 -0700 From: Varshini Rajendran To: , , , , , , , , , , , CC: Subject: [PATCH v6 02/27] dt-bindings: mfd: syscon: add microchip's sam9x7 sfr Date: Mon, 29 Jul 2024 12:36:03 +0530 Message-ID: <20240729070603.1990265-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729065603.1986074-1-varshini.rajendran@microchip.com> References: <20240729065603.1986074-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible for sam9x7 SoC's SFR. Signed-off-by: Varshini Rajendran --- Changes in v6: - New patch in v6 as the syscon devices are moved to a new file upstream. --- .../devicetree/bindings/mfd/syscon.yaml | 188 +++++++++--------- 1 file changed, 97 insertions(+), 91 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index 9dc594ea3654..50392d091e70 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -120,97 +120,103 @@ select: =20 properties: compatible: - items: - - enum: - - al,alpine-sysfabric-service - - allwinner,sun8i-a83t-system-controller - - allwinner,sun8i-h3-system-controller - - allwinner,sun8i-v3s-system-controller - - allwinner,sun50i-a64-system-controller - - altr,l3regs - - altr,sdr-ctl - - amd,pensando-elba-syscon - - amlogic,meson-mx-assist - - amlogic,meson-mx-bootrom - - amlogic,meson8-analog-top - - amlogic,meson8b-analog-top - - amlogic,meson8-pmu - - amlogic,meson8b-pmu - - apm,merlin-poweroff-mailbox - - apm,mustang-poweroff-mailbox - - apm,xgene-csw - - apm,xgene-efuse - - apm,xgene-mcb - - apm,xgene-rb - - apm,xgene-scu - - atmel,sama5d2-sfrbu - - atmel,sama5d3-nfc-io - - atmel,sama5d3-sfrbu - - atmel,sama5d4-sfrbu - - axis,artpec6-syscon - - brcm,cru-clkset - - brcm,sr-cdru - - brcm,sr-mhb - - cirrus,ep7209-syscon1 - - cirrus,ep7209-syscon2 - - cirrus,ep7209-syscon3 - - cnxt,cx92755-uc - - freecom,fsg-cs2-system-controller - - fsl,imx93-aonmix-ns-syscfg - - fsl,imx93-wakeupmix-syscfg - - fsl,ls1088a-reset - - fsl,vf610-anatop - - fsl,vf610-mscm-cpucfg - - hisilicon,dsa-subctrl - - hisilicon,hi6220-sramctrl - - hisilicon,hip04-ppe - - hisilicon,pcie-sas-subctrl - - hisilicon,peri-subctrl - - hpe,gxp-sysreg - - loongson,ls1b-syscon - - loongson,ls1c-syscon - - lsi,axxia-syscon - - marvell,armada-3700-cpu-misc - - marvell,armada-3700-nb-pm - - marvell,armada-3700-avs - - marvell,armada-3700-usb2-host-misc - - marvell,dove-global-config - - mediatek,mt2701-pctl-a-syscfg - - mediatek,mt2712-pctl-a-syscfg - - mediatek,mt6397-pctl-pmic-syscfg - - mediatek,mt8135-pctl-a-syscfg - - mediatek,mt8135-pctl-b-syscfg - - mediatek,mt8173-pctl-a-syscfg - - mediatek,mt8365-syscfg - - microchip,lan966x-cpu-syscon - - microchip,sam9x60-sfr - - microchip,sama7g5-ddr3phy - - mscc,ocelot-cpu-syscon - - mstar,msc313-pmsleep - - nuvoton,ma35d1-sys - - nuvoton,wpcm450-shm - - rockchip,px30-qos - - rockchip,rk3036-qos - - rockchip,rk3066-qos - - rockchip,rk3128-qos - - rockchip,rk3228-qos - - rockchip,rk3288-qos - - rockchip,rk3368-qos - - rockchip,rk3399-qos - - rockchip,rk3568-qos - - rockchip,rk3588-qos - - rockchip,rv1126-qos - - st,spear1340-misc - - stericsson,nomadik-pmu - - starfive,jh7100-sysmain - - ti,am62-opp-efuse-table - - ti,am62-usb-phy-ctrl - - ti,am625-dss-oldi-io-ctrl - - ti,am62p-cpsw-mac-efuse - - ti,am654-dss-oldi-io-ctrl - - ti,j784s4-pcie-ctrl - - ti,keystone-pllctrl - - const: syscon + oneOf: + - items: + - enum: + - al,alpine-sysfabric-service + - allwinner,sun8i-a83t-system-controller + - allwinner,sun8i-h3-system-controller + - allwinner,sun8i-v3s-system-controller + - allwinner,sun50i-a64-system-controller + - altr,l3regs + - altr,sdr-ctl + - amd,pensando-elba-syscon + - amlogic,meson-mx-assist + - amlogic,meson-mx-bootrom + - amlogic,meson8-analog-top + - amlogic,meson8b-analog-top + - amlogic,meson8-pmu + - amlogic,meson8b-pmu + - apm,merlin-poweroff-mailbox + - apm,mustang-poweroff-mailbox + - apm,xgene-csw + - apm,xgene-efuse + - apm,xgene-mcb + - apm,xgene-rb + - apm,xgene-scu + - atmel,sama5d2-sfrbu + - atmel,sama5d3-nfc-io + - atmel,sama5d3-sfrbu + - atmel,sama5d4-sfrbu + - axis,artpec6-syscon + - brcm,cru-clkset + - brcm,sr-cdru + - brcm,sr-mhb + - cirrus,ep7209-syscon1 + - cirrus,ep7209-syscon2 + - cirrus,ep7209-syscon3 + - cnxt,cx92755-uc + - freecom,fsg-cs2-system-controller + - fsl,imx93-aonmix-ns-syscfg + - fsl,imx93-wakeupmix-syscfg + - fsl,ls1088a-reset + - fsl,vf610-anatop + - fsl,vf610-mscm-cpucfg + - hisilicon,dsa-subctrl + - hisilicon,hi6220-sramctrl + - hisilicon,hip04-ppe + - hisilicon,pcie-sas-subctrl + - hisilicon,peri-subctrl + - hpe,gxp-sysreg + - loongson,ls1b-syscon + - loongson,ls1c-syscon + - lsi,axxia-syscon + - marvell,armada-3700-cpu-misc + - marvell,armada-3700-nb-pm + - marvell,armada-3700-avs + - marvell,armada-3700-usb2-host-misc + - marvell,dove-global-config + - mediatek,mt2701-pctl-a-syscfg + - mediatek,mt2712-pctl-a-syscfg + - mediatek,mt6397-pctl-pmic-syscfg + - mediatek,mt8135-pctl-a-syscfg + - mediatek,mt8135-pctl-b-syscfg + - mediatek,mt8173-pctl-a-syscfg + - mediatek,mt8365-syscfg + - microchip,lan966x-cpu-syscon + - microchip,sam9x60-sfr + - microchip,sam9x7-sfr + - microchip,sama7g5-ddr3phy + - mscc,ocelot-cpu-syscon + - mstar,msc313-pmsleep + - nuvoton,ma35d1-sys + - nuvoton,wpcm450-shm + - rockchip,px30-qos + - rockchip,rk3036-qos + - rockchip,rk3066-qos + - rockchip,rk3128-qos + - rockchip,rk3228-qos + - rockchip,rk3288-qos + - rockchip,rk3368-qos + - rockchip,rk3399-qos + - rockchip,rk3568-qos + - rockchip,rk3588-qos + - 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Signed-off-by: Varshini Rajendran Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/misc/atmel-ssc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/misc/atmel-ssc.txt b/Documen= tation/devicetree/bindings/misc/atmel-ssc.txt index f9fb412642fe..894875826de9 100644 --- a/Documentation/devicetree/bindings/misc/atmel-ssc.txt +++ b/Documentation/devicetree/bindings/misc/atmel-ssc.txt @@ -2,6 +2,7 @@ =20 Required properties: - compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc" + or "microchip,sam9x7-ssc", "atmel,at91sam9g45-ssc" - atmel,at91rm9200-ssc: support pdc transfer - atmel,at91sam9g45-ssc: support dma transfer - reg: Should contain SSC registers location and length --=20 2.25.1 From nobody Thu Sep 19 23:14:02 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5348D12C7F9; Mon, 29 Jul 2024 07:07:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236829; cv=none; b=QF6mkZ3FKTZ+qHaNeo9YywE5ISvNG+jfH9OkKw/eGNu3PnxHWE/MW5pNNqxQGMLyN9QUj4lLPk9/tKeGI0+/S4B20YDZhyl3JAmh8o+nTiQBkDfZNYphfWT3qC8lvMlSG/klQHoUxIeV+XsjRQllUzzUzN1jx0+TCUUDw5XOVqc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236829; c=relaxed/simple; bh=HvRchHRsZ8Se1MnE+Du4j5tNP8ULjzxQzw9kwHT1H1A=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=C0LNPBN7/8R7WOWJCScbkDwd4aaya0IGYHrzkdztYRmDA6Qf3EZk5A4B60zfs1McHR0HuDR5y0MhqgUqBM9ctxjcgtIDBXoRto8aWb3GU738yl+Thr+jV91nuXxdo8x9yZJ2YNCfZW4vQQVMcFizXlJpcdaZEoAaOa5hvhasJ/g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=0jzPhzcK; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="0jzPhzcK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1722236827; x=1753772827; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HvRchHRsZ8Se1MnE+Du4j5tNP8ULjzxQzw9kwHT1H1A=; b=0jzPhzcKrA59w5dzK3nZKi4TzQJKrK4EovNXG2UN1uKkycpgfJD/Xbol Bf1EuYRI3pUKNuRnfnuW3rwzdN9aOKpLlj78mpiwIkaoGNcFBqGzZ/K+j HMVeQdq3n+F0W1TvPxguUHZT/uTDleyOdfdvnPaJPPP+5yh1Ra1y8IKCP 6vy8WhFW3+VkmiLLUraOvpiSoUeh+dKK6cGJs+59R2WvCA1SVCukBdNFL bGGyuGBxnaZtjjTaKRvsaCVCLsZyk063YgsDiw7BMbM1fhNtosw1RPxdE Gp7V9nspEc6blLtNhJCje8VB8JBnKjI6BRhmLjQZHKo3dBFeCkFwd43y/ g==; X-CSE-ConnectionGUID: pQjOSLNzTjuj0oMDb/547w== X-CSE-MsgGUID: x5fW3k08Si69lrRIGDsp6w== X-IronPort-AV: E=Sophos;i="6.09,245,1716274800"; d="scan'208";a="197213805" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 29 Jul 2024 00:07:06 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 29 Jul 2024 00:06:49 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 29 Jul 2024 00:06:43 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , CC: , Conor Dooley Subject: [PATCH v6 04/27] dt-bindings: serial: atmel,at91-usart: add compatible for sam9x7. Date: Mon, 29 Jul 2024 12:36:36 +0530 Message-ID: <20240729070636.1990368-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729065603.1986074-1-varshini.rajendran@microchip.com> References: <20240729065603.1986074-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add sam9x7 compatible to DT bindings documentation. Signed-off-by: Varshini Rajendran Acked-by: Conor Dooley --- Changes in v6: - Updated the Acked-by tag. --- .../devicetree/bindings/serial/atmel,at91-usart.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml= b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml index eb2992a447d7..f466c38518c4 100644 --- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml @@ -23,13 +23,20 @@ properties: - const: atmel,at91sam9260-dbgu - const: atmel,at91sam9260-usart - items: - - const: microchip,sam9x60-usart + - enum: + - microchip,sam9x60-usart + - microchip,sam9x7-usart - const: atmel,at91sam9260-usart - items: - const: microchip,sam9x60-dbgu - const: microchip,sam9x60-usart - const: atmel,at91sam9260-dbgu - const: atmel,at91sam9260-usart + - items: + - const: microchip,sam9x7-dbgu + - const: atmel,at91sam9260-dbgu + - const: microchip,sam9x7-usart + - const: atmel,at91sam9260-usart =20 reg: maxItems: 1 --=20 2.25.1 From nobody Thu Sep 19 23:14:02 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 834AA12C7FD; Mon, 29 Jul 2024 07:07:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236829; cv=none; b=IWzoGJIhzik4rSRv/Kul0eI68AOVLc8MIE76zPTNolK+6L4EDW527BihwpS/jGeNiJj1Xen9wyRf74vGBJ5e7a4KZu+zXtvY4cTUo51pCiAQIPMuCDFkZLwjMpXzwIkVB0qfo7iqM+2rY96gtKk7hY/H0rPV05QM0ZhGp1A8Pxs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236829; c=relaxed/simple; bh=PSn+93YxahuM4/eEil9r4edmIQw42eptfiHBu+CeLF0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MgIdjUF3SNURuZPA/ajOMqPUorG2Pji0OwL3kwCNmZPTWnGPGe84TwAcjfnTdpT+OSomsz4xmo4vYiuVEuuSx04vxGX0/OfA3o7/D6EjIKuORq0lBrIs5lxgt2nxZQubZ6BlJT1BuiZ0BqIC1IAxgbLbYj3YWqXTorCy2iasWRA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=CISnNhmX; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="CISnNhmX" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1722236828; x=1753772828; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PSn+93YxahuM4/eEil9r4edmIQw42eptfiHBu+CeLF0=; b=CISnNhmX4A0Ka59HNgpTR1BOZYhCRxOco/OTM4A/SJXr6WHjXOeBmtVM AOtBPo+aJMDgdP7M8TBO60jlZhkdD7nYl20WYi0gsuMP8p3r8jKzKgGG6 ZNhCINJCRQ1dnAdOiHdbzlV2ls+YQTHjIBM4P1kuY1DwFLDNjc4VqOMad cmFGhmDoSde7tIXPP2+8r/DjLrt4YiGCaoSkwTimbbm1UlUNL52+KN0fR dWm4Bv5xoMGEmDhW3KyZiROnzbqIiWQQktEFvQ9Jn5uCib+2qwZYJaCa7 fMM7owor9lU/a9LI5JLrptqMmIaaRGOIrc1R9SB+UaciI5TJ+fvpXEsYt g==; X-CSE-ConnectionGUID: pQjOSLNzTjuj0oMDb/547w== X-CSE-MsgGUID: yLpZle7ZSI6AhsOFjTjvyw== X-IronPort-AV: E=Sophos;i="6.09,245,1716274800"; d="scan'208";a="197213810" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 29 Jul 2024 00:07:06 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 29 Jul 2024 00:06:58 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 29 Jul 2024 00:06:54 -0700 From: Varshini Rajendran To: , , , , , , , , CC: Subject: [PATCH v6 05/27] dt-bindings: microchip: atmel,at91rm9200-tcb: add sam9x7 compatible Date: Mon, 29 Jul 2024 12:36:49 +0530 Message-ID: <20240729070649.1990427-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729065603.1986074-1-varshini.rajendran@microchip.com> References: <20240729065603.1986074-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for sam9x7 device compatible. Signed-off-by: Varshini Rajendran --- Changes in v6: - New patch in v6 to document tcb compatible. --- .../soc/microchip/atmel,at91rm9200-tcb.yaml | 20 ++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm92= 00-tcb.yaml b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9= 200-tcb.yaml index a46411149571..2c7275c4503b 100644 --- a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.= yaml +++ b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.= yaml @@ -15,13 +15,19 @@ description: | =20 properties: compatible: - items: - - enum: - - atmel,at91rm9200-tcb - - atmel,at91sam9x5-tcb - - atmel,sama5d2-tcb - - const: simple-mfd - - const: syscon + oneOf: + - items: + - enum: + - atmel,at91rm9200-tcb + - atmel,at91sam9x5-tcb + - atmel,sama5d2-tcb + - const: simple-mfd + - const: syscon + - items: + - const: microchip,sam9x7-tcb + - const: atmel,sama5d2-tcb + - const: simple-mfd + - const: syscon =20 reg: maxItems: 1 --=20 2.25.1 From nobody Thu Sep 19 23:14:02 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42ECC86AE3 for ; Mon, 29 Jul 2024 07:07:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236830; cv=none; b=qSFMlV3mZKInQFJjdG/UfhKi94PaYYac/gwrqT0M6sxqX1smVpoWi/XLShIzm3xBnhiy2/+M9IZGq6R4AaiYstKub1o0DWqasdSkRlnwITTP33dOW3+QKi/hRi0X7D+miZxhMoTQy1dmIFjtGbvr6EmbFK7P4KcaOYAH7QIN0uE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236830; c=relaxed/simple; bh=QH6iVLDsFa2jo+SBqkx8ftjMcYybPbIGSfZAEccKHgc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ktHTN4tm03SaRWXTRAj5DjnNNTmB/uTv0mOiD9YeXR7jg1P+shQSYAbq5J9HRrT1kVm5YRUbPTdbzRM97IiQ8Zq0puFZZ6ITM3cFMqdWP/hQ1dEadcpyCsZ7UKlRQCXdigrKgxmRZWcqatGDxVVmcERqsx5Coh9RT56/2afruJE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Y2pCf0Mt; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Y2pCf0Mt" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1722236829; x=1753772829; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QH6iVLDsFa2jo+SBqkx8ftjMcYybPbIGSfZAEccKHgc=; b=Y2pCf0MtGbvioUd3OQ7ObKo7dDgiGgJsDXbFDqhjTqis2+J5g64REaGK YBWDCA2+/LFyJZZRey3ONTiaIJNsIuhQl/gIDV8cvpzP8NHzjNFGEALot JujCaYiAKFJKjoDLnkVKL7oFsU2g9GcYWO3zqkr/FXXi04VfkuSuPbZ41 +/yd/9ahU7t3V9CaKTWg9ym2P8hRJdniO3AQPGTeYWlFermvIc1HrgURY kncggZTdsFsEHcWAR5fO6MabWYCuDFeZJ7NEp339mjnuHmUE4j3rxXDy4 jKJZ9D0KUpSGXLbEEeBbO6PfwRPSagoFFPGwMh6oTSLPmoflmp2g3lUwm w==; X-CSE-ConnectionGUID: pQjOSLNzTjuj0oMDb/547w== X-CSE-MsgGUID: bpiantCIRn6jzEOqMW+n7g== X-IronPort-AV: E=Sophos;i="6.09,245,1716274800"; d="scan'208";a="197213812" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 29 Jul 2024 00:07:07 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 29 Jul 2024 00:07:05 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 29 Jul 2024 00:07:01 -0700 From: Varshini Rajendran To: , , , , , CC: , Claudiu Beznea Subject: [PATCH v6 06/27] ARM: at91: pm: add support for sam9x7 SoC family Date: Mon, 29 Jul 2024 12:36:59 +0530 Message-ID: <20240729070659.1990506-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729065603.1986074-1-varshini.rajendran@microchip.com> References: <20240729065603.1986074-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support and pm init config for sam9x7 SoC. Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- Changes in v6: - Sorted the compatibles alphanumerically. --- arch/arm/mach-at91/generic.h | 2 ++ arch/arm/mach-at91/pm.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 0c3960a8b3eb..acf0b3c82a30 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -12,6 +12,7 @@ extern void __init at91rm9200_pm_init(void); extern void __init at91sam9_pm_init(void); extern void __init sam9x60_pm_init(void); +extern void __init sam9x7_pm_init(void); extern void __init sama5_pm_init(void); extern void __init sama5d2_pm_init(void); extern void __init sama7_pm_init(void); @@ -19,6 +20,7 @@ extern void __init sama7_pm_init(void); static inline void __init at91rm9200_pm_init(void) { } static inline void __init at91sam9_pm_init(void) { } static inline void __init sam9x60_pm_init(void) { } +static inline void __init sam9x7_pm_init(void) { } static inline void __init sama5_pm_init(void) { } static inline void __init sama5d2_pm_init(void) { } static inline void __init sama7_pm_init(void) { } diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 345b91dc6627..b9b995f8a36e 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -233,6 +233,13 @@ static const struct of_device_id sama7g5_ws_ids[] =3D { { /* sentinel */ } }; =20 +static const struct of_device_id sam9x7_ws_ids[] =3D { + { .compatible =3D "microchip,sam9x7-rtc", .data =3D &ws_info[1] }, + { .compatible =3D "microchip,sam9x7-rtt", .data =3D &ws_info[4] }, + { .compatible =3D "microchip,sam9x7-gem", .data =3D &ws_info[5] }, + { /* sentinel */ } +}; + static int at91_pm_config_ws(unsigned int pm_mode, bool set) { const struct wakeup_source_info *wsi; @@ -1361,6 +1368,7 @@ static const struct of_device_id atmel_pmc_ids[] __in= itconst =3D { { .compatible =3D "atmel,sama5d4-pmc", .data =3D &pmc_infos[1] }, { .compatible =3D "atmel,sama5d2-pmc", .data =3D &pmc_infos[1] }, { .compatible =3D "microchip,sam9x60-pmc", .data =3D &pmc_infos[4] }, + { .compatible =3D "microchip,sam9x7-pmc", .data =3D &pmc_infos[4] }, { .compatible =3D "microchip,sama7g5-pmc", .data =3D &pmc_infos[5] }, { /* sentinel */ }, }; @@ -1499,6 +1507,27 @@ void __init sam9x60_pm_init(void) soc_pm.config_pmc_ws =3D at91_sam9x60_config_pmc_ws; } =20 +void __init sam9x7_pm_init(void) +{ + static const int modes[] __initconst =3D { + AT91_PM_STANDBY, AT91_PM_ULP0, + }; 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Mon, 29 Jul 2024 00:07:10 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 29 Jul 2024 00:07:08 -0700 From: Varshini Rajendran To: , , , , , CC: Subject: [PATCH v6 07/27] ARM: at91: pm: add sam9x7 SoC init config Date: Mon, 29 Jul 2024 12:37:05 +0530 Message-ID: <20240729070705.1990557-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729065603.1986074-1-varshini.rajendran@microchip.com> References: <20240729065603.1986074-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add SoC init config for sam9x7 family. Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- Changes in v6: - Updated Reviewed-by tag. --- arch/arm/mach-at91/Makefile | 1 + arch/arm/mach-at91/sam9x7.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 arch/arm/mach-at91/sam9x7.c diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 794bd12ab0a8..7d8a7bc44e65 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_SOC_AT91RM9200) +=3D at91rm9200.o obj-$(CONFIG_SOC_AT91SAM9) +=3D at91sam9.o obj-$(CONFIG_SOC_SAM9X60) +=3D sam9x60.o +obj-$(CONFIG_SOC_SAM9X7) +=3D sam9x7.o obj-$(CONFIG_SOC_SAMA5) +=3D sama5.o sam_secure.o obj-$(CONFIG_SOC_SAMA7) +=3D sama7.o obj-$(CONFIG_SOC_SAMV7) +=3D samv7.o diff --git a/arch/arm/mach-at91/sam9x7.c b/arch/arm/mach-at91/sam9x7.c new file mode 100644 index 000000000000..e1ff30b5b09b --- /dev/null +++ b/arch/arm/mach-at91/sam9x7.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Setup code for SAM9X7. + * + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + */ + +#include +#include + +#include + +#include "generic.h" + +static void __init sam9x7_init(void) +{ + of_platform_default_populate(NULL, NULL, NULL); + + sam9x7_pm_init(); +} + +static const char * const sam9x7_dt_board_compat[] __initconst =3D { + "microchip,sam9x7", + NULL +}; + +DT_MACHINE_START(sam9x7_dt, "Microchip SAM9X7") + /* Maintainer: Microchip */ + .init_machine =3D sam9x7_init, + .dt_compat =3D sam9x7_dt_board_compat, +MACHINE_END --=20 2.25.1 From nobody Thu Sep 19 23:14:02 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 540B012CDBE for ; Mon, 29 Jul 2024 07:07:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236877; cv=none; b=EVNisa3TEPRJYNvvD+tty+Rz3r+9eUBJp5LL6a1kKyasM8BsYG3jbz6dxR6YnXPdAC9DwK3m1XHaucwWHEn/os/NNomYdVsaJs1bp2gQYv0sxMQSNnQ2wrrJJRa+dliMGAG+aVWaCvc6BKxJ2XKF7MJ0+OzW1yBC7yu0/LY9FjM= ARC-Message-Signature: i=1; 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Mon, 29 Jul 2024 00:07:16 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 29 Jul 2024 00:07:14 -0700 From: Varshini Rajendran To: , , , , , CC: Claudiu Beznea Subject: [PATCH v6 08/27] ARM: at91: add support in SoC driver for new sam9x7 Date: Mon, 29 Jul 2024 12:37:11 +0530 Message-ID: <20240729070711.1990605-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729065603.1986074-1-varshini.rajendran@microchip.com> References: <20240729065603.1986074-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for SAM9X7 SoC in the SoC driver. Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- drivers/soc/atmel/soc.c | 23 +++++++++++++++++++++++ drivers/soc/atmel/soc.h | 9 +++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c index cc9a3e107479..2a42b28931c9 100644 --- a/drivers/soc/atmel/soc.c +++ b/drivers/soc/atmel/soc.c @@ -101,6 +101,29 @@ static const struct at91_soc socs[] __initconst =3D { AT91_CIDR_VERSION_MASK, SAM9X60_D6K_EXID_MATCH, "sam9x60 8MiB SDRAM SiP", "sam9x60"), #endif +#ifdef CONFIG_SOC_SAM9X7 + AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAM9X70_EXID_MATCH, + "sam9x70", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAM9X72_EXID_MATCH, + "sam9x72", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1M_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75 16MB DDR2 SiP", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D5M_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75 64MB DDR2 SiP", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1G_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75 125MB DDR3L SiP ", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D2G_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75 250MB DDR3L SiP", "sam9x7"), +#endif #ifdef CONFIG_SOC_SAMA5 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH, diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h index 7a9f47ce85fb..2c78e54255f7 100644 --- a/drivers/soc/atmel/soc.h +++ b/drivers/soc/atmel/soc.h @@ -44,6 +44,7 @@ at91_soc_init(const struct at91_soc *socs); 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charset="utf-8" Add bindings for SAM9X7's slow clock controller. Signed-off-by: Varshini Rajendran Acked-by: Conor Dooley Reviewed-by: Claudiu Beznea --- Changes in v6: - Corrected the subject line - Updated Reviewed-by tag --- .../devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.= yaml b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml index 7be29877e6d2..c2283cd07f05 100644 --- a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml +++ b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml @@ -18,7 +18,9 @@ properties: - atmel,sama5d4-sckc - microchip,sam9x60-sckc - items: - - const: microchip,sama7g5-sckc + - enum: + - microchip,sam9x7-sckc + - microchip,sama7g5-sckc - const: microchip,sam9x60-sckc =20 reg: --=20 2.25.1 From nobody Thu Sep 19 23:14:02 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BDF4D84DEB; Mon, 29 Jul 2024 07:07:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236866; cv=none; b=CLyxIuqOcNpP8TIR6RVhfyC2r6dQUD+jSKVeDMD3ynAclzZqxZiM78hYL0gQOsSlEFPIyWmHMjYa0GEtwAXm+2oxZB4dzmeq3UGFUnFzAvlgCoAJ5DmmG89Nf0aShvApXuWOkNpzyMeC8CNA5n/xTds4OxM+pEsGWE7UVHOPHgk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236866; c=relaxed/simple; bh=fDqE0tBeSlSB34dZ9C+ua0ag8uXX5Nqi4XoXWGufPtw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=CUaJB/7V4GCrtmzUA1P3BAk0fl9qz6SiEyelZaDM8WfHtaXUkvTS/eWDf3FP7+ivruKJjqJGMs5lr0bh6JzSUsgnnaUbLPd57zJQ6nPSN/eFNO9ZxT8JNDlACFPNPJvF5Ph19r953+/llgPtXVaNcQfmEaCcHkTiIiTsObj2ses= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=ufcfvTrR; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="ufcfvTrR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1722236864; x=1753772864; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fDqE0tBeSlSB34dZ9C+ua0ag8uXX5Nqi4XoXWGufPtw=; b=ufcfvTrRbEju8QF/hrMAiG8GDaUE9bGN12e5g4+D/emGoKar1t+7PG+e mtWw6DMWgpqpxhu2gERjek/PG8tIxPe7Q36s+UCIQgUBC9jpxcMiwAE8c xbZYYJYMXsR1yR10lgt1+LOIndle8u7Am/CKgYIBrW7eI3kPEAI/I50qh pOTSAom2PK7vZEq13IU/dipYpJ+EhUTMJsHY5Li+iWIJQzKjKDaYbeDot GOU53e6qKDj32eHcAQfysF2aoavUl20RoBpIR2xgwp2h63QedEYi7YSOW 8BCPymepg2fePNIfGZJACB24mWAytJ6mnbG509RbQWKsbvD3Z90isQioE w==; X-CSE-ConnectionGUID: qXa6hTCZRDuoKzAisfRBPw== X-CSE-MsgGUID: LdKhooi9QLqydwfPPztv2w== X-IronPort-AV: E=Sophos;i="6.09,245,1716274800"; d="scan'208";a="197213861" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 29 Jul 2024 00:07:43 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 29 Jul 2024 00:07:37 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 29 Jul 2024 00:07:32 -0700 From: Varshini Rajendran To: , , , , , , , , , , , CC: , Conor Dooley Subject: [PATCH v6 10/27] dt-bindings: clocks: atmel,at91rm9200-pmc: add sam9x7 clock controller Date: Mon, 29 Jul 2024 12:37:26 +0530 Message-ID: <20240729070726.1990705-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729065603.1986074-1-varshini.rajendran@microchip.com> References: <20240729065603.1986074-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add bindings for SAM9X7's pmc. Signed-off-by: Varshini Rajendran Acked-by: Conor Dooley Reviewed-by: Claudiu Beznea --- Changes in v6: - Corrected the subject line - Updated Reviewed-by tag --- .../devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.y= aml b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml index c1bdcd9058ed..c9eb60776b4d 100644 --- a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml +++ b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml @@ -42,6 +42,7 @@ properties: - atmel,sama5d3-pmc - atmel,sama5d4-pmc - microchip,sam9x60-pmc + - microchip,sam9x7-pmc - microchip,sama7g5-pmc - const: syscon =20 @@ -88,6 +89,7 @@ allOf: contains: enum: - microchip,sam9x60-pmc + - microchip,sam9x7-pmc - microchip,sama7g5-pmc then: properties: --=20 2.25.1 From nobody Thu Sep 19 23:14:02 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DABA012FF65; Mon, 29 Jul 2024 07:07:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236880; cv=none; b=YB+4YKyeraPG3JNYPTsB5SHlYnZFMgBwDpfV92tss8L4sY0vGdl8YRgPttqXmVCPOFlSIuWinifX1T5Hr9GvFCipUzVJJZ+X9Hb13so0hsJsiRjpHVrj2TQyXDxhfrZZmnEqAt5GE99rDE/vc13iK+6ntk1eYJ6bt14N5uT+IPo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236880; c=relaxed/simple; bh=q5323n++TaWWMADTjdvqcpdyQh2QIVsYWT8VC7rVzdM=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qyiYX6vGr+kDgrR2CNMrpHAB42a94IdBSbJfrWcMoJerl8m3ZNX+uOoeG1pW4szdHe6GN7+siXPSeUXZu7kwkNDfUr0DpV5/e/EHzfkvzYIFUkYFgjWk5SNaCPbO8w9hJhiMdBbxnZtOsAqK874VdQKhPZrjtNVf0p+lAmDouRI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=EBT6V+oR; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="EBT6V+oR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1722236879; x=1753772879; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=q5323n++TaWWMADTjdvqcpdyQh2QIVsYWT8VC7rVzdM=; b=EBT6V+oRa81euc875o0rY1XywVcC6ABB/6Wg7IDk9wI6GqkvQ0i8Us2p ratwGa/UGRfamGert5cd+QS6pB6Vo/DOHffqa1/MmgDRchHpTE0D5+heW 0aF8OnP1yED3aLIE+lBSmviSC6LGGb9skxJZLbt93CFX0SptosaHjTtNg tRERAiP1cebd43atqNNYJxzMaG0un+oj8+84swFTlRZeGPz2XjiWkg95X C54w4nGvyLaPbQ8ZXp2jiv8L9zh5piehJu0TW0IbEcQ9W0pdyWoxizdAp O/w2GlG/3hyiCTMvDlN4mX+EEZHPhr2PyXi8l1/4516OhsaZsj9NdOZCX Q==; X-CSE-ConnectionGUID: R9YWgj/LTvO//sJgAksALA== X-CSE-MsgGUID: CMKpmI9kR26ayQxAfUj0AA== X-IronPort-AV: E=Sophos;i="6.09,245,1716274800"; d="scan'208";a="30454114" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 29 Jul 2024 00:07:58 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 29 Jul 2024 00:07:45 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 29 Jul 2024 00:07:42 -0700 From: Varshini Rajendran To: , , , , , , , , Subject: [PATCH v6 11/27] clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs Date: Mon, 29 Jul 2024 12:37:37 +0530 Message-ID: <20240729070737.1990756-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729065603.1986074-1-varshini.rajendran@microchip.com> References: <20240729065603.1986074-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SAM9X7 SoC family supports different core output frequencies for different PLL IDs. To handle the same in the PLL driver, a separate parameter core_output is added. The sam9x60 and sama7g5 SoC PMC drivers are aligned to the PLL driver by adding the core output freq range in the PLL characteristics configurations. Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- Changes in v6: - Updated Reviewed-by tag --- drivers/clk/at91/clk-sam9x60-pll.c | 12 ++++++------ drivers/clk/at91/pmc.h | 1 + drivers/clk/at91/sam9x60.c | 7 +++++++ drivers/clk/at91/sama7g5.c | 7 +++++++ 4 files changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9= x60-pll.c index ff65f7b916f0..b0314dfd7393 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -23,9 +23,6 @@ #define UPLL_DIV 2 #define PLL_MUL_MAX (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1) =20 -#define FCORE_MIN (600000000) -#define FCORE_MAX (1200000000) - #define PLL_MAX_ID 7 =20 struct sam9x60_pll_core { @@ -194,7 +191,8 @@ static long sam9x60_frac_pll_compute_mul_frac(struct sa= m9x60_pll_core *core, unsigned long nmul =3D 0; unsigned long nfrac =3D 0; =20 - if (rate < FCORE_MIN || rate > FCORE_MAX) + if (rate < core->characteristics->core_output[0].min || + rate > core->characteristics->core_output[0].max) return -ERANGE; =20 /* @@ -214,7 +212,8 @@ static long sam9x60_frac_pll_compute_mul_frac(struct sa= m9x60_pll_core *core, } =20 /* Check if resulted rate is a valid. */ - if (tmprate < FCORE_MIN || tmprate > FCORE_MAX) + if (tmprate < core->characteristics->core_output[0].min || + tmprate > core->characteristics->core_output[0].max) return -ERANGE; =20 if (update) { @@ -669,7 +668,8 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, sp= inlock_t *lock, goto free; } =20 - ret =3D sam9x60_frac_pll_compute_mul_frac(&frac->core, FCORE_MIN, + ret =3D sam9x60_frac_pll_compute_mul_frac(&frac->core, + characteristics->core_output[0].min, parent_rate, true); if (ret < 0) { hw =3D ERR_PTR(ret); diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 0f52e80bcd49..bb9da35198d9 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -75,6 +75,7 @@ struct clk_pll_characteristics { struct clk_range input; int num_output; const struct clk_range *output; + const struct clk_range *core_output; u16 *icpll; u8 *out; u8 upll : 1; diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index e309cbf3cb9a..db6db9e2073e 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -26,10 +26,16 @@ static const struct clk_range plla_outputs[] =3D { { .min =3D 2343750, .max =3D 1200000000 }, }; =20 +/* Fractional PLL core output range. */ +static const struct clk_range core_outputs[] =3D { + { .min =3D 600000000, .max =3D 1200000000 }, +}; + static const struct clk_pll_characteristics plla_characteristics =3D { .input =3D { .min =3D 12000000, .max =3D 48000000 }, .num_output =3D ARRAY_SIZE(plla_outputs), .output =3D plla_outputs, + .core_output =3D core_outputs, }; =20 static const struct clk_range upll_outputs[] =3D { @@ -40,6 +46,7 @@ static const struct clk_pll_characteristics upll_characte= ristics =3D { .input =3D { .min =3D 12000000, .max =3D 48000000 }, .num_output =3D ARRAY_SIZE(upll_outputs), .output =3D upll_outputs, + .core_output =3D core_outputs, .upll =3D true, }; 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charset="utf-8" Add support for hardware dividers for PLL IDs in sam9x7 SoC. The system PLL - PLLA and the system PLL divided by 2 - PLLADIV2 with PLL ID 0 and 4 respectively, both have a hardware divider /2. This has to be taken into account in the software to obtain the right frequencies. Support for the same is added in the PLL driver. fcorepllack -----> HW Div =3D 2 -+--> fpllack | +--> HW Div =3D 2 ---> fplladiv2ck In this case the corepll freq is 1600 MHz. So, the plla freq is 800 MHz after the hardware divider and the plladiv2 freq is 400 MHz after the hardware divider (given that the DIVPMC is 0). Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- Changes in v6: - Updated Reviewed-by tag --- drivers/clk/at91/clk-sam9x60-pll.c | 30 ++++++++++++++++++++++++++++-- drivers/clk/at91/pmc.h | 1 + 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9= x60-pll.c index b0314dfd7393..fda041102224 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -73,9 +73,15 @@ static unsigned long sam9x60_frac_pll_recalc_rate(struct= clk_hw *hw, { struct sam9x60_pll_core *core =3D to_sam9x60_pll_core(hw); struct sam9x60_frac *frac =3D to_sam9x60_frac(core); + unsigned long freq; =20 - return parent_rate * (frac->mul + 1) + + freq =3D parent_rate * (frac->mul + 1) + DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22)); + + if (core->layout->div2) + freq >>=3D 1; + + return freq; } =20 static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core) @@ -432,6 +438,12 @@ static unsigned long sam9x60_div_pll_recalc_rate(struc= t clk_hw *hw, return DIV_ROUND_CLOSEST_ULL(parent_rate, (div->div + 1)); } =20 +static unsigned long sam9x60_fixed_div_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return parent_rate >> 1; +} + static long sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core, unsigned long *parent_rate, unsigned long rate) @@ -606,6 +618,16 @@ static const struct clk_ops sam9x60_div_pll_ops_chg = =3D { .restore_context =3D sam9x60_div_pll_restore_context, }; =20 +static const struct clk_ops sam9x60_fixed_div_pll_ops =3D { + .prepare =3D sam9x60_div_pll_prepare, + .unprepare =3D sam9x60_div_pll_unprepare, + .is_prepared =3D sam9x60_div_pll_is_prepared, + .recalc_rate =3D sam9x60_fixed_div_pll_recalc_rate, + .round_rate =3D sam9x60_div_pll_round_rate, + .save_context =3D sam9x60_div_pll_save_context, + .restore_context =3D sam9x60_div_pll_restore_context, +}; + struct clk_hw * __init sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, const char *name, const char *parent_name, @@ -725,10 +747,14 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, s= pinlock_t *lock, else init.parent_names =3D &parent_name; init.num_parents =3D 1; - if (flags & CLK_SET_RATE_GATE) + + if (layout->div2) + init.ops =3D &sam9x60_fixed_div_pll_ops; + else if (flags & CLK_SET_RATE_GATE) init.ops =3D &sam9x60_div_pll_ops; else init.ops =3D &sam9x60_div_pll_ops_chg; + init.flags =3D flags; =20 div->core.id =3D id; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index bb9da35198d9..91d1c6305d95 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -64,6 +64,7 @@ struct clk_pll_layout { u8 frac_shift; u8 div_shift; u8 endiv_shift; + u8 div2; }; =20 extern const struct clk_pll_layout at91rm9200_pll_layout; --=20 2.25.1 From nobody Thu Sep 19 23:14:02 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D04F786AE9; Mon, 29 Jul 2024 07:08:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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d="scan'208";a="197213911" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 29 Jul 2024 00:08:24 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 29 Jul 2024 00:08:03 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 29 Jul 2024 00:07:59 -0700 From: Varshini Rajendran To: , , , , , , , , Subject: [PATCH v6 13/27] clk: at91: sama7g5: move mux table macros to header file Date: Mon, 29 Jul 2024 12:37:53 +0530 Message-ID: <20240729070753.1990866-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729065603.1986074-1-varshini.rajendran@microchip.com> References: <20240729065603.1986074-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move the mux table init and fill macro function definitions from the sama7g5 pmc driver to the pmc.h header file since they will be used by other SoC's pmc drivers as well like sam9x7. Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- Changes in v6: - Updated Reviewed-by tag --- drivers/clk/at91/pmc.h | 16 ++++++++++++++++ drivers/clk/at91/sama7g5.c | 35 ++++++++++------------------------- 2 files changed, 26 insertions(+), 25 deletions(-) diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 91d1c6305d95..4fb29ca111f7 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -121,6 +121,22 @@ struct at91_clk_pms { =20 #define ndck(a, s) (a[s - 1].id + 1) #define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1) + +#define PMC_INIT_TABLE(_table, _count) \ + do { \ + u8 _i; \ + for (_i =3D 0; _i < (_count); _i++) \ + (_table)[_i] =3D _i; \ + } while (0) + +#define PMC_FILL_TABLE(_to, _from, _count) \ + do { \ + u8 _i; \ + for (_i =3D 0; _i < (_count); _i++) { \ + (_to)[_i] =3D (_from)[_i]; \ + } \ + } while (0) + struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsyste= m, unsigned int nperiph, unsigned int ngck, unsigned int npck); diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index e6eb5afba93d..6706d1305baa 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -16,21 +16,6 @@ =20 #include "pmc.h" =20 -#define SAMA7G5_INIT_TABLE(_table, _count) \ - do { \ - u8 _i; \ - for (_i =3D 0; _i < (_count); _i++) \ - (_table)[_i] =3D _i; \ - } while (0) - -#define SAMA7G5_FILL_TABLE(_to, _from, _count) \ - do { \ - u8 _i; \ - for (_i =3D 0; _i < (_count); _i++) { \ - (_to)[_i] =3D (_from)[_i]; \ - } \ - } while (0) - static DEFINE_SPINLOCK(pmc_pll_lock); static DEFINE_SPINLOCK(pmc_mck0_lock); static DEFINE_SPINLOCK(pmc_mckX_lock); @@ -1119,17 +1104,17 @@ static void __init sama7g5_pmc_setup(struct device_= node *np) if (!mux_table) goto err_free; =20 - SAMA7G5_INIT_TABLE(mux_table, 3); - SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table, - sama7g5_mckx[i].ep_count); + PMC_INIT_TABLE(mux_table, 3); + PMC_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table, + sama7g5_mckx[i].ep_count); for (j =3D 0; j < sama7g5_mckx[i].ep_count; j++) { u8 pll_id =3D sama7g5_mckx[i].ep[j].pll_id; u8 pll_compid =3D sama7g5_mckx[i].ep[j].pll_compid; =20 tmp_parent_hws[j] =3D sama7g5_plls[pll_id][pll_compid].hw; } - SAMA7G5_FILL_TABLE(&parent_hws[3], tmp_parent_hws, - sama7g5_mckx[i].ep_count); + PMC_FILL_TABLE(&parent_hws[3], tmp_parent_hws, + sama7g5_mckx[i].ep_count); =20 hw =3D at91_clk_sama7g5_register_master(regmap, sama7g5_mckx[i].n, num_parents, NULL, parent_hws, mux_table, @@ -1215,17 +1200,17 @@ static void __init sama7g5_pmc_setup(struct device_= node *np) if (!mux_table) goto err_free; =20 - SAMA7G5_INIT_TABLE(mux_table, 3); - SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table, - sama7g5_gck[i].pp_count); + PMC_INIT_TABLE(mux_table, 3); + PMC_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table, + sama7g5_gck[i].pp_count); for (j =3D 0; j < sama7g5_gck[i].pp_count; j++) { u8 pll_id =3D sama7g5_gck[i].pp[j].pll_id; u8 pll_compid =3D sama7g5_gck[i].pp[j].pll_compid; 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Mon, 29 Jul 2024 00:08:10 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 29 Jul 2024 00:08:06 -0700 From: Varshini Rajendran To: , , , , , , , , , , , CC: Subject: [PATCH v6 14/27] dt-bindings: clock: at91: Allow PLLs to be exported and referenced in DT Date: Mon, 29 Jul 2024 12:38:03 +0530 Message-ID: <20240729070803.1990916-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729065603.1986074-1-varshini.rajendran@microchip.com> References: <20240729065603.1986074-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allow PLLADIV2 and LVDSPLL to be referenced as a PMC_TYPE_CORE clock from phandle in DT for sam9x7 SoC family. Signed-off-by: Varshini Rajendran Acked-by: Rob Herring Reviewed-by: Claudiu Beznea --- Changes in v6: - Updated Reviewed-by tag --- include/dt-bindings/clock/at91.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/a= t91.h index 3e3972a814c1..6ede88c3992d 100644 --- a/include/dt-bindings/clock/at91.h +++ b/include/dt-bindings/clock/at91.h @@ -38,6 +38,10 @@ #define PMC_CPU (PMC_MAIN + 9) #define PMC_MCK1 (PMC_MAIN + 10) =20 +/* SAM9X7 */ +#define PMC_PLLADIV2 (PMC_MAIN + 11) +#define PMC_LVDSPLL (PMC_MAIN + 12) + #ifndef AT91_PMC_MOSCS #define AT91_PMC_MOSCS 0 /* MOSCS Flag */ #define AT91_PMC_LOCKA 1 /* PLLA Lock */ --=20 2.25.1 From nobody Thu Sep 19 23:14:02 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E048126F2A; Mon, 29 Jul 2024 07:08:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236908; cv=none; b=Sql10HV5EWRRBOSEsqUWgok9xJpbqLbv4vfTVySAOZHtQeJs4cgWmu40u41zTW/N3wforNuSfBJ4e21oloWGZoQbmJzGA1uYzv64DAfCM7puYgfb18pqrqj0NzoFUWljj/UA6Bjd0vsnesA8Bl4q0gDbO38164hMW288ZwcbeWA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236908; c=relaxed/simple; bh=woEdkpezRGzhxS7IRa42zWfoMJ/y2xnPWTkcni7d7Mk=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nD93QWCfYUxJ2Pbe7RnSxWzDoKSt8zaVvLBO99C3llNPGfHHZpDx87LkYSQvnme6Z3pXKBDv/eSoO+8ooY+yCMb+XbvHeMjZAG7bIwE7wm1oH7CXywFb5kLIJuBIOU06d0UdkE4T6etBh6XJXlHECzSro2rx3QcNzDJnikaax0Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=xVKgYYgF; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="xVKgYYgF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1722236906; x=1753772906; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=woEdkpezRGzhxS7IRa42zWfoMJ/y2xnPWTkcni7d7Mk=; b=xVKgYYgFYvmxQagmYkBBxcGCv4JFplajxa+ihPwyogzWBMAtvTGyJHfA nv0w7tn9ZKaJ0ToAjy05yU2oderwZ0Ag4gQ9ivJ9fc0FOooX7sB3bbUmX hZBmU00/Z1rHjl5PtmgdtLd0cVEb9NXxARuqT6HcOrNK37hrOk/aAJ9Nn 9qdk25Mctpj0ohLXUlR4KWLVcu3o+5HlgqIBETLHGOzJhImb5UJ3pV560 y5lZw7wZVBV6r5ZCQ0Ws2ZIipQO+cRGbE91r6n4428QTq8ais6ib+lYX9 7K2XDVGJ8dt4c9ZVOCGnhMZmU68aPoqh5GzjXcohqNMxvJHRw8v5So5xi w==; X-CSE-ConnectionGUID: v1dANIOrTaeFXifMe9veag== X-CSE-MsgGUID: CbjkmHbHT0e2VfaNyM3L7w== X-IronPort-AV: E=Sophos;i="6.09,245,1716274800"; d="scan'208";a="197213933" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 29 Jul 2024 00:08:24 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 29 Jul 2024 00:08:17 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 29 Jul 2024 00:08:13 -0700 From: Varshini Rajendran To: , , , , , , , , Subject: [PATCH v6 15/27] clk: at91: sam9x7: add sam9x7 pmc driver Date: Mon, 29 Jul 2024 12:38:11 +0530 Message-ID: <20240729070811.1990964-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729065603.1986074-1-varshini.rajendran@microchip.com> References: <20240729065603.1986074-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a driver for the PMC clocks of sam9x7 Soc family. Signed-off-by: Varshini Rajendran --- Changes in v6: - Changed the 2D array coloumn size from PLL_MAX_ID to 3. --- drivers/clk/at91/Makefile | 1 + drivers/clk/at91/sam9x7.c | 946 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 947 insertions(+) create mode 100644 drivers/clk/at91/sam9x7.c diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile index 89061b85e7d2..8e3684ba2c74 100644 --- a/drivers/clk/at91/Makefile +++ b/drivers/clk/at91/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_SOC_AT91SAM9) +=3D at91sam9260.o at91sam9rl.= o at91sam9x5.o dt-compat. obj-$(CONFIG_SOC_AT91SAM9) +=3D at91sam9g45.o dt-compat.o obj-$(CONFIG_SOC_AT91SAM9) +=3D at91sam9n12.o at91sam9x5.o dt-compat.o obj-$(CONFIG_SOC_SAM9X60) +=3D sam9x60.o +obj-$(CONFIG_SOC_SAM9X7) +=3D sam9x7.o obj-$(CONFIG_SOC_SAMA5D3) +=3D sama5d3.o dt-compat.o obj-$(CONFIG_SOC_SAMA5D4) +=3D sama5d4.o dt-compat.o obj-$(CONFIG_SOC_SAMA5D2) +=3D sama5d2.o dt-compat.o diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c new file mode 100644 index 000000000000..cbb8b220f16b --- /dev/null +++ b/drivers/clk/at91/sam9x7.c @@ -0,0 +1,946 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SAM9X7 PMC code. + * + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + * + */ +#include +#include +#include +#include + +#include + +#include "pmc.h" + +static DEFINE_SPINLOCK(pmc_pll_lock); +static DEFINE_SPINLOCK(mck_lock); + +/** + * enum pll_ids - PLL clocks identifiers + * @PLL_ID_PLLA: PLLA identifier + * @PLL_ID_UPLL: UPLL identifier + * @PLL_ID_AUDIO: Audio PLL identifier + * @PLL_ID_LVDS: LVDS PLL identifier + * @PLL_ID_PLLA_DIV2: PLLA DIV2 identifier + * @PLL_ID_MAX: Max PLL Identifier + */ +enum pll_ids { + PLL_ID_PLLA, + PLL_ID_UPLL, + PLL_ID_AUDIO, + PLL_ID_LVDS, + PLL_ID_PLLA_DIV2, + PLL_ID_MAX, +}; + +/** + * enum pll_type - PLL type identifiers + * @PLL_TYPE_FRAC: fractional PLL identifier + * @PLL_TYPE_DIV: divider PLL identifier + */ +enum pll_type { + PLL_TYPE_FRAC, + PLL_TYPE_DIV, +}; + +static const struct clk_master_characteristics mck_characteristics =3D { + .output =3D { .min =3D 32000000, .max =3D 266666667 }, + .divisors =3D { 1, 2, 4, 3, 5}, + .have_div3_pres =3D 1, +}; + +static const struct clk_master_layout sam9x7_master_layout =3D { + .mask =3D 0x373, + .pres_shift =3D 4, + .offset =3D 0x28, +}; + +/* Fractional PLL core output range. */ +static const struct clk_range plla_core_outputs[] =3D { + { .min =3D 375000000, .max =3D 1600000000 }, +}; + +static const struct clk_range upll_core_outputs[] =3D { + { .min =3D 600000000, .max =3D 1200000000 }, +}; + +static const struct clk_range lvdspll_core_outputs[] =3D { + { .min =3D 400000000, .max =3D 800000000 }, +}; + +static const struct clk_range audiopll_core_outputs[] =3D { + { .min =3D 400000000, .max =3D 800000000 }, +}; + +static const struct clk_range plladiv2_core_outputs[] =3D { + { .min =3D 375000000, .max =3D 1600000000 }, +}; + +/* Fractional PLL output range. */ +static const struct clk_range plla_outputs[] =3D { + { .min =3D 732421, .max =3D 800000000 }, +}; + +static const struct clk_range upll_outputs[] =3D { + { .min =3D 300000000, .max =3D 600000000 }, +}; + +static const struct clk_range lvdspll_outputs[] =3D { + { .min =3D 10000000, .max =3D 800000000 }, +}; + +static const struct clk_range audiopll_outputs[] =3D { + { .min =3D 10000000, .max =3D 800000000 }, +}; + +static const struct clk_range plladiv2_outputs[] =3D { + { .min =3D 366210, .max =3D 400000000 }, +}; + +/* PLL characteristics. */ +static const struct clk_pll_characteristics plla_characteristics =3D { + .input =3D { .min =3D 20000000, .max =3D 50000000 }, + .num_output =3D ARRAY_SIZE(plla_outputs), + .output =3D plla_outputs, + .core_output =3D plla_core_outputs, +}; + +static const struct clk_pll_characteristics upll_characteristics =3D { + .input =3D { .min =3D 20000000, .max =3D 50000000 }, + .num_output =3D ARRAY_SIZE(upll_outputs), + .output =3D upll_outputs, + .core_output =3D upll_core_outputs, + .upll =3D true, +}; + +static const struct clk_pll_characteristics lvdspll_characteristics =3D { + .input =3D { .min =3D 20000000, .max =3D 50000000 }, + .num_output =3D ARRAY_SIZE(lvdspll_outputs), + .output =3D lvdspll_outputs, + .core_output =3D lvdspll_core_outputs, +}; + +static const struct clk_pll_characteristics audiopll_characteristics =3D { + .input =3D { .min =3D 20000000, .max =3D 50000000 }, + .num_output =3D ARRAY_SIZE(audiopll_outputs), + .output =3D audiopll_outputs, + .core_output =3D audiopll_core_outputs, +}; + +static const struct clk_pll_characteristics plladiv2_characteristics =3D { + .input =3D { .min =3D 20000000, .max =3D 50000000 }, + .num_output =3D ARRAY_SIZE(plladiv2_outputs), + .output =3D plladiv2_outputs, + .core_output =3D plladiv2_core_outputs, +}; + +/* Layout for fractional PLL ID PLLA. */ +static const struct clk_pll_layout plla_frac_layout =3D { + .mul_mask =3D GENMASK(31, 24), + .frac_mask =3D GENMASK(21, 0), + .mul_shift =3D 24, + .frac_shift =3D 0, + .div2 =3D 1, +}; + +/* Layout for fractional PLLs. */ +static const struct clk_pll_layout pll_frac_layout =3D { + .mul_mask =3D GENMASK(31, 24), + .frac_mask =3D GENMASK(21, 0), + .mul_shift =3D 24, + .frac_shift =3D 0, +}; + +/* Layout for DIV PLLs. */ +static const struct clk_pll_layout pll_divpmc_layout =3D { + .div_mask =3D GENMASK(7, 0), + .endiv_mask =3D BIT(29), + .div_shift =3D 0, + .endiv_shift =3D 29, +}; + +/* Layout for DIV PLL ID PLLADIV2. */ +static const struct clk_pll_layout plladiv2_divpmc_layout =3D { + .div_mask =3D GENMASK(7, 0), + .endiv_mask =3D BIT(29), + .div_shift =3D 0, + .endiv_shift =3D 29, + .div2 =3D 1, +}; + +/* Layout for DIVIO dividers. */ +static const struct clk_pll_layout pll_divio_layout =3D { + .div_mask =3D GENMASK(19, 12), + .endiv_mask =3D BIT(30), + .div_shift =3D 12, + .endiv_shift =3D 30, +}; + +/* + * PLL clocks description + * @n: clock name + * @p: clock parent + * @l: clock layout + * @t: clock type + * @c: pll characteristics + * @f: clock flags + * @eid: export index in sam9x7->chws[] array + */ +static const struct { + const char *n; + const char *p; + const struct clk_pll_layout *l; + u8 t; + const struct clk_pll_characteristics *c; + unsigned long f; + u8 eid; +} sam9x7_plls[][3] =3D { + [PLL_ID_PLLA] =3D { + { + .n =3D "plla_fracck", + .p =3D "mainck", + .l =3D &plla_frac_layout, + .t =3D PLL_TYPE_FRAC, + /* + * This feeds plla_divpmcck which feeds CPU. It should + * not be disabled. + */ + .f =3D CLK_IS_CRITICAL | CLK_SET_RATE_GATE, + .c =3D &plla_characteristics, + }, + + { + .n =3D "plla_divpmcck", + .p =3D "plla_fracck", + .l =3D &pll_divpmc_layout, + .t =3D PLL_TYPE_DIV, + /* This feeds CPU. It should not be disabled */ + .f =3D CLK_IS_CRITICAL | CLK_SET_RATE_GATE, + .eid =3D PMC_PLLACK, + .c =3D &plla_characteristics, + }, + }, + + [PLL_ID_UPLL] =3D { + { + .n =3D "upll_fracck", + .p =3D "main_osc", + .l =3D &pll_frac_layout, + .t =3D PLL_TYPE_FRAC, + .f =3D CLK_SET_RATE_GATE, + .c =3D &upll_characteristics, + }, + + { + .n =3D "upll_divpmcck", + .p =3D "upll_fracck", + .l =3D &pll_divpmc_layout, + .t =3D PLL_TYPE_DIV, + .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, + .eid =3D PMC_UTMI, + .c =3D &upll_characteristics, + }, + }, + + [PLL_ID_AUDIO] =3D { + { + .n =3D "audiopll_fracck", + .p =3D "main_osc", + .l =3D &pll_frac_layout, + .f =3D CLK_SET_RATE_GATE, + .c =3D &audiopll_characteristics, + .t =3D PLL_TYPE_FRAC, + }, + + { + .n =3D "audiopll_divpmcck", + .p =3D "audiopll_fracck", + .l =3D &pll_divpmc_layout, + .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, + .c =3D &audiopll_characteristics, + .eid =3D PMC_AUDIOPMCPLL, + .t =3D PLL_TYPE_DIV, + }, + + { + .n =3D "audiopll_diviock", + .p =3D "audiopll_fracck", + .l =3D &pll_divio_layout, + .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, + .c =3D &audiopll_characteristics, + .eid =3D PMC_AUDIOIOPLL, + .t =3D PLL_TYPE_DIV, + }, + }, + + [PLL_ID_LVDS] =3D { + { + .n =3D "lvdspll_fracck", + .p =3D "main_osc", + .l =3D &pll_frac_layout, + .f =3D CLK_SET_RATE_GATE, + .c =3D &lvdspll_characteristics, + .t =3D PLL_TYPE_FRAC, + }, + + { + .n =3D "lvdspll_divpmcck", + .p =3D "lvdspll_fracck", + .l =3D &pll_divpmc_layout, + .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, + .c =3D &lvdspll_characteristics, + .eid =3D PMC_LVDSPLL, + .t =3D PLL_TYPE_DIV, + }, + }, + + [PLL_ID_PLLA_DIV2] =3D { + { + .n =3D "plla_div2pmcck", + .p =3D "plla_fracck", + .l =3D &plladiv2_divpmc_layout, + /* + * This may feed critical parts of the system like timers. + * It should not be disabled. + */ + .f =3D CLK_IS_CRITICAL | CLK_SET_RATE_GATE, + .c =3D &plladiv2_characteristics, + .eid =3D PMC_PLLADIV2, + .t =3D PLL_TYPE_DIV, + }, + }, +}; + +static const struct clk_programmable_layout sam9x7_programmable_layout =3D= { + .pres_mask =3D 0xff, + .pres_shift =3D 8, + .css_mask =3D 0x1f, + .have_slck_mck =3D 0, + .is_pres_direct =3D 1, +}; + +static const struct clk_pcr_layout sam9x7_pcr_layout =3D { + .offset =3D 0x88, + .cmd =3D BIT(31), + .gckcss_mask =3D GENMASK(12, 8), + .pid_mask =3D GENMASK(6, 0), +}; + +static const struct { + char *n; + char *p; + u8 id; + unsigned long flags; +} sam9x7_systemck[] =3D { + /* + * ddrck feeds DDR controller and is enabled by bootloader thus we need + * to keep it enabled in case there is no Linux consumer for it. + */ + { .n =3D "ddrck", .p =3D "masterck_div", .id =3D 2, .flags =3D CLK_IS_CR= ITICAL }, + { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, + { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, + { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, +}; + +/* + * Peripheral clocks description + * @n: clock name + * @f: clock flags + * @id: peripheral id + */ +static const struct { + char *n; + unsigned long f; + u8 id; +} sam9x7_periphck[] =3D { + { .n =3D "pioA_clk", .id =3D 2, }, + { .n =3D "pioB_clk", .id =3D 3, }, + { .n =3D "pioC_clk", .id =3D 4, }, + { .n =3D "flex0_clk", .id =3D 5, }, + { .n =3D "flex1_clk", .id =3D 6, }, + { .n =3D "flex2_clk", .id =3D 7, }, + { .n =3D "flex3_clk", .id =3D 8, }, + { .n =3D "flex6_clk", .id =3D 9, }, + { .n =3D "flex7_clk", .id =3D 10, }, + { .n =3D "flex8_clk", .id =3D 11, }, + { .n =3D "sdmmc0_clk", .id =3D 12, }, + { .n =3D "flex4_clk", .id =3D 13, }, + { .n =3D "flex5_clk", .id =3D 14, }, + { .n =3D "flex9_clk", .id =3D 15, }, + { .n =3D "flex10_clk", .id =3D 16, }, + { .n =3D "tcb0_clk", .id =3D 17, }, + { .n =3D "pwm_clk", .id =3D 18, }, + { .n =3D "adc_clk", .id =3D 19, }, + { .n =3D "dma0_clk", .id =3D 20, }, + { .n =3D "uhphs_clk", .id =3D 22, }, + { .n =3D "udphs_clk", .id =3D 23, }, + { .n =3D "macb0_clk", .id =3D 24, }, + { .n =3D "lcd_clk", .id =3D 25, }, + { .n =3D "sdmmc1_clk", .id =3D 26, }, + { .n =3D "ssc_clk", .id =3D 28, }, + { .n =3D "can0_clk", .id =3D 29, }, + { .n =3D "can1_clk", .id =3D 30, }, + { .n =3D "flex11_clk", .id =3D 32, }, + { .n =3D "flex12_clk", .id =3D 33, }, + { .n =3D "i2s_clk", .id =3D 34, }, + { .n =3D "qspi_clk", .id =3D 35, }, + { .n =3D "gfx2d_clk", .id =3D 36, }, + { .n =3D "pit64b0_clk", .id =3D 37, }, + { .n =3D "trng_clk", .id =3D 38, }, + { .n =3D "aes_clk", .id =3D 39, }, + { .n =3D "tdes_clk", .id =3D 40, }, + { .n =3D "sha_clk", .id =3D 41, }, + { .n =3D "classd_clk", .id =3D 42, }, + { .n =3D "isi_clk", .id =3D 43, }, + { .n =3D "pioD_clk", .id =3D 44, }, + { .n =3D "tcb1_clk", .id =3D 45, }, + { .n =3D "dbgu_clk", .id =3D 47, }, + /* + * mpddr_clk feeds DDR controller and is enabled by bootloader thus we + * need to keep it enabled in case there is no Linux consumer for it. + */ + { .n =3D "mpddr_clk", .id =3D 49, .f =3D CLK_IS_CRITICAL }, + { .n =3D "csi2dc_clk", .id =3D 52, }, + { .n =3D "csi4l_clk", .id =3D 53, }, + { .n =3D "dsi4l_clk", .id =3D 54, }, + { .n =3D "lvdsc_clk", .id =3D 56, }, + { .n =3D "pit64b1_clk", .id =3D 58, }, + { .n =3D "puf_clk", .id =3D 59, }, + { .n =3D "gmactsu_clk", .id =3D 67, }, +}; + +/* + * Generic clock description + * @n: clock name + * @pp: PLL parents + * @pp_mux_table: PLL parents mux table + * @r: clock output range + * @pp_chg_id: id in parent array of changeable PLL parent + * @pp_count: PLL parents count + * @id: clock id + */ +static const struct { + const char *n; + const char *pp[8]; + const char pp_mux_table[8]; + struct clk_range r; + int pp_chg_id; + u8 pp_count; + u8 id; +} sam9x7_gck[] =3D { + { + .n =3D "flex0_gclk", + .id =3D 5, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex1_gclk", + .id =3D 6, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex2_gclk", + .id =3D 7, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex3_gclk", + .id =3D 8, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex6_gclk", + .id =3D 9, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex7_gclk", + .id =3D 10, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex8_gclk", + .id =3D 11, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "sdmmc0_gclk", + .id =3D 12, + .r =3D { .max =3D 105000000 }, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex4_gclk", + .id =3D 13, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex5_gclk", + .id =3D 14, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex9_gclk", + .id =3D 15, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex10_gclk", + .id =3D 16, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "tcb0_gclk", + .id =3D 17, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "adc_gclk", + .id =3D 19, + .pp =3D { "upll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 5, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "lcd_gclk", + .id =3D 25, + .r =3D { .max =3D 75000000 }, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "sdmmc1_gclk", + .id =3D 26, + .r =3D { .max =3D 105000000 }, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "mcan0_gclk", + .id =3D 29, + .r =3D { .max =3D 80000000 }, + .pp =3D { "upll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 5, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "mcan1_gclk", + .id =3D 30, + .r =3D { .max =3D 80000000 }, + .pp =3D { "upll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 5, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex11_gclk", + .id =3D 32, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex12_gclk", + .id =3D 33, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "i2s_gclk", + .id =3D 34, + .r =3D { .max =3D 100000000 }, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "qspi_gclk", + .id =3D 35, + .r =3D { .max =3D 200000000 }, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "pit64b0_gclk", + .id =3D 37, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "classd_gclk", + .id =3D 42, + .r =3D { .max =3D 100000000 }, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "tcb1_gclk", + .id =3D 45, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "dbgu_gclk", + .id =3D 47, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "mipiphy_gclk", + .id =3D 55, + .r =3D { .max =3D 27000000 }, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "pit64b1_gclk", + .id =3D 58, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "gmac_gclk", + .id =3D 67, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, +}; + +static void __init sam9x7_pmc_setup(struct device_node *np) +{ + struct clk_range range =3D CLK_RANGE(0, 0); + const char *td_slck_name, *md_slck_name, *mainxtal_name; + struct pmc_data *sam9x7_pmc; + const char *parent_names[9]; + void **clk_mux_buffer =3D NULL; + int clk_mux_buffer_size =3D 0; + struct clk_hw *main_osc_hw; + struct regmap *regmap; + struct clk_hw *hw; + int i, j; + + i =3D of_property_match_string(np, "clock-names", "td_slck"); + if (i < 0) + return; + + td_slck_name =3D of_clk_get_parent_name(np, i); + + i =3D of_property_match_string(np, "clock-names", "md_slck"); + if (i < 0) + return; + + md_slck_name =3D of_clk_get_parent_name(np, i); + + i =3D of_property_match_string(np, "clock-names", "main_xtal"); + if (i < 0) + return; + mainxtal_name =3D of_clk_get_parent_name(np, i); + + regmap =3D device_node_to_regmap(np); + if (IS_ERR(regmap)) + return; + + sam9x7_pmc =3D pmc_data_allocate(PMC_LVDSPLL + 1, + nck(sam9x7_systemck), + nck(sam9x7_periphck), + nck(sam9x7_gck), 8); + if (!sam9x7_pmc) + return; + + clk_mux_buffer =3D kmalloc(sizeof(void *) * + (ARRAY_SIZE(sam9x7_gck)), + GFP_KERNEL); + if (!clk_mux_buffer) + goto err_free; + + hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, + 50000000); + if (IS_ERR(hw)) + goto err_free; + + hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL= , 0); + if (IS_ERR(hw)) + goto err_free; + main_osc_hw =3D hw; + + parent_names[0] =3D "main_rc_osc"; + parent_names[1] =3D "main_osc"; + hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL= , 2); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->chws[PMC_MAIN] =3D hw; + + for (i =3D 0; i < PLL_ID_MAX; i++) { + for (j =3D 0; j < 3; j++) { + struct clk_hw *parent_hw; + + if (!sam9x7_plls[i][j].n) + continue; + + switch (sam9x7_plls[i][j].t) { + case PLL_TYPE_FRAC: + if (!strcmp(sam9x7_plls[i][j].p, "mainck")) + parent_hw =3D sam9x7_pmc->chws[PMC_MAIN]; + else if (!strcmp(sam9x7_plls[i][j].p, "main_osc")) + parent_hw =3D main_osc_hw; + else + parent_hw =3D __clk_get_hw(of_clk_get_by_name + (np, sam9x7_plls[i][j].p)); + + hw =3D sam9x60_clk_register_frac_pll(regmap, + &pmc_pll_lock, + sam9x7_plls[i][j].n, + sam9x7_plls[i][j].p, + parent_hw, i, + sam9x7_plls[i][j].c, + sam9x7_plls[i][j].l, + sam9x7_plls[i][j].f); + break; + + case PLL_TYPE_DIV: + hw =3D sam9x60_clk_register_div_pll(regmap, + &pmc_pll_lock, + sam9x7_plls[i][j].n, + sam9x7_plls[i][j].p, NULL, i, + sam9x7_plls[i][j].c, + sam9x7_plls[i][j].l, + sam9x7_plls[i][j].f, 0); + break; + + default: + continue; + } + + if (IS_ERR(hw)) + goto err_free; + + if (sam9x7_plls[i][j].eid) + sam9x7_pmc->chws[sam9x7_plls[i][j].eid] =3D hw; + } + } + + parent_names[0] =3D md_slck_name; + parent_names[1] =3D "mainck"; + parent_names[2] =3D "plla_divpmcck"; + parent_names[3] =3D "upll_divpmcck"; + hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, + parent_names, NULL, &sam9x7_master_layout, + &mck_characteristics, &mck_lock); + if (IS_ERR(hw)) + goto err_free; + + hw =3D at91_clk_register_master_div(regmap, "masterck_div", + "masterck_pres", NULL, &sam9x7_master_layout, + &mck_characteristics, &mck_lock, + CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->chws[PMC_MCK] =3D hw; + + parent_names[0] =3D "plla_divpmcck"; + parent_names[1] =3D "upll_divpmcck"; + parent_names[2] =3D "main_osc"; + hw =3D sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3); + if (IS_ERR(hw)) + goto err_free; + + parent_names[0] =3D md_slck_name; + parent_names[1] =3D td_slck_name; + parent_names[2] =3D "mainck"; + parent_names[3] =3D "masterck_div"; + parent_names[4] =3D "plla_divpmcck"; + parent_names[5] =3D "upll_divpmcck"; + parent_names[6] =3D "audiopll_divpmcck"; + for (i =3D 0; i < 2; i++) { + char name[6]; + + snprintf(name, sizeof(name), "prog%d", i); + + hw =3D at91_clk_register_programmable(regmap, name, + parent_names, NULL, 7, i, + &sam9x7_programmable_layout, + NULL); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->pchws[i] =3D hw; + } + + for (i =3D 0; i < ARRAY_SIZE(sam9x7_systemck); i++) { + hw =3D at91_clk_register_system(regmap, sam9x7_systemck[i].n, + sam9x7_systemck[i].p, NULL, + sam9x7_systemck[i].id, + sam9x7_systemck[i].flags); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->shws[sam9x7_systemck[i].id] =3D hw; + } + + for (i =3D 0; i < ARRAY_SIZE(sam9x7_periphck); i++) { + hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, + &sam9x7_pcr_layout, + sam9x7_periphck[i].n, + "masterck_div", NULL, + sam9x7_periphck[i].id, + &range, INT_MIN, + sam9x7_periphck[i].f); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->phws[sam9x7_periphck[i].id] =3D hw; + } + + parent_names[0] =3D md_slck_name; + parent_names[1] =3D td_slck_name; + parent_names[2] =3D "mainck"; + parent_names[3] =3D "masterck_div"; + for (i =3D 0; i < ARRAY_SIZE(sam9x7_gck); i++) { + u8 num_parents =3D 4 + sam9x7_gck[i].pp_count; + u32 *mux_table; + + mux_table =3D kmalloc_array(num_parents, sizeof(*mux_table), + GFP_KERNEL); + if (!mux_table) + goto err_free; + + PMC_INIT_TABLE(mux_table, 4); + PMC_FILL_TABLE(&mux_table[4], sam9x7_gck[i].pp_mux_table, + sam9x7_gck[i].pp_count); + PMC_FILL_TABLE(&parent_names[4], sam9x7_gck[i].pp, + sam9x7_gck[i].pp_count); + + hw =3D at91_clk_register_generated(regmap, &pmc_pcr_lock, + &sam9x7_pcr_layout, + sam9x7_gck[i].n, + parent_names, NULL, mux_table, + num_parents, + sam9x7_gck[i].id, + &sam9x7_gck[i].r, + sam9x7_gck[i].pp_chg_id); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->ghws[sam9x7_gck[i].id] =3D hw; + clk_mux_buffer[clk_mux_buffer_size++] =3D mux_table; + } + + of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sam9x7_pmc); + kfree(clk_mux_buffer); + + return; + +err_free: + if (clk_mux_buffer) { + for (i =3D 0; i < clk_mux_buffer_size; i++) + kfree(clk_mux_buffer[i]); + kfree(clk_mux_buffer); + } + kfree(sam9x7_pmc); +} + +/* Some clks are used for a clocksource */ +CLK_OF_DECLARE(sam9x7_pmc, "microchip,sam9x7-pmc", sam9x7_pmc_setup); --=20 2.25.1 From nobody Thu Sep 19 23:14:02 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95B8882D66; Mon, 29 Jul 2024 07:08:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236939; cv=none; b=SychX56+DOO++O4R/I1lNkmRzNivS7bpSV+8BpKYZ651P0HXGAdAnj7vZg1FUUemNrPWKnxgHIyHjSMmhwhiOoonywZ4+kx2bB0CkTlJswVlF6k+n1KN0ZN6qK8ldDF1qbMMR5tPHWH4kILDOiSMBVtmONC3zdI4FrTzq6MOaX0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236939; c=relaxed/simple; bh=PkbeR8nMl2Je78nVLSik0CIhm+m2k0l233024j1jZ2A=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 29 Jul 2024 00:08:29 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 29 Jul 2024 00:08:24 -0700 From: Varshini Rajendran To: , , , , , , , , , , CC: Subject: [PATCH v6 16/27] dt-bindings: interrupt-controller: Add support for sam9x7 aic Date: Mon, 29 Jul 2024 12:38:18 +0530 Message-ID: <20240729070818.1991013-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729065603.1986074-1-varshini.rajendran@microchip.com> References: <20240729065603.1986074-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the support added for the Advanced interrupt controller(AIC) chip in the sam9x7 SoC family. Signed-off-by: Varshini Rajendran --- Changes in v6: - Changed the compatible list to only sam9x7's. Removed the Acked-by tag as there is functional change in the patch. --- .../devicetree/bindings/interrupt-controller/atmel,aic.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,a= ic.yaml b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.= yaml index d4658fe3867c..d671ed884c9e 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml @@ -23,6 +23,7 @@ properties: - atmel,sama5d3-aic - atmel,sama5d4-aic - microchip,sam9x60-aic + - microchip,sam9x7-aic =20 reg: maxItems: 1 --=20 2.25.1 From nobody Thu Sep 19 23:14:02 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBAF982899 for ; Mon, 29 Jul 2024 07:09:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236946; cv=none; b=KUFhFoA4DrzFgGvtq43NgKBTe6qXfGki/HcgcVRyloy78aeF9CRjBkUJo3qDgIYnO1HuaRDlj6de1y+WXMx60n7r3ngfYAoAtrtxBsHg+W2LrhkJt8V/Sylc1MSn1jEL5DIf3ZANcKQa3qwwVAdZ9GbxhLQdotLFAWj/4NWLpTc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236946; c=relaxed/simple; bh=FVK9wR6Wo6gRh2hzH07gqe36H17j5T1xR0c0wlKxflk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=B/1jl3QRwYR8mlVEW+9EReg60J37D2sMNmeHxyyLB8+jyonnKJjnnfaxkj1EP4Ky9tFJv+cpu+kbMs7mRdUi3iL2E4gwYWN7M6hBJif8x/xdEHso3+qDbNtZeKsTQyeiI7mtZzOQqxHQAkjZBRH7cmw8Z8rTx+6TgoLYFLK2nI4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=MKZHoo38; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="MKZHoo38" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1722236945; x=1753772945; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FVK9wR6Wo6gRh2hzH07gqe36H17j5T1xR0c0wlKxflk=; b=MKZHoo38i7QvK05Jy7YT3Ow0QzlUwux3Jz4ZOxEzzCpX48dnnRN3W7rS 3hBse0YrsJMnXWeGbZkSUKLZGhE8BDgu2X4QnQ4MfbF2PTU4a7Js0uIhZ b3qIUqZ0SlIaqDS7NRPtuKs6QniQkVkB6IDFL7FmI5ZJxa0BATznwMNgh cd+T+HWphigHkAbDUBiGYIrJCRbkjphO12Js1I2ug7rm12SzxQOvvl4ni gVipC2pgHAZoBy6vERY46fh9DcslzFJbTa0j7Ap+vjLktpKZvbnyK4QeL WE3/EI2lyEPU4kU3bCTKPIwEWfjOdL6is+lU/qbrVfzb0TXB81+3jHG7x g==; X-CSE-ConnectionGUID: /xcbkqlfTo+UjYKU1jzHkw== X-CSE-MsgGUID: xk0+ohGQRdCqf5XaAZK3lA== X-IronPort-AV: E=Sophos;i="6.09,245,1716274800"; d="scan'208";a="30454158" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 29 Jul 2024 00:09:04 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 29 Jul 2024 00:08:36 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 29 Jul 2024 00:08:33 -0700 From: Varshini Rajendran To: , , , , , CC: , Hari Prasath Subject: [PATCH v6 17/27] irqchip/atmel-aic5: Add support for sam9x7 aic Date: Mon, 29 Jul 2024 12:38:29 +0530 Message-ID: <20240729070829.1991064-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729065603.1986074-1-varshini.rajendran@microchip.com> References: <20240729065603.1986074-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hari Prasath Add support for the Advanced interrupt controller(AIC) chip in the sam9x7. Signed-off-by: Hari Prasath Signed-off-by: Varshini Rajendran --- Changes in v6: - Reverted back to the patch in version 3 considering the complexity involving in using DT match data. --- drivers/irqchip/irq-atmel-aic5.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-a= ic5.c index 145535bd7560..bab11900f3ef 100644 --- a/drivers/irqchip/irq-atmel-aic5.c +++ b/drivers/irqchip/irq-atmel-aic5.c @@ -320,6 +320,7 @@ static const struct of_device_id aic5_irq_fixups[] __in= itconst =3D { { .compatible =3D "atmel,sama5d3", .data =3D sama5d3_aic_irq_fixup }, { .compatible =3D "atmel,sama5d4", .data =3D sama5d3_aic_irq_fixup }, { .compatible =3D "microchip,sam9x60", .data =3D sam9x60_aic_irq_fixup }, + { .compatible =3D "microchip,sam9x7", .data =3D sam9x60_aic_irq_fixup }, { /* sentinel */ }, }; =20 @@ -406,3 +407,12 @@ static int __init sam9x60_aic5_of_init(struct device_n= ode *node, return aic5_of_init(node, parent, NR_SAM9X60_IRQS); } IRQCHIP_DECLARE(sam9x60_aic5, "microchip,sam9x60-aic", sam9x60_aic5_of_ini= t); + +#define NR_SAM9X7_IRQS 70 + +static int __init sam9x7_aic5_of_init(struct device_node *node, + struct device_node *parent) +{ + return aic5_of_init(node, parent, NR_SAM9X7_IRQS); +} +IRQCHIP_DECLARE(sam9x7_aic5, "microchip,sam9x7-aic", sam9x7_aic5_of_init); --=20 2.25.1 From nobody Thu Sep 19 23:14:02 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BF8412CDA8; Mon, 29 Jul 2024 07:09:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236947; cv=none; b=ZVBCqvscjHXYuG1kJOuMWBBu5QzGohc3ZimRaCFuIzkQhjFdDLIvsFVcH4NwLqoeZoF0gxOgnqcCxUGgKtzgmGjZMubARl/Y+Bg7m5xwIFmZEB4aQsYnYxwTQHJ1xptaVeedrUIp26WtATPksRSzfuIjByITE9to/nDq1L2A+98= ARC-Message-Signature: i=1; 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Mon, 29 Jul 2024 00:08:42 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 29 Jul 2024 00:08:39 -0700 From: Varshini Rajendran To: , , , , , , CC: , Sebastian Reichel Subject: [PATCH v6 18/27] power: reset: at91-poweroff: lookup for proper pmc dt node for sam9x7 Date: Mon, 29 Jul 2024 12:38:37 +0530 Message-ID: <20240729070837.1991113-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729065603.1986074-1-varshini.rajendran@microchip.com> References: <20240729065603.1986074-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use sam9x7 pmc's compatible to lookup for in the SHDWC driver. Signed-off-by: Varshini Rajendran Acked-by: Sebastian Reichel Reviewed-by: Claudiu Beznea --- Changes in v6: - Updated Reviewed-by tag --- drivers/power/reset/at91-sama5d2_shdwc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset= /at91-sama5d2_shdwc.c index 959ce0dbe91d..2121d7e74e12 100644 --- a/drivers/power/reset/at91-sama5d2_shdwc.c +++ b/drivers/power/reset/at91-sama5d2_shdwc.c @@ -326,6 +326,7 @@ static const struct of_device_id at91_pmc_ids[] =3D { { .compatible =3D "atmel,sama5d2-pmc" }, { .compatible =3D "microchip,sam9x60-pmc" }, { .compatible =3D "microchip,sama7g5-pmc" }, + { .compatible =3D "microchip,sam9x7-pmc" }, { /* Sentinel. */ } }; =20 --=20 2.25.1 From nobody Thu Sep 19 23:14:02 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64C8A12FF70; Mon, 29 Jul 2024 07:09:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236961; cv=none; b=kSlU7qyp/Og1xxogcuzEMqdmKUnBABJP+qEB40xtUPGWKN472ly8Khw3WefuQZhqEOTd4IpBmjylJecbHulPWfnSapsrFlXnZ7YmwPLxOQxrjl7JbJiEvWYeHnjWmF0ZNXZ8OYfAYc8bkFHMlVKIqUi1qMKhWMP0fQZqhVyRsKk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236961; c=relaxed/simple; bh=YTCSQwlakjV1yDkngsDhAcJOYk4NOtlZ8FWSyh+ya88=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bzPn1zhIfvvJMo8T6LgVYwPEuc4/ccUrsEnrZRzBTPRh+pAW9LcVqVoVUpGY5ojJ5yHwx9Xyh+JgujG8qyMXbYSLdcOtEUOxAZwNmNzYfA2GfXExnBjA+YH6M+xrjwr52hT4BZVL78F1e1QonAoB4M/E6MZ4dEMZmY0WHgaqrQM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=S8sTudYG; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="S8sTudYG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1722236960; x=1753772960; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YTCSQwlakjV1yDkngsDhAcJOYk4NOtlZ8FWSyh+ya88=; b=S8sTudYG7q0rppN7jEMftZSsvsYuzOOAwRNi1yH0iRTftejSb/i4ftFS swQ6dHXws3F+oW+Ocf7/Rcua6X0dnLqvSkjLuZri+YqoWv+moP5ZeNtxl L21sY9RW2KPQ9jcN2Y0IBSc9/xVXykzGEeLC8ytW3e0Qi3XkbMORh0eV1 RbOBZv7SHIHjvribVaz+QHeP5jjnaC4o7x4laA/BXAZhsm3rK8j6rk46W Oqj+LzcFqwWwLfjEcu6nt/IQ950CC/E4RsMxaQKwfZiaFPih5kJwPGq9j U7p/2rarsAJlqd6NRmTD8bE7SquYaJUjYzv76MI6mFxJ0rEolj5bNx7kB g==; X-CSE-ConnectionGUID: ysGf804zTF6Jk/9HVsTmhQ== X-CSE-MsgGUID: qwP/+f9DQ1iDHa1VzIZ0IA== X-IronPort-AV: E=Sophos;i="6.09,245,1716274800"; d="scan'208";a="29796785" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 29 Jul 2024 00:09:20 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 29 Jul 2024 00:08:49 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 29 Jul 2024 00:08:46 -0700 From: Varshini Rajendran To: , , CC: , Sebastian Reichel , Claudiu Beznea Subject: [PATCH v6 19/27] power: reset: at91-reset: add reset support for sam9x7 SoC Date: Mon, 29 Jul 2024 12:38:43 +0530 Message-ID: <20240729070843.1991162-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729065603.1986074-1-varshini.rajendran@microchip.com> References: <20240729065603.1986074-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add power reset support for SAM9X7 SoC. Signed-off-by: Varshini Rajendran Acked-by: Sebastian Reichel Reviewed-by: Claudiu Beznea --- Changes in v6: - Updated Reviewed-by tag --- drivers/power/reset/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index fece990af4a7..e3ebebc1f80d 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -26,7 +26,7 @@ config POWER_RESET_AT91_POWEROFF config POWER_RESET_AT91_RESET tristate "Atmel AT91 reset driver" depends on ARCH_AT91 - default SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 + default SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 help This driver supports restart for Atmel AT91SAM9 and SAMA5 SoCs --=20 2.25.1 From nobody Thu Sep 19 23:14:02 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D73D12FF88; Mon, 29 Jul 2024 07:09:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236962; cv=none; b=o9Rz/GaktTzi9NYQsr+PQCD1FbZGoaIQRlCa1iK+6Fn9KLkuTNrqDksgkAN6UNSQcPwTUQhMK0MsvTQhF5b10q6821yA+MsPHIZuZnn/9AwzkahXGWCcuqO0UaLbOFhAyxARlAY6id6oVvC39lX7bLTO7ZFJzyMvmi5jjGElYYU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236962; c=relaxed/simple; bh=iJBr3M8Ba+68qK1AqhukgdXo70chhq/RepYao7oCYFw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XNVNmfy8xm6LlHu62VoHdUD86MwTioSmFTDwPBVTYgJZLbIqK6FlOgQsJ3AEpacVuBofMc3HhXeGXrI50tS/41qI1OEi7bQTQrT8I4v7qEBLEkTUs7TUmzcHfCB+7bnSELY8xRaX15Nlc8SDglY0Gkw/uopPdIZhIdBsY2ewk3I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=h0T2uBxj; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="h0T2uBxj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1722236961; x=1753772961; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iJBr3M8Ba+68qK1AqhukgdXo70chhq/RepYao7oCYFw=; b=h0T2uBxjTRVuOBGnq2QA42pcHLWRjk+5rThn3yfsS65QnDXMVHQIucQM JyRWTfia4Nmou+C7yIh1nHsnzsV59sneQHCCWJVVqKdXi5WpNpf5B7luA 75qsG/vPcjEB0+hozx7phu/nVk+1DUCHZfFxGj9LPXYHeX0FYCBeiiVX3 R3krrU8bKyHNh7tJJNEDT7um8Re5S5JHm/F2N4H3X0BP31wYFzOj/HIrV b8Ono1MSIw2V7k/raP14BIMjN+GS80jt/N9jpv+D8KgE0aP+W4JRJOnCK Z/krB7UrlRTjGjDv42LfSk4yz0YSv9HDsnMkhwm3dt8H6CwA7o735qa+y g==; X-CSE-ConnectionGUID: o1mEAA2WRF+mZwSZKkI/oQ== X-CSE-MsgGUID: 2BZZWdVQTsOrDPd2py9XWA== X-IronPort-AV: E=Sophos;i="6.09,245,1716274800"; d="scan'208";a="197213997" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 29 Jul 2024 00:09:20 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 29 Jul 2024 00:08:59 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 29 Jul 2024 00:08:57 -0700 From: Varshini Rajendran To: , , CC: , Sebastian Reichel , Claudiu Beznea Subject: [PATCH v6 20/27] power: reset: at91-reset: add sdhwc support for sam9x7 SoC Date: Mon, 29 Jul 2024 12:38:49 +0530 Message-ID: <20240729070849.1991220-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729065603.1986074-1-varshini.rajendran@microchip.com> References: <20240729065603.1986074-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add shutdown controller support for SAM9X7 SoC. Signed-off-by: Varshini Rajendran Acked-by: Sebastian Reichel Reviewed-by: Claudiu Beznea --- Changes in v6: - Updated Reviewed-by tag --- drivers/power/reset/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index e3ebebc1f80d..dafb0126f683 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -34,7 +34,7 @@ config POWER_RESET_AT91_RESET config POWER_RESET_AT91_SAMA5D2_SHDWC tristate "Atmel AT91 SAMA5D2-Compatible shutdown controller driver" depends on ARCH_AT91 - default SOC_SAM9X60 || SOC_SAMA5 + default SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 help This driver supports the alternate shutdown controller for some Atmel SAMA5 SoCs. It is present for example on SAMA5D2 SoC. --=20 2.25.1 From nobody Thu Sep 19 23:14:02 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2A62131E4B; Mon, 29 Jul 2024 07:09:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236964; cv=none; b=N7g1hZbIIYFwcE31P3H9SORRcXJZWJSqo7JZE67ycUVKj2I3Ju79uXwBVAZfs26NaaRVGHMIc72TSrDC7Cf0THcnr6Z0eNAFoHSkETiRWIQ0uLgDN3dxOpyJFrwOLktUNiFwRX4eJkOS6J0mRiNkGUPUFAMX7gaBJv5Lx/EBQWs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236964; c=relaxed/simple; bh=8i5Z2KfBYTZAJwGXyHoxcKMWI4cBoFSSa/Wp6ippfD0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DiDlUwA2R7Ncn9s25Clc46KHYf7mAjeR1ONBiC+6s3Bw22+nnfuNIk8ZKqwmiu/v+uBb9zOGu7ydKXf3VY3t6ukr1oiGNdpLm5xvN4mb8YEefrPs3ohNcXk3Rf7RLQ5t+t9Sdn/ZiLqqISeZEbRlU4Ln8qqK3iPA5DWPqnFxvCo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=RcMBO6s0; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="RcMBO6s0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1722236962; x=1753772962; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8i5Z2KfBYTZAJwGXyHoxcKMWI4cBoFSSa/Wp6ippfD0=; b=RcMBO6s05pZFtT1xeLNpoEIV+hjGgHjLdjjLhJoXoWgqv5F+neXaNXZB vVckgoZ9cXgR14acCO0uvRgnPcG3pJ7oQNA1MHpQKVYDNeYQyutTAR+9K vkXMhxud5HtYRJrxAmY4x3CyFPsTyyMwiXSVLvmulXDGFWoHuNS35vwIY duflzEL1HCuraFT5WCb//EuGGlCTnwS4A3thLX+dp3Twlr1vQHftTYbu1 qJFcc3rCG4B4+DKfRcvaFumc2rMdOgZDx3JZaatdeknKVYcU2BNR7DJ3P yWYPQ1FEkiJXxnSKOl+AOotQu4pG9xxazDN6Z6Kgv/F3Mkdr8c0413I14 w==; X-CSE-ConnectionGUID: o1mEAA2WRF+mZwSZKkI/oQ== X-CSE-MsgGUID: M625Avi5Q2iy2PWsO2pPNQ== X-IronPort-AV: E=Sophos;i="6.09,245,1716274800"; d="scan'208";a="197214000" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 29 Jul 2024 00:09:20 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 29 Jul 2024 00:09:07 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 29 Jul 2024 00:09:02 -0700 From: Varshini Rajendran To: , , , , , , , , , CC: , Krzysztof Kozlowski Subject: [PATCH v6 21/27] dt-bindings: reset: atmel,at91sam9260-reset: add sam9x7 Date: Mon, 29 Jul 2024 12:39:00 +0530 Message-ID: <20240729070900.1991270-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729065603.1986074-1-varshini.rajendran@microchip.com> References: <20240729065603.1986074-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add documentation for SAM9X7 reset controller. Signed-off-by: Varshini Rajendran Reviewed-by: Krzysztof Kozlowski Acked-by: Philipp Zabel --- .../devicetree/bindings/reset/atmel,at91sam9260-reset.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-rese= t.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.ya= ml index 98465d26949e..c3b33bbc7319 100644 --- a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml +++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml @@ -26,6 +26,10 @@ properties: - items: - const: atmel,sama5d3-rstc - const: atmel,at91sam9g45-rstc + - items: + - enum: + - microchip,sam9x7-rstc + - const: microchip,sam9x60-rstc =20 reg: minItems: 1 --=20 2.25.1 From nobody Thu Sep 19 23:14:02 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39F7912C7FD; Mon, 29 Jul 2024 07:09:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236994; cv=none; b=ToTnv2eT00hFy3LIon1qdF6yCCd9PXwOAcQKac6s6N4OxjYbPQlUd8e5nZxHERISWm9/r9ESzrsVL53Ky7yxUTlKXL7TFqPD4uSCfX5plx3NRz+anxuSIK7sEJ/+tPlBQ5dW8RtulJOF6aGVRIsDkNdF4A5f14N1kc989HgvM9Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236994; c=relaxed/simple; bh=flQEluk5hLljQfPymWhZA5C4pdYlqlYSYYtSaCbnjQ8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=h1ePLnPf29MXUeIjHCkyHykGZFb6B8tOeF+V7/Lq3rZ1KFhnQkzJWEzGfH+BPRDDvJqCaVBq4A04YM0RM625emVcv53LIWvQ8gEMneXxMYDu88X1s5tjeh3s4FZLQIyor6sW+V0WDgHB0H7XUGS60xaG413idjOFT1L5zwupsH4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=FNHd2VhA; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="FNHd2VhA" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1722236993; x=1753772993; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=flQEluk5hLljQfPymWhZA5C4pdYlqlYSYYtSaCbnjQ8=; b=FNHd2VhAyJr4uZwhs6jGEawpZdkcuHSERBnC3DcoHizbPieqCu4GQfB8 80aBN2BvT7d9+lGqQT/PP+Nx65YxmO41ZnY/LlXt1jO82N3zRkcaUlE06 fKKVITViqBjXlAAV7WX4CgB1BkbD5qwB1XKmrVdXQ9+AE6SH181qfVkNQ CWQV5lV4pj2WS5G7f9fojysaeDrhl88LOC6hfBAh77hBgLJSDgTsuCQ7M PYyY8AQcqjBn8phLMiU1AlWqBWi3kHp6apGSBZ95WF3VjUGToIeA3g2vT g10OHVA7K9XYBqW3FoTRYAXiBKjhlze3GHcOgB1Cs7pp2WXoZakiag7Tl w==; X-CSE-ConnectionGUID: YmCZXuD3Tai4yHyg8vJh5A== X-CSE-MsgGUID: htNuK+SpS2CqwLB2J77/3w== X-IronPort-AV: E=Sophos;i="6.09,245,1716274800"; d="scan'208";a="30454179" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 29 Jul 2024 00:09:52 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 29 Jul 2024 00:09:16 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 29 Jul 2024 00:09:11 -0700 From: Varshini Rajendran To: , , , , , , , , , , CC: , Krzysztof Kozlowski , Sebastian Reichel Subject: [PATCH v6 22/27] dt-bindings: power: reset: atmel,sama5d2-shdwc: add sam9x7 Date: Mon, 29 Jul 2024 12:39:07 +0530 Message-ID: <20240729070907.1991321-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729065603.1986074-1-varshini.rajendran@microchip.com> References: <20240729065603.1986074-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add shutdown controller DT bindings. Signed-off-by: Varshini Rajendran Reviewed-by: Krzysztof Kozlowski Acked-by: Sebastian Reichel --- .../devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-sh= dwc.yaml b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdw= c.yaml index 8c58e12cdb60..0735ceb7c103 100644 --- a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml +++ b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml @@ -22,6 +22,9 @@ properties: - enum: - atmel,sama5d2-shdwc - microchip,sam9x60-shdwc + - items: + - const: microchip,sam9x7-shdwc + - const: microchip,sam9x60-shdwc =20 reg: maxItems: 1 --=20 2.25.1 From nobody Thu Sep 19 23:14:02 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9A8B12D773 for ; Mon, 29 Jul 2024 07:09:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236996; cv=none; b=lRT+0N8u5X7Q9mwL9Ze9D3Hz2Ay+LeiTjyetb1dWmmI1CH0HkYznlC6Xe+oEP8LS/JbWoQMPViEMFQTPZSgtuJcLJEenpzjzSOq+03riSE6zTn9FBcBgFM3DUNoDKTlJ6qcJcN/SK6hTViwvJih0mvcu7kYT3cWZYDVcDrf4ps8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722236996; c=relaxed/simple; bh=Zp4EXrWaqvt9w4fN5txweOfGJMN/jM2LGcFRrFU+QQY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fCE4g/nLzZz/3EmObUimtz/vT4X5LIlG8jtrZ78Um5ams4/gxoE0ZTpjEYCwftJTEFJO7GPBkISLCydOLynZTrA4xxYW2zkAOw7+naJJKmJgvREaTmdTPL9ODAaWkZh9pfff9HSmsSYSJWA8Tz2Tnb2YNtDv+ZIkqlmfxTauCeg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=sFXhpdAB; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="sFXhpdAB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1722236995; x=1753772995; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Zp4EXrWaqvt9w4fN5txweOfGJMN/jM2LGcFRrFU+QQY=; b=sFXhpdAB9mzv9FctscZnnx7bm2PgIrKX+CnJEhkUjAVgQB5hmpqneJ8E SIIzTn56sOraxz4SAiKUR5dPU42OJex6VblYUTXX0aWspKctRY5RObyfn gMw7u3pJIDQ1sjDTuV/uMbiK41ghekc1n+9JkTfLB898TVnzUx57yqo6w Hp6tVvGTwA2cH1XtZby0qAU6x06CNhi1Ja+SE2Y+K1SGakhnOc8MyYIxq loOMK9ZgxVMfegGHua9m1gBMJGjyJ1J1oZZpf6s7aJMdHvQuE1yv3m732 5e+YcA0206YPNcw4SLmHTldiytpwf7q4V54bm6dNualVzdMlD7dpzsyn/ Q==; X-CSE-ConnectionGUID: YmCZXuD3Tai4yHyg8vJh5A== X-CSE-MsgGUID: iLQ2sjlpSFyFcszSVTt3Ag== X-IronPort-AV: E=Sophos;i="6.09,245,1716274800"; d="scan'208";a="30454182" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 29 Jul 2024 00:09:53 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 29 Jul 2024 00:09:22 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 29 Jul 2024 00:09:20 -0700 From: Varshini Rajendran To: , , , , , CC: Subject: [PATCH v6 23/27] ARM: at91: Kconfig: add config flag for SAM9X7 SoC Date: Mon, 29 Jul 2024 12:39:16 +0530 Message-ID: <20240729070916.1991370-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729065603.1986074-1-varshini.rajendran@microchip.com> References: <20240729065603.1986074-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add config flag for sam9x7 SoC. Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- arch/arm/mach-at91/Kconfig | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index a8c022b4c053..344f5305f69a 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -141,11 +141,27 @@ config SOC_SAM9X60 help Select this if you are using Microchip's SAM9X60 SoC =20 +config SOC_SAM9X7 + bool "SAM9X7" + depends on ARCH_MULTI_V5 + select ATMEL_AIC5_IRQ + select ATMEL_PM if PM + select CPU_ARM926T + select HAVE_AT91_USB_CLK + select HAVE_AT91_GENERATED_CLK + select HAVE_AT91_SAM9X60_PLL + select MEMORY + select PINCTRL_AT91 + select SOC_SAM_V4_V5 + select SRAM if PM + help + Select this if you are using Microchip's SAM9X7 SoC + comment "Clocksource driver selection" =20 config ATMEL_CLOCKSOURCE_PIT bool "Periodic Interval Timer (PIT) support" - depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 + depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 default SOC_AT91SAM9 || SOC_SAMA5 select ATMEL_PIT help @@ -155,7 +171,7 @@ config ATMEL_CLOCKSOURCE_PIT =20 config ATMEL_CLOCKSOURCE_TCB bool "Timer Counter Blocks (TCB) support" - default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 + default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SO= C_SAMA5 select ATMEL_TCB_CLKSRC help Select this to get a high precision clocksource based on a @@ -166,7 +182,7 @@ config ATMEL_CLOCKSOURCE_TCB =20 config MICROCHIP_CLOCKSOURCE_PIT64B bool "64-bit Periodic Interval Timer (PIT64B) support" - default SOC_SAM9X60 || SOC_SAMA7 + default SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA7 select MICROCHIP_PIT64B help Select this to get a high resolution clockevent (SAM9X60) or --=20 2.25.1 From nobody Thu Sep 19 23:14:02 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F00212E1C5 for ; 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charset="utf-8" Enable config flags for SAM9X7 SoC for the sam9x7 SoC family. Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- Changes in v6: - Updated Reviewed-by tag --- arch/arm/configs/at91_dt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_= defconfig index 6eabe2313c9a..2022a7fca0f9 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_AT91=3Dy CONFIG_SOC_AT91RM9200=3Dy CONFIG_SOC_AT91SAM9=3Dy CONFIG_SOC_SAM9X60=3Dy +CONFIG_SOC_SAM9X7=3Dy # CONFIG_ATMEL_CLOCKSOURCE_PIT is not set CONFIG_AEABI=3Dy CONFIG_UACCESS_WITH_MEMCPY=3Dy --=20 2.25.1 From nobody Thu Sep 19 23:14:02 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33A1384DF1; Mon, 29 Jul 2024 07:10:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722237024; cv=none; b=iip9c5FryT4EmeTstmoIZ0a0DJHniXbXPVzakoGju9MyCz6ktFmx6d/Q/ZN8TIFW4NsIKPnib2yHxMa/aQyjiuKnK64e1qtv9yW1uQmSfPKIs0jdIgB+AojxWR2SLy4+a2WxQZeICL72y4UDEsuYvNPvDIbdecC74mUXdnrmBQc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722237024; c=relaxed/simple; bh=KrTUlh7J8ks2uJKVy69LG+TCF+qwurP5zH8hEsovOBE=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LJx6H0oV7dCru/z+apnA4Ve9XClk9ONPmgwwjKnK/6zh/f60gJ+IKtf6oLRJoNbS3keZR02LDHz1MT3Qz7vA6IZ7pFCVObXtPglVZi0tTIp0Q6Dc6Qshr4Tna3y1E/fapUNcuY4mq72B80+LB50PDK9Yp8VHSnPRMyYMy3UUqE8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=1oa/V6Jf; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="1oa/V6Jf" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1722237021; x=1753773021; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=KrTUlh7J8ks2uJKVy69LG+TCF+qwurP5zH8hEsovOBE=; b=1oa/V6JfmBGLxPgFD0dBKjJDHmwQ0Or/R5BqSNJpytDr8qBZmDT+aSkW RLf16e8r0ZgTb4sXAOxEliv/z3oo2Tr86ihu2Y8TcPt27/moMEBto8dBl p7dNem2tgv4/V1QQ5lg/TSVKY79upFGWopuJaWcRghaQq4EiyJNKQjcFA EB4ZwF3F3vy7ghlulHiwSnG6zhF2prZ/q8owEaM/RqOjakAukNNxMumN6 H2AYtjhEbrY/t4vdn/xI+JiwjnHPEgGuCNJDB/WcyNa9LYUPA5veIMSO0 Q82z9Uiwdic8arMwTt49LTNqBZ37YnthdpJRkZ47Lo6ukbm/Arm9c0S1P A==; X-CSE-ConnectionGUID: nya7fybtRtOcSI+sfk742g== X-CSE-MsgGUID: wjjUuPO+Su+BsY46v5wblw== X-IronPort-AV: E=Sophos;i="6.09,245,1716274800"; d="scan'208";a="32597000" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 29 Jul 2024 00:10:21 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 29 Jul 2024 00:09:40 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 29 Jul 2024 00:09:37 -0700 From: Varshini Rajendran To: , , , , , , Subject: [PATCH v6 25/27] ARM: dts: at91: sam9x7: add device tree for SoC Date: Mon, 29 Jul 2024 12:39:34 +0530 Message-ID: <20240729070934.1991467-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729065603.1986074-1-varshini.rajendran@microchip.com> References: <20240729065603.1986074-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree file for SAM9X7 SoC family. Co-developed-by: Nicolas Ferre Signed-off-by: Nicolas Ferre Signed-off-by: Varshini Rajendran --- Changes in v6: - Moved vendor specific property to the end of the nodes. - Added assigned-clock-rates property in gmac node. - Modify aic compatible according to the previous support patches. --- arch/arm/boot/dts/microchip/sam9x7.dtsi | 1226 +++++++++++++++++++++++ 1 file changed, 1226 insertions(+) create mode 100644 arch/arm/boot/dts/microchip/sam9x7.dtsi diff --git a/arch/arm/boot/dts/microchip/sam9x7.dtsi b/arch/arm/boot/dts/mi= crochip/sam9x7.dtsi new file mode 100644 index 000000000000..bedcb9173b79 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sam9x7.dtsi @@ -0,0 +1,1226 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sam9x7.dtsi - Device Tree Include file for Microchip SAM9X7 SoC family + * + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + model =3D "Microchip SAM9X7 SoC"; + compatible =3D "microchip,sam9x7"; + #address-cells =3D <1>; + #size-cells =3D <1>; + interrupt-parent =3D <&aic>; + + aliases { + serial0 =3D &dbgu; + gpio0 =3D &pioA; + gpio1 =3D &pioB; + gpio2 =3D &pioC; + gpio3 =3D &pioD; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + compatible =3D "arm,arm926ej-s"; + reg =3D <0>; + device_type =3D "cpu"; + }; + }; + + clocks { + slow_xtal: clock-slowxtal { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + main_xtal: clock-mainxtal { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + }; + + sram: sram@300000 { + compatible =3D "mmio-sram"; + reg =3D <0x300000 0x10000>; + ranges =3D <0 0x300000 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + + ahb { + compatible =3D "simple-bus"; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + + sdmmc0: mmc@80000000 { + compatible =3D "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci"; + reg =3D <0x80000000 0x300>; + interrupts =3D <12 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>; + clock-names =3D "hclock", "multclk"; + assigned-clocks =3D <&pmc PMC_TYPE_GCK 12>; + assigned-clock-rates =3D <100000000>; + status =3D "disabled"; + }; + + sdmmc1: mmc@90000000 { + compatible =3D "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci"; + reg =3D <0x90000000 0x300>; + interrupts =3D <26 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>; + clock-names =3D "hclock", "multclk"; + assigned-clocks =3D <&pmc PMC_TYPE_GCK 26>; + assigned-clock-rates =3D <100000000>; + status =3D "disabled"; + }; + }; + + apb { + compatible =3D "simple-bus"; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + + flx4: flexcom@f0000000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf0000000 0x200>; + ranges =3D <0x0 0xf0000000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; + status =3D "disabled"; + + uart4: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + spi4: spi@400 { + compatible =3D "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c4: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx5: flexcom@f0004000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf0004000 0x200>; + ranges =3D <0x0 0xf0004000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 14>; + status =3D "disabled"; + + uart5: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + spi5: spi@400 { + compatible =3D "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c5: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 14>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + dma0: dma-controller@f0008000 { + compatible =3D "microchip,sam9x7-dma", "atmel,sama5d4-dma"; + reg =3D <0xf0008000 0x1000>; + interrupts =3D <20 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 20>; + clock-names =3D "dma_clk"; + status =3D "disabled"; + }; + + ssc: ssc@f0010000 { + compatible =3D "microchip,sam9x7-ssc", "atmel,at91sam9g45-ssc"; + reg =3D <0xf0010000 0x4000>; + interrupts =3D <28 IRQ_TYPE_LEVEL_HIGH 5>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 28>; + clock-names =3D "pclk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(38))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(39))>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + i2s: i2s@f001c000 { + compatible =3D "microchip,sam9x7-i2smcc", "microchip,sam9x60-i2smcc"; + reg =3D <0xf001c000 0x100>; + interrupts =3D <34 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>; + clock-names =3D "pclk", "gclk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(36))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(37))>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + flx11: flexcom@f0020000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf0020000 0x200>; + ranges =3D <0x0 0xf0020000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 32>; + status =3D "disabled"; + + uart11: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <32 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 32>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(22))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(23))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + i2c11: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <32 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 32>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(22))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(23))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx12: flexcom@f0024000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf0024000 0x200>; + ranges =3D <0x0 0xf0024000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 33>; + status =3D "disabled"; + + uart12: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <33 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 33>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(24))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(25))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + i2c12: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <33 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 33>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(24))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(25))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + pit64b0: timer@f0028000 { + compatible =3D "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"; + reg =3D <0xf0028000 0x100>; + interrupts =3D <37 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; + clock-names =3D "pclk", "gclk"; + }; + + sha: crypto@f002c000 { + compatible =3D "microchip,sam9x7-sha", "atmel,at91sam9g46-sha"; + reg =3D <0xf002c000 0x100>; + interrupts =3D <41 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 41>; + clock-names =3D "sha_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(34))>; + dma-names =3D "tx"; + }; + + trng: rng@f0030000 { + compatible =3D "microchip,sam9x7-trng", "microchip,sam9x60-trng"; + reg =3D <0xf0030000 0x100>; + interrupts =3D <38 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 38>; + status =3D "disabled"; + }; + + aes: crypto@f0034000 { + compatible =3D "microchip,sam9x7-aes", "atmel,at91sam9g46-aes"; + reg =3D <0xf0034000 0x100>; + interrupts =3D <39 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 39>; + clock-names =3D "aes_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(32))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(33))>; + dma-names =3D "tx", "rx"; + }; + + tdes: crypto@f0038000 { + compatible =3D "microchip,sam9x7-tdes", "atmel,at91sam9g46-tdes"; + reg =3D <0xf0038000 0x100>; + interrupts =3D <40 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 40>; + clock-names =3D "tdes_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(31))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(30))>; + dma-names =3D "tx", "rx"; + }; + + classd: sound@f003c000 { + compatible =3D "microchip,sam9x7-classd", "atmel,sama5d2-classd"; + reg =3D <0xf003c000 0x100>; + interrupts =3D <42 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>; + clock-names =3D "pclk", "gclk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(35))>; + dma-names =3D "tx"; + status =3D "disabled"; + }; + + pit64b1: timer@f0040000 { + compatible =3D "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"; + reg =3D <0xf0040000 0x100>; + interrupts =3D <58 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; + clock-names =3D "pclk", "gclk"; + }; + + can0: can@f8000000 { + compatible =3D "bosch,m_can"; + reg =3D <0xf8000000 0x100>, <0x300000 0x7800>; + reg-names =3D "m_can", "message_ram"; + interrupts =3D <29 IRQ_TYPE_LEVEL_HIGH 0>, + <68 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names =3D "int0", "int1"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_GCK 29>; + clock-names =3D "hclk", "cclk"; + assigned-clocks =3D <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 2= 9>; + assigned-clock-rates =3D <480000000>, <40000000>; + assigned-clock-parents =3D <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYP= E_CORE PMC_UTMI>; + bosch,mram-cfg =3D <0x3400 0 0 64 0 0 32 32>; + status =3D "disabled"; + }; + + can1: can@f8004000 { + compatible =3D "bosch,m_can"; + reg =3D <0xf8004000 0x100>, <0x300000 0xbc00>; + reg-names =3D "m_can", "message_ram"; + interrupts =3D <30 IRQ_TYPE_LEVEL_HIGH 0>, + <69 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names =3D "int0", "int1"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 30>, <&pmc PMC_TYPE_GCK 30>; + clock-names =3D "hclk", "cclk"; + assigned-clocks =3D <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 3= 0>; + assigned-clock-rates =3D <480000000>, <40000000>; + assigned-clock-parents =3D <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYP= E_CORE PMC_UTMI>; + bosch,mram-cfg =3D <0x7800 0 0 64 0 0 32 32>; + status =3D "disabled"; + }; + + tcb: timer@f8008000 { + compatible =3D "microchip,sam9x7-tcb","atmel,sama5d2-tcb", "simple-mfd"= , "syscon"; + reg =3D <0xf8008000 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D <17 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_GCK 17>, <&clk= 32k 0>; + clock-names =3D "t0_clk", "gclk", "slow_clk"; + status =3D "disabled"; + }; + + flx6: flexcom@f8010000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8010000 0x200>; + ranges =3D <0x0 0xf8010000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 9>; + status =3D "disabled"; + + uart6: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <9 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 9>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + i2c6: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <9 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 9>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx7: flexcom@f8014000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8014000 0x200>; + ranges =3D <0x0 0xf8014000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 10>; + status =3D "disabled"; + + uart7: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <10 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 10>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + i2c7: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <10 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 10>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx8: flexcom@f8018000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8018000 0x200>; + ranges =3D <0x0 0xf8018000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 11>; + status =3D "disabled"; + + uart8: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <11 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 11>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + i2c8: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <11 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 11>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx0: flexcom@f801c000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf801c000 0x200>; + ranges =3D <0x0 0xf801c000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; + status =3D "disabled"; + + uart0: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + spi0: spi@400 { + compatible =3D "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c0: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx1: flexcom@f8020000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8020000 0x200>; + ranges =3D <0x0 0xf8020000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 6>; + status =3D "disabled"; + + uart1: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + spi1: spi@400 { + compatible =3D "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c1: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 6>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx2: flexcom@f8024000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8024000 0x200>; + ranges =3D <0x0 0xf8024000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 7>; + status =3D "disabled"; + + uart2: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + spi2: spi@400 { + compatible =3D "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c2: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx3: flexcom@f8028000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8028000 0x200>; + ranges =3D <0x0 0xf8028000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 8>; + status =3D "disabled"; + + uart3: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + spi3: spi@400 { + compatible =3D "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c3: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 8>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + gmac: ethernet@f802c000 { + compatible =3D "microchip,sam9x7-gem", "microchip,sama7g5-gem"; + reg =3D <0xf802c000 0x1000>; + interrupts =3D <24 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 0 */ + <60 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 1 */ + <61 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 2 */ + <62 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 3 */ + <63 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 4 */ + <64 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 5 */ + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>= , <&pmc PMC_TYPE_GCK 24>, <&pmc PMC_TYPE_GCK 67>; + clock-names =3D "hclk", "pclk", "tx_clk", "tsu_clk"; + assigned-clocks =3D <&pmc PMC_TYPE_GCK 67>; + assigned-clock-rates =3D <266666666>; + status =3D "disabled"; + }; + + pwm0: pwm@f8034000 { + compatible =3D "microchip,sam9x7-pwm", "microchip,sam9x60-pwm"; + reg =3D <0xf8034000 0x300>; + interrupts =3D <18 IRQ_TYPE_LEVEL_HIGH 4>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 18>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + flx9: flexcom@f8040000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8040000 0x200>; + ranges =3D <0x0 0xf8040000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 15>; + status =3D "disabled"; + + uart9: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <15 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 15>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + i2c9: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <15 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 15>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx10: flexcom@f8044000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8044000 0x200>; + ranges =3D <0x0 0xf8044000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 16>; + status =3D "disabled"; + + uart10: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 16>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(21))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + i2c10: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 16>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(21))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + sfr: sfr@f8050000 { + compatible =3D "microchip,sam9x7-sfr", "microchip,sam9x60-sfr", "syscon= "; + reg =3D <0xf8050000 0x100>; + }; + + matrix: matrix@ffffde00 { + compatible =3D "microchip,sam9x7-matrix", "atmel,at91sam9x5-matrix", "s= yscon"; + reg =3D <0xffffde00 0x200>; + }; + + pmecc: ecc-engine@ffffe000 { + compatible =3D "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc"; + reg =3D <0xffffe000 0x300>, <0xffffe600 0x100>; + }; + + mpddrc: mpddrc@ffffe800 { + compatible =3D "microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc"; + reg =3D <0xffffe800 0x200>; + clocks =3D <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>; + clock-names =3D "ddrck", "mpddr"; + }; + + smc: smc@ffffea00 { + compatible =3D "microchip,sam9x7-smc", "atmel,at91sam9260-smc", "syscon= "; + reg =3D <0xffffea00 0x100>; + }; + + aic: interrupt-controller@fffff100 { + compatible =3D "microchip,sam9x7-aic"; + reg =3D <0xfffff100 0x100>; + #interrupt-cells =3D <3>; + interrupt-controller; + atmel,external-irqs =3D <31>; + }; + + dbgu: serial@fffff200 { + compatible =3D "microchip,sam9x7-dbgu", "atmel,at91sam9260-dbgu", "micr= ochip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0xfffff200 0x200>; + interrupts =3D <47 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 47>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(28))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(29))>; + dma-names =3D "tx", "rx"; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + pinctrl: pinctrl@fffff400 { + compatible =3D "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl",= "simple-mfd"; + ranges =3D <0xfffff400 0xfffff400 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + /* mux-mask corresponding to sam9x7 SoC in TFBGA228L package */ + atmel,mux-mask =3D < + /* A B C D */ + 0xffffffff 0xffffefc0 0xc0ffd000 0x00000000 /* pioA */ + 0x07ffffff 0x0805fe7f 0x01ff9f81 0x06078000 /* pioB */ + 0xffffffff 0x07dfffff 0xfa3fffff 0x00000000 /* pioC */ + 0x00003fff 0x00003fe0 0x0000003f 0x00000000 /* pioD */ + >; + + pioA: gpio@fffff400 { + compatible =3D "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atm= el,at91rm9200-gpio"; + reg =3D <0xfffff400 0x200>; + interrupts =3D <2 IRQ_TYPE_LEVEL_HIGH 1>; + #interrupt-cells =3D <2>; + interrupt-controller; + #gpio-cells =3D <2>; + gpio-controller; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 2>; + }; + + pioB: gpio@fffff600 { + compatible =3D "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atm= el,at91rm9200-gpio"; + reg =3D <0xfffff600 0x200>; + interrupts =3D <3 IRQ_TYPE_LEVEL_HIGH 1>; + #interrupt-cells =3D <2>; + interrupt-controller; + #gpio-cells =3D <2>; + gpio-controller; + #gpio-lines =3D <26>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 3>; + }; + + pioC: gpio@fffff800 { + compatible =3D "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atm= el,at91rm9200-gpio"; + reg =3D <0xfffff800 0x200>; + interrupts =3D <4 IRQ_TYPE_LEVEL_HIGH 1>; + #interrupt-cells =3D <2>; + interrupt-controller; + #gpio-cells =3D <2>; + gpio-controller; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 4>; + }; + + pioD: gpio@fffffa00 { + compatible =3D "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atm= el,at91rm9200-gpio"; + reg =3D <0xfffffa00 0x200>; + interrupts =3D <44 IRQ_TYPE_LEVEL_HIGH 1>; + #interrupt-cells =3D <2>; + interrupt-controller; + #gpio-cells =3D <2>; + gpio-controller; + #gpio-lines =3D <22>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 44>; + }; + }; + + pmc: clock-controller@fffffc00 { + compatible =3D "microchip,sam9x7-pmc", "syscon"; + reg =3D <0xfffffc00 0x200>; + interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH 7>; + #clock-cells =3D <2>; + clocks =3D <&clk32k 1>, <&clk32k 0>, <&main_xtal>; + clock-names =3D "td_slck", "md_slck", "main_xtal"; + }; + + reset_controller: reset-controller@fffffe00 { + compatible =3D "microchip,sam9x7-rstc", "microchip,sam9x60-rstc"; + reg =3D <0xfffffe00 0x10>; + clocks =3D <&clk32k 0>; + }; + + poweroff: poweroff@fffffe10 { + compatible =3D "microchip,sam9x7-shdwc", "microchip,sam9x60-shdwc"; + reg =3D <0xfffffe10 0x10>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk32k 0>; + atmel,wakeup-rtc-timer; + atmel,wakeup-rtt-timer; + status =3D "disabled"; + }; + + rtt: rtc@fffffe20 { + compatible =3D "microchip,sam9x7-rtt", "atmel,at91sam9260-rtt"; + reg =3D <0xfffffe20 0x20>; + interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&clk32k 0>; + }; + + clk32k: clock-controller@fffffe50 { + compatible =3D "microchip,sam9x7-sckc", "microchip,sam9x60-sckc"; + reg =3D <0xfffffe50 0x4>; + clocks =3D <&slow_xtal>; + #clock-cells =3D <1>; + }; + + gpbr: syscon@fffffe60 { + compatible =3D "microchip,sam9x7-gpbr", "atmel,at91sam9260-gpbr", "sysc= on"; + reg =3D <0xfffffe60 0x10>; + }; + + rtc: rtc@fffffea8 { + compatible =3D "microchip,sam9x7-rtc", "microchip,sam9x60-rtc"; + reg =3D <0xfffffea8 0x100>; + interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&clk32k 0>; + }; + + watchdog: watchdog@ffffff80 { + compatible =3D "microchip,sam9x7-wdt", "microchip,sam9x60-wdt"; + reg =3D <0xffffff80 0x24>; + interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH 7>; + status =3D "disabled"; + }; + }; +}; --=20 2.25.1 From nobody Thu Sep 19 23:14:02 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6BDB6E619; Mon, 29 Jul 2024 07:10:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; 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charset="utf-8" Add documentation for SAM9X75 Curiosity board. Signed-off-by: Varshini Rajendran Acked-by: Rob Herring Reviewed-by: Claudiu Beznea --- Changes in v6: - Updated Reviewed-by tag --- Documentation/devicetree/bindings/arm/atmel-at91.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Docume= ntation/devicetree/bindings/arm/atmel-at91.yaml index 82f37328cc69..7160ec80ac1b 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -106,6 +106,12 @@ properties: - const: microchip,sam9x60 - const: atmel,at91sam9 =20 + - description: Microchip SAM9X7 Evaluation Boards + items: + - const: microchip,sam9x75-curiosity + - const: microchip,sam9x7 + - const: atmel,at91sam9 + - description: Nattis v2 board with Natte v2 power board items: - const: axentia,nattis-2 --=20 2.25.1 From nobody Thu Sep 19 23:14:02 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B282512E1F9; Mon, 29 Jul 2024 07:10:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722237027; cv=none; b=p7jYBdby9JLkXP/VfLTNxn9tG9Ek8LANaDOp1L3h8X0tjpzUyLiSQEdSrXWvzU45j2axvSMeBKSG5MChr0G1B+BQxBWvt/0G9UA9CLrrZ6g45nL7qh2cH2mhlpm3hvexr/oYLF3MWBz/tNsmMhffW6W/IcE4iKZAzC+awXie6xM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722237027; c=relaxed/simple; bh=Fy03B8yiu2Way3mFHHeNbbjCDOG9ABmV+Hm8/1S0ELI=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Nk4/pjpGbylobb2+s/3M9pR8bfuAjtkW29JHH+OBmYyii1lw66rfx2nLDeM/K915panoz6vupUoiEuNrce97JSTVqAe6/G9b29PKKReT3ayJtTXd74fZiHZ4b9PJNCmOQDI4jiOJfZvmNpmm1fq3SivZjFeiMDKDAqP57k/cRzw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=yOKe+ke/; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="yOKe+ke/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1722237025; x=1753773025; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=Fy03B8yiu2Way3mFHHeNbbjCDOG9ABmV+Hm8/1S0ELI=; b=yOKe+ke/RYXXy+lgSDa8WgyOOh2YqTu5N7hngjtnlEZNxdvvjWZtcCat LHfKo2eB9jC5LFnUVO6mH9/F/tn7+3iYk6hcU3pNwzN3itQ8I9sZdnwah PvwaQ2NU6m6JtPIqu2N3ceRpwt/RVpUiOz3DB1yjI5wPSWjUe8WrJhwwY atXPpYFTfBFG8+qGMKyj7evpHFRqrkXi2BJXunapcoIKQ5d5/r16vGAzV iHa7ZNQwX3IpX14TyKIA/LQo0PQsTD1LN9V0WKYRWuC5EJTha7R5ijWed J8EpbzhZG+SHdkoWrQoveD7X0Ss2IlZq2G8hjJLjnEX79uB8tileGOm18 A==; X-CSE-ConnectionGUID: nya7fybtRtOcSI+sfk742g== X-CSE-MsgGUID: y2pZL6FfS1eMFBrJtx4PDQ== X-IronPort-AV: E=Sophos;i="6.09,245,1716274800"; d="scan'208";a="32597015" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 29 Jul 2024 00:10:23 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 29 Jul 2024 00:10:06 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 29 Jul 2024 00:10:02 -0700 From: Varshini Rajendran To: , , , , , , , , , , Subject: [PATCH v6 27/27] ARM: dts: microchip: sam9x75_curiosity: add sam9x75 curiosity board Date: Mon, 29 Jul 2024 12:40:00 +0530 Message-ID: <20240729071000.1991575-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729065603.1986074-1-varshini.rajendran@microchip.com> References: <20240729065603.1986074-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree file for sam9x75 curiosity board. Signed-off-by: Varshini Rajendran --- Changes in v6: - Corrected the regulator voltages according to the schematics --- arch/arm/boot/dts/microchip/Makefile | 3 + .../dts/microchip/at91-sam9x75_curiosity.dts | 312 ++++++++++++++++++ 2 files changed, 315 insertions(+) create mode 100644 arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts diff --git a/arch/arm/boot/dts/microchip/Makefile b/arch/arm/boot/dts/micro= chip/Makefile index 0c45c8d17468..470fe46433a9 100644 --- a/arch/arm/boot/dts/microchip/Makefile +++ b/arch/arm/boot/dts/microchip/Makefile @@ -2,6 +2,7 @@ # Enables support for device-tree overlays DTC_FLAGS_at91-sam9x60_curiosity :=3D -@ DTC_FLAGS_at91-sam9x60ek :=3D -@ +DTC_FLAGS_at91-sam9x75_curiosity :=3D -@ DTC_FLAGS_at91-sama5d27_som1_ek :=3D -@ DTC_FLAGS_at91-sama5d27_wlsom1_ek :=3D -@ DTC_FLAGS_at91-sama5d29_curiosity :=3D -@ @@ -60,6 +61,8 @@ dtb-$(CONFIG_SOC_AT91SAM9) +=3D \ dtb-$(CONFIG_SOC_SAM9X60) +=3D \ at91-sam9x60_curiosity.dtb \ at91-sam9x60ek.dtb +dtb-$(CONFIG_SOC_SAM9X7) +=3D \ + at91-sam9x75_curiosity.dtb dtb-$(CONFIG_SOC_SAM_V7) +=3D \ at91-kizbox2-2.dtb \ at91-kizbox3-hs.dtb \ diff --git a/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts b/arch/= arm/boot/dts/microchip/at91-sam9x75_curiosity.dts new file mode 100644 index 000000000000..4cab66b317ba --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts @@ -0,0 +1,312 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sam9x75_curiosity.dts - Device Tree file for Microchip SAM9X75 Cur= iosity board + * + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + */ +/dts-v1/; +#include "sam9x7.dtsi" +#include + +/ { + model =3D "Microchip SAM9X75 Curiosity"; + compatible =3D "microchip,sam9x75-curiosity", "microchip,sam9x7", "atmel,= at91sam9"; + + aliases { + i2c0 =3D &i2c6; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_key_gpio_default>; + + button-user { + label =3D "USER"; + gpios =3D <&pioC 9 GPIO_ACTIVE_LOW>; + linux,code =3D ; + wakeup-source; + }; + }; + + leds { + compatible =3D "gpio-leds"; + + led_red: led-red { + label =3D "red"; + gpios =3D <&pioC 14 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&pinctrl_red_led_gpio_default>; + }; + + led_green: led-green { + label =3D "green"; + gpios =3D <&pioC 21 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&pinctrl_green_led_gpio_default>; + }; + + led_blue: led-blue { + label =3D "blue"; + gpios =3D <&pioC 20 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&pinctrl_blue_led_gpio_default>; + linux,default-trigger =3D "heartbeat"; + }; + }; + + memory@20000000 { + reg =3D <0x20000000 0x10000000>; + device_type =3D "memory"; + }; +}; + +&classd { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_classd_default>; + atmel,pwm-type =3D "diff"; + atmel,non-overlap-time =3D <10>; + status =3D "okay"; +}; + +&dbgu { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_dbgu_default>; + status =3D "okay"; +}; + +&dma0 { + status =3D "okay"; +}; + +&flx6 { + atmel,flexcom-mode =3D ; + status =3D "okay"; +}; + +&i2c6 { + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flx6_default>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns =3D <35>; + status =3D "okay"; + + pmic@5b { + compatible =3D "microchip,mcp16502"; + reg =3D <0x5b>; + + regulators { + vdd_3v3: VDD_IO { + regulator-name =3D "VDD_IO"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D <2>; + regulator-allowed-modes =3D <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode =3D <4>; + }; + + regulator-state-mem { + regulator-mode =3D <4>; + }; + }; + + vddioddr: VDD_DDR { + regulator-name =3D "VDD_DDR"; + regulator-min-microvolt =3D <1350000>; + regulator-max-microvolt =3D <1350000>; + regulator-initial-mode =3D <2>; + regulator-allowed-modes =3D <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode =3D <4>; + }; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode =3D <4>; + }; + }; + + vddcore: VDD_CORE { + regulator-name =3D "VDD_CORE"; + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1150000>; + regulator-initial-mode =3D <2>; + regulator-allowed-modes =3D <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode =3D <4>; + }; + + regulator-state-mem { + regulator-mode =3D <4>; + }; + }; + + dcdc4: VDD_OTHER { + regulator-name =3D "VDD_OTHER"; + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1150000>; + regulator-initial-mode =3D <2>; + regulator-allowed-modes =3D <2>, <4>; + regulator-ramp-delay =3D <3125>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode =3D <4>; + }; + + regulator-state-mem { + regulator-mode =3D <4>; + }; + }; + + vldo1: LDO1 { + regulator-name =3D "LDO1"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + }; + }; + + vldo2: LDO2 { + regulator-name =3D "LDO2"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-standby { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2s { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2s_default>; + #sound-dai-cells =3D <0>; + status =3D "okay"; +}; + +&main_xtal { + clock-frequency =3D <24000000>; +}; + +&pinctrl { + classd { + pinctrl_classd_default: classd-default { + atmel,pins =3D + , + ; + }; + }; + + dbgu { + pinctrl_dbgu_default: dbgu-default { + atmel,pins =3D , + ; + }; + }; + + flexcom { + pinctrl_flx6_default: flx6-default { + atmel,pins =3D + , + ; + }; + }; + + gpio-keys { + pinctrl_key_gpio_default: key-gpio-default { + atmel,pins =3D ; + }; + }; + + i2s { + pinctrl_i2s_default: i2s-default { + atmel,pins =3D + , /* I2SCK */ + , /* I2SWS */ + , /* I2SDIN */ + , /* I2SDOUT */ + ; /* I2SMCK */ + }; + }; + + leds { + pinctrl_red_led_gpio_default: red-led-gpio-default { + atmel,pins =3D ; + }; + pinctrl_green_led_gpio_default: green-led-gpio-default { + atmel,pins =3D ; + }; + pinctrl_blue_led_gpio_default: blue-led-gpio-default { + atmel,pins =3D ; + }; + }; + + sdmmc0 { + pinctrl_sdmmc0_default: sdmmc0-default { + atmel,pins =3D + , /* PA2 CK periph A with pullup */ + , /* PA1 CMD periph A with pullup = */ + , /* PA0 DAT0 periph A */ + , /* PA3 DAT1 periph A with pullup= */ + , /* PA4 DAT2 periph A with pullup= */ + ; /* PA5 DAT3 periph A with pullup= */ + }; + }; +}; /* pinctrl */ + +&rtt { + atmel,rtt-rtc-time-reg =3D <&gpbr 0x0>; +}; + +&sdmmc0 { + bus-width =3D <4>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sdmmc0_default>; + cd-gpios =3D <&pioA 23 GPIO_ACTIVE_LOW>; + disable-wp; + status =3D "okay"; +}; + +&slow_xtal { + clock-frequency =3D <32768>; +}; + +&poweroff { + debounce-delay-us =3D <976>; + status =3D "okay"; + + input@0 { + reg =3D <0>; + }; +}; + +&trng { + status =3D "okay"; +}; + +&watchdog { + status =3D "okay"; +}; --=20 2.25.1