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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2cd8cd2013fsm7951282a91.0.2024.07.28.23.15.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jul 2024 23:15:16 -0700 (PDT) From: hpchen0 To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, hpchen0 Subject: [PATCH 1/2] dt-bindings: phy: nuvoton,ma35-usb2-phy: add new bindings Date: Mon, 29 Jul 2024 06:15:08 +0000 Message-Id: <20240729061509.83828-2-hpchen0nvt@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729061509.83828-1-hpchen0nvt@gmail.com> References: <20240729061509.83828-1-hpchen0nvt@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add dt-bindings for USB2 PHY found on the Nuvoton MA35 SoC. Signed-off-by: hpchen0 --- .../bindings/phy/nuvoton,ma35-usb2-phy.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/nuvoton,ma35-usb2= -phy.yaml diff --git a/Documentation/devicetree/bindings/phy/nuvoton,ma35-usb2-phy.ya= ml b/Documentation/devicetree/bindings/phy/nuvoton,ma35-usb2-phy.yaml new file mode 100644 index 000000000000..415ea2c45975 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/nuvoton,ma35-usb2-phy.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/nuvoton,ma35-usb2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35 USB2 phy + +maintainers: + - hpchen0 + +properties: + compatible: + enum: + - nuvoton,ma35-usb2-phy + + "#phy-cells": + const: 0 + + clocks: + maxItems: 1 + description: USB PHY clock + + clock-names: + const: usbd_gate + + nuvoton,sys: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle of the system-management node. + +required: + - compatible + - clocks + - nuvoton,sys + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + usb_phy: usb-phy { + compatible =3D "nuvoton,ma35-usb2-phy"; + clocks =3D <&clk USBD_GATE>; + clock-names =3D "usbd_gate"; + nuvoton,sys =3D <&sys>; + #phy-cells =3D <0>; + }; --=20 2.25.1 From nobody Sat Feb 7 18:21:22 2026 Received: from mail-pj1-f47.google.com (mail-pj1-f47.google.com [209.85.216.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0936A84E0D; Mon, 29 Jul 2024 06:15:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722233721; cv=none; b=NPjMbzZe8045NjGxE156FN+3NuLGAPxklmukebftC9Zf0I1sRMEf505h3GPEYa8TiKajOFWJUU8jWuFNI6eWjw3kXVqteM4iE+7U3XCSnqVDy8Zd1l2syavAYAxPPBl/kAipwJHxHlV0bBH6FvGBo2zCcr/9+J1NcJ59FbkuJJg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722233721; c=relaxed/simple; bh=NUy+jTEJyqsig85RtzFjSm8Zl7cV2dfMtpTiYVvlfDA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2cd8cd2013fsm7951282a91.0.2024.07.28.23.15.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jul 2024 23:15:19 -0700 (PDT) From: hpchen0 To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, hpchen0 Subject: [PATCH 2/2] phy: nuvoton: add new driver for the Nuvoton MA35 SoC USB 2.0 PHY Date: Mon, 29 Jul 2024 06:15:09 +0000 Message-Id: <20240729061509.83828-3-hpchen0nvt@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729061509.83828-1-hpchen0nvt@gmail.com> References: <20240729061509.83828-1-hpchen0nvt@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Nuvoton MA35 SoCs support DWC2 USB controller. Add the driver to drive the USB 2.0 PHY transceivers. Signed-off-by: hpchen0 --- drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/nuvoton/Kconfig | 13 +++ drivers/phy/nuvoton/Makefile | 3 + drivers/phy/nuvoton/phy-ma35-usb2.c | 160 ++++++++++++++++++++++++++++ 5 files changed, 178 insertions(+) create mode 100644 drivers/phy/nuvoton/Kconfig create mode 100644 drivers/phy/nuvoton/Makefile create mode 100644 drivers/phy/nuvoton/phy-ma35-usb2.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index dfab1c66b3e5..f73abff416be 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -95,6 +95,7 @@ source "drivers/phy/mediatek/Kconfig" source "drivers/phy/microchip/Kconfig" source "drivers/phy/motorola/Kconfig" source "drivers/phy/mscc/Kconfig" +source "drivers/phy/nuvoton/Kconfig" source "drivers/phy/qualcomm/Kconfig" source "drivers/phy/ralink/Kconfig" source "drivers/phy/realtek/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 5fcbce5f9ab1..ebc399560da4 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -25,6 +25,7 @@ obj-y +=3D allwinner/ \ microchip/ \ motorola/ \ mscc/ \ + nuvoton/ \ qualcomm/ \ ralink/ \ realtek/ \ diff --git a/drivers/phy/nuvoton/Kconfig b/drivers/phy/nuvoton/Kconfig new file mode 100644 index 000000000000..270ee2943287 --- /dev/null +++ b/drivers/phy/nuvoton/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# PHY drivers for Nuvoton MA35 platforms +# +config PHY_MA35_USB + tristate "Nuvoton MA35 USB2.0 PHY driver" + depends on ARCH_MA35 || COMPILE_TEST + depends on OF + select GENERIC_PHY + help + Enable this to support the USB2.0 PHY on the Nuvoton MA35 + series SoCs. + diff --git a/drivers/phy/nuvoton/Makefile b/drivers/phy/nuvoton/Makefile new file mode 100644 index 000000000000..85785e037d5f --- /dev/null +++ b/drivers/phy/nuvoton/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_PHY_MA35_USB) +=3D phy-ma35-usb2.o diff --git a/drivers/phy/nuvoton/phy-ma35-usb2.c b/drivers/phy/nuvoton/phy-= ma35-usb2.c new file mode 100644 index 000000000000..061b31fcfbb1 --- /dev/null +++ b/drivers/phy/nuvoton/phy-ma35-usb2.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Nuvoton Technology Corp. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* USB PHY Miscellaneous Control Register */ +#define MA35_SYS_REG_USBPMISCR 0x60 +#define PHY0POR BIT(0) /* PHY Power-On Reset Control Bit */ +#define PHY0SUSPEND BIT(1) /* PHY Suspend; 0: suspend, 1: operaion */ +#define PHY0COMN BIT(2) /* PHY Common Block Power-Down Control */ +#define PHY0DEVCKSTB BIT(10) /* PHY 60 MHz UTMI clock stable bit */ + +struct ma35_usb_phy { + struct clk *clk; + struct device *dev; + struct regmap *sysreg; +}; + +static int ma35_usb_phy_power_on(struct phy *phy) +{ + struct ma35_usb_phy *p_phy =3D phy_get_drvdata(phy); + unsigned long timeout; + unsigned int val; + int ret; + + ret =3D clk_prepare_enable(p_phy->clk); + if (ret < 0) { + dev_err(p_phy->dev, "Failed to enable PHY clock: %d\n", ret); + return ret; + } + + regmap_read(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, &val); + if (val & PHY0SUSPEND) { + /* + * USB PHY0 is in operation mode already + * make sure USB PHY 60 MHz UTMI Interface Clock ready + */ + timeout =3D jiffies + msecs_to_jiffies(200); + while (time_before(jiffies, timeout)) { + regmap_read(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, &val); + if (val & PHY0DEVCKSTB) + return 0; + usleep_range(1000, 1500); + } + } + + /* + * reset USB PHY0. + * wait until USB PHY0 60 MHz UTMI Interface Clock ready + */ + regmap_update_bits(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, 0x7, (PHY0POR |= PHY0SUSPEND)); + timeout =3D jiffies + msecs_to_jiffies(200); + while (time_before(jiffies, timeout)) { + regmap_read(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, &val); + if (val & PHY0DEVCKSTB) + break; + usleep_range(1000, 1500); + } + + /* make USB PHY0 enter operation mode */ + regmap_update_bits(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, 0x7, PHY0SUSPEN= D); + + /* make sure USB PHY 60 MHz UTMI Interface Clock ready */ + timeout =3D jiffies + msecs_to_jiffies(200); + while (time_before(jiffies, timeout)) { + regmap_read(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, &val); + if (val & PHY0DEVCKSTB) + return 0; + usleep_range(1000, 1500); + } + + dev_err(p_phy->dev, "Timed out waiting for PHY to power on\n"); + ret =3D -ETIMEDOUT; + + clk_disable_unprepare(p_phy->clk); + return ret; +} + +static int ma35_usb_phy_power_off(struct phy *phy) +{ + struct ma35_usb_phy *p_phy =3D phy_get_drvdata(phy); + + clk_disable_unprepare(p_phy->clk); + return 0; +} + +static const struct phy_ops ma35_usb_phy_ops =3D { + .power_on =3D ma35_usb_phy_power_on, + .power_off =3D ma35_usb_phy_power_off, + .owner =3D THIS_MODULE, +}; + +static int ma35_usb_phy_probe(struct platform_device *pdev) +{ + struct phy_provider *provider; + struct ma35_usb_phy *p_phy; + const char *clkgate; + struct phy *phy; + + p_phy =3D devm_kzalloc(&pdev->dev, sizeof(*p_phy), GFP_KERNEL); + if (!p_phy) + return -ENOMEM; + + p_phy->dev =3D &pdev->dev; + platform_set_drvdata(pdev, p_phy); + + p_phy->sysreg =3D syscon_regmap_lookup_by_phandle(p_phy->dev->of_node, "n= uvoton,sys"); + if (IS_ERR(p_phy->sysreg)) + return dev_err_probe(&pdev->dev, PTR_ERR(p_phy->sysreg), + "Failed to get SYS registers\n"); + + /* enable clock */ + of_property_read_string(p_phy->dev->of_node, "clock-enable", &clkgate); + p_phy->clk =3D devm_clk_get(p_phy->dev, clkgate); + if (IS_ERR(p_phy->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(p_phy->clk), + "Failed to get usb_phy clock\n"); + + phy =3D devm_phy_create(p_phy->dev, NULL, &ma35_usb_phy_ops); + if (IS_ERR(phy)) + return dev_err_probe(&pdev->dev, PTR_ERR(phy), "Failed to create PHY\n"); + + phy_set_drvdata(phy, p_phy); + + provider =3D devm_of_phy_provider_register(p_phy->dev, of_phy_simple_xlat= e); + if (IS_ERR(provider)) + return dev_err_probe(&pdev->dev, PTR_ERR(provider), + "Failed to register PHY provider\n"); + return 0; +} + +static const struct of_device_id ma35_usb_phy_of_match[] =3D { + { .compatible =3D "nuvoton,ma35-usb2-phy", }, + { }, +}; +MODULE_DEVICE_TABLE(of, ma35_usb_phy_of_match); + +static struct platform_driver ma35_usb_phy_driver =3D { + .probe =3D ma35_usb_phy_probe, + .driver =3D { + .name =3D "ma35-usb2-phy", + .of_match_table =3D ma35_usb_phy_of_match, + }, +}; +module_platform_driver(ma35_usb_phy_driver); + +MODULE_DESCRIPTION("Nuvoton ma35 USB2.0 PHY driver"); +MODULE_AUTHOR("hpchen0nvt@gmail.com"); +MODULE_LICENSE("GPL"); --=20 2.25.1