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While the controller resembles that of iMX8MP, the PHY differs significantly. Notably, there's a distinction between PCI bus addresses and CPU addresses. Introduce IMX_PCIE_FLAG_CPU_ADDR_FIXUP in drvdata::flags to indicate driver need the cpu_addr_fixup() callback to facilitate CPU address to PCI bus address conversion according to "ranges" property. Signed-off-by: Richard Zhu Reviewed-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 91aab0288fdcb..4928cea05f6fe 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -65,6 +65,7 @@ enum imx_pcie_variants { IMX8MQ, IMX8MM, IMX8MP, + IMX8Q, IMX95, IMX8MQ_EP, IMX8MM_EP, @@ -80,6 +81,7 @@ enum imx_pcie_variants { #define IMX_PCIE_FLAG_HAS_PHY_RESET BIT(5) #define IMX_PCIE_FLAG_HAS_SERDES BIT(6) #define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7) +#define IMX_PCIE_FLAG_CPU_ADDR_FIXUP BIT(8) =20 #define imx_check_flag(pci, val) (pci->drvdata->flags & val) =20 @@ -1011,6 +1013,22 @@ static void imx_pcie_host_exit(struct dw_pcie_rp *pp) regulator_disable(imx_pcie->vpcie); } =20 +static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr) +{ + struct imx_pcie *imx_pcie =3D to_imx_pcie(pcie); + struct dw_pcie_rp *pp =3D &pcie->pp; + struct resource_entry *entry; + unsigned int offset; + + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_CPU_ADDR_FIXUP)) + return cpu_addr; + + entry =3D resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); + offset =3D entry->offset; + + return (cpu_addr - offset); +} + static const struct dw_pcie_host_ops imx_pcie_host_ops =3D { .init =3D imx_pcie_host_init, .deinit =3D imx_pcie_host_exit, @@ -1019,6 +1037,7 @@ static const struct dw_pcie_host_ops imx_pcie_host_op= s =3D { static const struct dw_pcie_ops dw_pcie_ops =3D { .start_link =3D imx_pcie_start_link, .stop_link =3D imx_pcie_stop_link, + .cpu_addr_fixup =3D imx_pcie_cpu_addr_fixup, }; =20 static void imx_pcie_ep_init(struct dw_pcie_ep *ep) @@ -1461,6 +1480,7 @@ static const char * const imx6q_clks[] =3D {"pcie_bus= ", "pcie", "pcie_phy"}; static const char * const imx8mm_clks[] =3D {"pcie_bus", "pcie", "pcie_aux= "}; static const char * const imx8mq_clks[] =3D {"pcie_bus", "pcie", "pcie_phy= ", "pcie_aux"}; static const char * const imx6sx_clks[] =3D {"pcie_bus", "pcie", "pcie_phy= ", "pcie_inbound_axi"}; +static const char * const imx8q_clks[] =3D {"mstr", "slv", "dbi"}; =20 static const struct imx_pcie_drvdata drvdata[] =3D { [IMX6Q] =3D { @@ -1564,6 +1584,13 @@ static const struct imx_pcie_drvdata drvdata[] =3D { .mode_mask[0] =3D IMX6Q_GPR12_DEVICE_TYPE, .enable_ref_clk =3D imx8mm_pcie_enable_ref_clk, }, + [IMX8Q] =3D { + .variant =3D IMX8Q, + .flags =3D IMX_PCIE_FLAG_HAS_PHYDRV | + IMX_PCIE_FLAG_CPU_ADDR_FIXUP, + .clk_names =3D imx8q_clks, + .clks_cnt =3D ARRAY_SIZE(imx8q_clks), + }, [IMX95] =3D { .variant =3D IMX95, .flags =3D IMX_PCIE_FLAG_HAS_SERDES, @@ -1641,6 +1668,7 @@ static const struct of_device_id imx_pcie_of_match[] = =3D { { .compatible =3D "fsl,imx8mq-pcie", .data =3D &drvdata[IMX8MQ], }, { .compatible =3D "fsl,imx8mm-pcie", .data =3D &drvdata[IMX8MM], }, { .compatible =3D "fsl,imx8mp-pcie", .data =3D &drvdata[IMX8MP], }, + { .compatible =3D "fsl,imx8q-pcie", .data =3D &drvdata[IMX8Q], }, { .compatible =3D "fsl,imx95-pcie", .data =3D &drvdata[IMX95], }, { .compatible =3D "fsl,imx8mq-pcie-ep", .data =3D &drvdata[IMX8MQ_EP], }, { .compatible =3D "fsl,imx8mm-pcie-ep", .data =3D &drvdata[IMX8MM_EP], }, --=20 2.34.1