From nobody Mon Sep 16 19:59:18 2024 Received: from mail-oi1-f176.google.com (mail-oi1-f176.google.com [209.85.167.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D59B4282EE; Sat, 27 Jul 2024 05:09:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722056951; cv=none; b=IWpHTuk9L9BUHn6JIx0Fw50AcI4xN1yzJrWCe1u+BmyyesDE0jViMT6IEN6m20uPH/M1nVuFG55aj8GoXlB0XA+QQ9VXiI87MeHqc91GFgvnNVqsvMx3LrOyOKcCENJeWuGhpabuJWjamvCMo5Zo+m9TfFs/CkEg5ozS2atnkEQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722056951; c=relaxed/simple; bh=/2NWqLRm7vR2tJQCwRFY6lKLcDi5Nvh2hiXFpvYNEVg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NP+zg017HiOK1UZkzp7EK7UnV7N6ykZcaBlky0vMhG9OZbDmomJ3avM2c+6Wd9H5cQ7uw7VFiEeoCX2nfYo23Ox+7t9OyDHDC6LB/YAuRQ9XM29MyeD30Jpw/oitUYRCrtGYRgBXCfru+cIsanRzuhEGQgp1cbkCkNIczzgTBx4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=hrBrENMY; arc=none smtp.client-ip=209.85.167.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hrBrENMY" Received: by mail-oi1-f176.google.com with SMTP id 5614622812f47-3db1d4dab7fso753496b6e.1; Fri, 26 Jul 2024 22:09:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1722056949; x=1722661749; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Jskn060TGJq5Co5vXiUSQP3ayqytOiAl7GKb00mvlwU=; b=hrBrENMY9inHxJwxCqt9AZFkPfIdQigd5oOzMOTFA6oTe0aykftBDuhai2hyDOIAkW oXNAPP0nrosBDzGw4F9sSGCOw670XKagkqndxFxpH3hrvml2Jn7cNndtjP2YvLWUiiDZ WH6K160HqVQzb3dYF+U83UZqzdypEeBhZu4Wd+JRgw1p6DwXpsbbGgMZyyLRHBtiFv5q 3yOSdmDBz2RiFPuQub/1ywnOYYsUUD/oGHos3jjSOBUvEiqff1pDz/6HVRWR9SqUMSsN Pfgzngk96TJPnGU8iM5noO7PQtlLe8Z608+zUPfd9iWIXCDkts36jJ7R4S1Br++NnumB i4Gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722056949; x=1722661749; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Jskn060TGJq5Co5vXiUSQP3ayqytOiAl7GKb00mvlwU=; b=vdqnYOik2/ykjcoQMDDVwEhqpQODXZz0luFib+r3Manlj20/MaPSeS8ebCTmbJ28YO SQyfo7G1SlrAVq+tyFTsK9xBO0Mud3mJHJi2XiqwKUlJU6xEyA9BK+XiDWK/qHZNdryq l/3o3RE2eibH+wp4WcgyvdGh2kcJ/rkAsIXBsKRK0pDfSWBYNov58S2PrQeAsou2VG6d TUqPyZerPiSYQY8YCOejBpBaa4pbXJaYDThdTdq/nztikJ03hfObJa1CZ6+dkmqGV0b9 356vWx26VmzFXLRakoCw2tNg2hZJnHyo4ctJrzvg6QX4eXV+j2gG2d10W/DS+B8PVp2v o9XA== X-Forwarded-Encrypted: i=1; AJvYcCW0hhhlF5zF/ud5rN6kMW+czePteMuzHuLXqkyOzDRI1OF0EyFxb8OJt1vqQYdT0FzhhzPT7IQKVBMX+4g8s0iytvMpdXyyaeTLeLvR6WsBG6p+Ad7krmrToa1EZ13h6pq90UNNce2gkzJTphU= X-Gm-Message-State: AOJu0Yx8HehWuZENfFe9M7XUNXsdDGN63YPvyPzu3aJRb9RJAsRoYDS4 x9KLzXHLTnQ/dSFZ/vefFgOCDFVWwMvGL+wdKs4nzTCGrW8e+xEE X-Google-Smtp-Source: AGHT+IHrBTWJGfiE6gm3x43/Am7Z8OjiEWDYyi4+knnsglpPE5cEkP1i5OP/IB1blYEMALI7+f3v2g== X-Received: by 2002:a05:6808:1387:b0:3da:bc74:e9c7 with SMTP id 5614622812f47-3db23aa5748mr2335158b6e.38.1722056948839; Fri, 26 Jul 2024 22:09:08 -0700 (PDT) Received: from kousik.local ([2405:201:c006:380f:4245:58a3:6108:fcf0]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70ead87a372sm3495756b3a.166.2024.07.26.22.08.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jul 2024 22:09:08 -0700 (PDT) From: Kousik Sanagavarapu To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wim Van Sebroeck , Guenter Roeck Cc: devicetree@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org, Kousik Sanagavarapu , Krzysztof Kozlowski Subject: [PATCH v4 1/2] dt-bindings: timer: ti,davinci-timer: convert to dtschema Date: Sat, 27 Jul 2024 10:34:43 +0530 Message-ID: <20240727050736.4756-2-five231003@gmail.com> X-Mailer: git-send-email 2.45.2.827.g557ae147e6.dirty In-Reply-To: <20240727050736.4756-1-five231003@gmail.com> References: <20240727050736.4756-1-five231003@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert txt binding of TI's DaVinci timer to dtschema to allow for validation. While at it, change the file name to match the compatible. Signed-off-by: Kousik Sanagavarapu Reviewed-by: Krzysztof Kozlowski --- .../bindings/timer/ti,da830-timer.yaml | 68 +++++++++++++++++++ .../bindings/timer/ti,davinci-timer.txt | 37 ---------- 2 files changed, 68 insertions(+), 37 deletions(-) create mode 100644 Documentation/devicetree/bindings/timer/ti,da830-timer.= yaml delete mode 100644 Documentation/devicetree/bindings/timer/ti,davinci-time= r.txt diff --git a/Documentation/devicetree/bindings/timer/ti,da830-timer.yaml b/= Documentation/devicetree/bindings/timer/ti,da830-timer.yaml new file mode 100644 index 000000000000..e9646f4e86cc --- /dev/null +++ b/Documentation/devicetree/bindings/timer/ti,da830-timer.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/ti,da830-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI DaVinci Timer + +maintainers: + - Kousik Sanagavarapu + +description: | + This is a 64-bit timer found on TI's DaVinci architecture devices. The t= imer + can be configured as a general-purpose 64-bit timer, dual general-purpose + 32-bit timers. When configured as dual 32-bit timers, each half can oper= ate + in conjunction (chain mode) or independently (unchained mode) of each ot= her. + + The timer is a free running up-counter and can generate interrupts when = the + counter reaches preset counter values. + +properties: + compatible: + const: ti,da830-timer + + reg: + maxItems: 1 + + interrupts: + minItems: 2 + maxItems: 10 + + interrupt-names: + minItems: 2 + items: + - const: tint12 + - const: tint34 + - const: cmpint0 + - const: cmpint1 + - const: cmpint2 + - const: cmpint3 + - const: cmpint4 + - const: cmpint5 + - const: cmpint6 + - const: cmpint7 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + +additionalProperties: false + +examples: + - | + timer@20000 { + compatible =3D "ti,da830-timer"; + reg =3D <0x20000 0x1000>; + interrupts =3D <21>, <22>; + interrupt-names =3D "tint12", "tint34"; + clocks =3D <&pll0_auxclk>; + }; + +... diff --git a/Documentation/devicetree/bindings/timer/ti,davinci-timer.txt b= /Documentation/devicetree/bindings/timer/ti,davinci-timer.txt deleted file mode 100644 index 29bf91ccf5b7..000000000000 --- a/Documentation/devicetree/bindings/timer/ti,davinci-timer.txt +++ /dev/null @@ -1,37 +0,0 @@ -* Device tree bindings for Texas Instruments DaVinci timer - -This document provides bindings for the 64-bit timer in the DaVinci -architecture devices. The timer can be configured as a general-purpose 64-= bit -timer, dual general-purpose 32-bit timers. When configured as dual 32-bit -timers, each half can operate in conjunction (chain mode) or independently -(unchained mode) of each other. - -The timer is a free running up-counter and can generate interrupts when the -counter reaches preset counter values. - -Also see ../watchdog/davinci-wdt.txt for timers that are configurable as -watchdog timers. - -Required properties: - -- compatible : should be "ti,da830-timer". -- reg : specifies base physical address and count of the registers. -- interrupts : interrupts generated by the timer. -- interrupt-names: should be "tint12", "tint34", "cmpint0", "cmpint1", - "cmpint2", "cmpint3", "cmpint4", "cmpint5", "cmpint6", - "cmpint7" ("cmpintX" may be omitted if not present in the - hardware). -- clocks : the clock feeding the timer clock. - -Example: - - clocksource: timer@20000 { - compatible =3D "ti,da830-timer"; - reg =3D <0x20000 0x1000>; - interrupts =3D <21>, <22>, <74>, <75>, <76>, <77>, <78>, <79>, - <80>, <81>; - interrupt-names =3D "tint12", "tint34", "cmpint0", "cmpint1", - "cmpint2", "cmpint3", "cmpint4", "cmpint5", - "cmpint6", "cmpint7"; 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charset="utf-8" Convert txt bindings of TI's DaVinci/Keystone Watchdog Timer Controller to dtschema to allow for validation. While at it, - Change the order of the compatibles. - Add "power-domains" to represent that the power domain maybe managed by TI-SCI controller if found on the SoC (for example, Keystone based K2G). w.r.t. to the txt binding to stay in sync with existing DTS. Signed-off-by: Kousik Sanagavarapu Reviewed-by: Krzysztof Kozlowski --- .../bindings/watchdog/davinci-wdt.txt | 24 -------- .../bindings/watchdog/ti,davinci-wdt.yaml | 55 +++++++++++++++++++ 2 files changed, 55 insertions(+), 24 deletions(-) delete mode 100644 Documentation/devicetree/bindings/watchdog/davinci-wdt.= txt create mode 100644 Documentation/devicetree/bindings/watchdog/ti,davinci-w= dt.yaml diff --git a/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt b/D= ocumentation/devicetree/bindings/watchdog/davinci-wdt.txt deleted file mode 100644 index aa10b8ec36e2..000000000000 --- a/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt +++ /dev/null @@ -1,24 +0,0 @@ -Texas Instruments DaVinci/Keystone Watchdog Timer (WDT) Controller - -Required properties: -- compatible : Should be "ti,davinci-wdt", "ti,keystone-wdt" -- reg : Should contain WDT registers location and length - -Optional properties: -- timeout-sec : Contains the watchdog timeout in seconds -- clocks : the clock feeding the watchdog timer. - Needed if platform uses clocks. - See clock-bindings.txt - -Documentation: -Davinci DM646x - https://www.ti.com/lit/ug/spruer5b/spruer5b.pdf -Keystone - https://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf - -Examples: - -wdt: wdt@2320000 { - compatible =3D "ti,davinci-wdt"; - reg =3D <0x02320000 0x80>; - timeout-sec =3D <30>; - clocks =3D <&clkwdtimer0>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/ti,davinci-wdt.yaml= b/Documentation/devicetree/bindings/watchdog/ti,davinci-wdt.yaml new file mode 100644 index 000000000000..3c78f60f5f48 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/ti,davinci-wdt.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/ti,davinci-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI DaVinci/Keystone Watchdog Timer Controller + +maintainers: + - Kousik Sanagavarapu + +description: | + TI's Watchdog Timer Controller for DaVinci and Keystone Processors. + + Datasheets + + Davinci DM646x - https://www.ti.com/lit/ug/spruer5b/spruer5b.pdf + Keystone - https://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + oneOf: + - items: + - const: ti,keystone-wdt + - const: ti,davinci-wdt + - items: + - const: ti,davinci-wdt + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + wdt: watchdog@22f0080 { + compatible =3D "ti,keystone-wdt", "ti,davinci-wdt"; + reg =3D <0x022f0080 0x80>; + clocks =3D <&clkwdtimer0>; + }; + +... --=20 2.45.2.827.g557ae147e6.dirty