From nobody Mon Sep 16 19:39:54 2024 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A691E177981; Fri, 26 Jul 2024 10:24:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721989496; cv=none; b=j/axZSxLen+rvipTkcmBLZBRccJ7s35AeKsoIVwG4NSgO4viQF2paF6r66+tL2Y0OTfNqPCZJ+Hnu5RnmnCqgHlTYvTfCdGrALy5woTwvy6EgDwK7HQw3gE9VlN0eX8vEGq5jlEkrwLqRQPIiu5wqoEoDdbxVZ7N3lmjJ5MhtLs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721989496; c=relaxed/simple; bh=dzI/zsPyKQCK28oV3k7uem09cC7627zq5DBwESNoFCM=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version:Content-Type; b=R3T7i9vSlmPH6IFFPNXC1039BOw2Z+5gM8PuTRfvSRZM5y3rPLr01ql3nbSQzWG2+V6HvCrhQdXlXsu8G6tOL5TX0xtsM8UFUEvL+m5MCHYwgMybVnVy1aJMCXWeECeG3GOj5t5MUx0RhBaygPfgZeTK4wDTWvAqb5FVHtLmyp4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.10.34]) by gateway (Coremail) with SMTP id _____8AxW+pveaNmTAoCAA--.7642S3; Fri, 26 Jul 2024 18:24:47 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.10.34]) by front1 (Coremail) with SMTP id qMiowMAxusVteaNm2J4CAA--.11906S2; Fri, 26 Jul 2024 18:24:45 +0800 (CST) From: Tianyang Zhang To: corbet@lwn.net, alexs@kernel.org, siyanteng@loongson.cn, chenhuacai@kernel.org, kernel@xen0n.name, tglx@linutronix.de, jiaxun.yang@flygoat.com, gaoliang@loongson.cn, wangliupu@loongson.cn, lvjianmin@loongson.cn, zhangtianyang@loongson.cn, yijun@loongson.cn, mhocko@suse.com, akpm@linux-foundation.org, dianders@chromium.org, maobibo@loongson.cn, xry111@xry111.site, zhaotianrui@loongson.cn, nathan@kernel.org, yangtiezhu@loongson.cn, zhoubinbin@loongson.cn Cc: loongarch@lists.linux.dev, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Huacai Chen Subject: [PATCH V7] LoongArch: Add AVEC irqchip support Date: Fri, 26 Jul 2024 18:24:43 +0800 Message-Id: <20240726102443.12471-1-zhangtianyang@loongson.cn> X-Mailer: git-send-email 2.20.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMAxusVteaNm2J4CAA--.11906S2 X-CM-SenderInfo: x2kd0wxwld05hdqjqz5rrqw2lrqou0/ X-Coremail-Antispam: 1Uk129KBj9fXoWfuFy5CryfJw4xGw15Kw47KFX_yoW5tFyrJo WfZF1Yy348Gr45urZ5Jr1qqFyUZr4jkrWkA3sruanxCFyxAF15KryUKw13KFy3Jrs5GFZx GayfWrn3Ja97trn5l-sFpf9Il3svdjkaLaAFLSUrUUUU5b8apTn2vfkv8UJUUUU8wcxFpf 9Il3svdxBIdaVrn0xqx4xG64xvF2IEw4CE5I8CrVC2j2Jv73VFW2AGmfu7bjvjm3AaLaJ3 UjIYCTnIWjp_UUUYC7kC6x804xWl14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI 8IcIk0rVWrJVCq3wAFIxvE14AKwVWUXVWUAwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xG Y2AK021l84ACjcxK6xIIjxv20xvE14v26r1I6r4UM28EF7xvwVC0I7IYx2IY6xkF7I0E14 v26r4j6F4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_Gr1j6F4UJwAaw2AFwI0_JF0_Jw1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2 xF0cIa020Ex4CE44I27wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_ Jw0_WrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x 0EwIxGrwCY1x0262kKe7AKxVWUtVW8ZwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkE bVWUJVW8JwCFI7km07C267AKxVWUAVWUtwC20s026c02F40E14v26r1j6r18MI8I3I0E74 80Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr41lIxAIcVC0 I7IYx2IY67AKxVWUCVW8JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04 k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7Cj xVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x07jnEfOUUUUU= Introduce the advanced extended interrupt controllers (AVECINTC). This feature will allow each core to have 256 independent interrupt vectors and MSI interrupts can be independently routed to any vector on any CPU. The whole topology of irqchips in LoongArch machines looks like this if AVECINTC is supported: +-----+ +-----------------------+ +-------+ | IPI | --> | CPUINTC | <-- | Timer | +-----+ +-----------------------+ +-------+ ^ ^ ^ | | | +---------+ +----------+ +---------+ +-------+ | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs | +---------+ +----------+ +---------+ +-------+ ^ ^ | | +---------+ +---------+ | PCH-PIC | | PCH-MSI | +---------+ +---------+ ^ ^ ^ | | | +---------+ +---------+ +---------+ | Devices | | PCH-LPC | | Devices | +---------+ +---------+ +---------+ ^ | +---------+ | Devices | +---------+ Co-developed-by: Jianmin Lv Signed-off-by: Jianmin Lv Co-developed-by: Liupu Wang Signed-off-by: Liupu Wang Co-developed-by: Huacai Chen Signed-off-by: Huacai Chen Signed-off-by: Tianyang Zhang --- .../arch/loongarch/irq-chip-model.rst | 32 ++ .../zh_CN/arch/loongarch/irq-chip-model.rst | 32 ++ arch/loongarch/Kconfig | 1 + arch/loongarch/include/asm/cpu-features.h | 1 + arch/loongarch/include/asm/cpu.h | 2 + arch/loongarch/include/asm/hardirq.h | 3 +- arch/loongarch/include/asm/irq.h | 25 +- arch/loongarch/include/asm/loongarch.h | 18 +- arch/loongarch/include/asm/smp.h | 2 + arch/loongarch/kernel/cpu-probe.c | 3 +- arch/loongarch/kernel/irq.c | 14 +- arch/loongarch/kernel/paravirt.c | 5 + arch/loongarch/kernel/smp.c | 6 + drivers/irqchip/Makefile | 2 +- drivers/irqchip/irq-loongarch-avec.c | 447 ++++++++++++++++++ drivers/irqchip/irq-loongarch-cpu.c | 5 +- drivers/irqchip/irq-loongson-eiointc.c | 7 +- drivers/irqchip/irq-loongson-pch-msi.c | 41 +- include/linux/cpuhotplug.h | 3 +- 19 files changed, 632 insertions(+), 17 deletions(-) create mode 100644 drivers/irqchip/irq-loongarch-avec.c Changes log: V0->V1: 1.Modified some formats and declarations 2.Removed kmalloc/kfree when adding affinity related data to pendi= ng_list, and used moving tag to replace the original behavior 3.Adjusted the process that enables AVEC interrupts, now it is at = the end of all processes 4.Removed CPUHP related callbacks, now irq_matrix_online/irq_matri= x_offline is completed in start_secondary/loongson_cpu_disable 5.Adjusted compatibility issues for CONFIG_ACPI 6.About question: > irr =3D csr_read64(LOONGARCH_CSR_IRR0 + vector / 64); > should be good enough, no? csr_read64 was built-in as __csrrd_d, it doesn't seem to support v= ariables as parameters >>>> drivers/irqchip/irq-loongarch-avec.c: In function =E2=80=98complet= e_irq_moving=E2=80=99: ./arch/loongarch/include/asm/loongarch.h:164:25: error: invalid ar= gument to built-in function 164 | #define csr_read64(reg) __csrrd_d(reg) | ^~~~~~~~~ drivers/irqchip/irq-loongarch-avec.c:170:23: note: in expansion of= macro =E2=80=98csr_read64=E2=80=99 170 | irr =3D csr_read64(LOONGARCH_CSR_IRR_BASE = + vector / VECTORS_PER_REG); | ^~~~~~~~~~ >>>> So we have temporarily retained the previous implementation. =20 V1->V2: Fixed up coding style. Made on/offline functions void Added compatibility when CONFIG_SMP is turned off =20 V2->V3: Squash two patches into one =20 V3->V4: Update NR_IRQS Update Register's name Fixed up coding style V4->V5: Retain feature CPUCFG1_MSGINT=09 Fixed up coding style Delete the test code introduced by V4, and now msi msg address still uses = the 32-bit address V5->V6: Fix definition of NR_IRQS Define arch_probe_nr_irqs() Handle all avecintc interrupts in one dispatch Use cpuhotplug callbacks instead of direct call to avec_online_cpu()/avec_= offline_cpu() Rename {SMP,ACTION}_CLEAR_VECT to {SMP,ACTION}_CLEAR_VECTOR Use avecintc_ prefix instead of loongarch_avec_ to keep consistancy V6->V7: Fixed compatibility issue with cpuhp_setup_state_nocalls when CONFIG_SMP i= s turned off Rename avecintc_online/offline_cpu as avecintc_cpu_online/offline Use pch_msi_handle[0] as default value of get_pch_msi_handle Rework commit-message =09 diff --git a/Documentation/arch/loongarch/irq-chip-model.rst b/Documentatio= n/arch/loongarch/irq-chip-model.rst index 7988f41923639..6dd48256e39f7 100644 --- a/Documentation/arch/loongarch/irq-chip-model.rst +++ b/Documentation/arch/loongarch/irq-chip-model.rst @@ -85,6 +85,38 @@ to CPUINTC directly:: | Devices | +---------+ =20 +Advanced Extended IRQ model +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D + +In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interru= pt go +to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupt= s go +to AVECINTC, and then go to CPUINTC directly, while all other devices inte= rrupts +go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then go to CPUINTC dire= ctly:: + + +-----+ +-----------------------+ +-------+ + | IPI | --> | CPUINTC | <-- | Timer | + +-----+ +-----------------------+ +-------+ + ^ ^ ^ + | | | + +---------+ +----------+ +---------+ +-------+ + | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs | + +---------+ +----------+ +---------+ +-------+ + ^ ^ + | | + +---------+ +---------+ + | PCH-PIC | | PCH-MSI | + +---------+ +---------+ + ^ ^ ^ + | | | + +---------+ +---------+ +---------+ + | Devices | | PCH-LPC | | Devices | + +---------+ +---------+ +---------+ + ^ + | + +---------+ + | Devices | + +---------+ + ACPI-related definitions =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 diff --git a/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model= .rst b/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst index f1e9ab18206c3..472761938682c 100644 --- a/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst +++ b/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst @@ -87,6 +87,38 @@ PCH-LPC/PCH-MSI=EF=BC=8C=E7=84=B6=E5=90=8E=E8=A2=ABEIOIN= TC=E7=BB=9F=E4=B8=80=E6=94=B6=E9=9B=86=EF=BC=8C=E5=86=8D=E7=9B=B4=E6=8E=A5= =E5=88=B0=E8=BE=BECPUINTC:: | Devices | +---------+ =20 +=E9=AB=98=E7=BA=A7=E6=89=A9=E5=B1=95IRQ=E6=A8=A1=E5=9E=8B +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +=E5=9C=A8=E8=BF=99=E7=A7=8D=E6=A8=A1=E5=9E=8B=E9=87=8C=E9=9D=A2=EF=BC=8CIP= I=EF=BC=88Inter-Processor Interrupt=EF=BC=89=E5=92=8CCPU=E6=9C=AC=E5=9C=B0= =E6=97=B6=E9=92=9F=E4=B8=AD=E6=96=AD=E7=9B=B4=E6=8E=A5=E5=8F=91=E9=80=81=E5= =88=B0CPUINTC=EF=BC=8C +CPU=E4=B8=B2=E5=8F=A3=EF=BC=88UARTs=EF=BC=89=E4=B8=AD=E6=96=AD=E5=8F=91=E9= =80=81=E5=88=B0LIOINTC=EF=BC=8CPCH-MSI=E4=B8=AD=E6=96=AD=E5=8F=91=E9=80=81= =E5=88=B0AVECINTC=EF=BC=8C=E8=80=8C=E5=90=8E=E9=80=9A=E8=BF=87AVECINTC=E7= =9B=B4=E6=8E=A5 +=E9=80=81=E8=BE=BECPUINTC=EF=BC=8C=E8=80=8C=E5=85=B6=E4=BB=96=E6=89=80=E6= =9C=89=E8=AE=BE=E5=A4=87=E7=9A=84=E4=B8=AD=E6=96=AD=E5=88=99=E5=88=86=E5=88= =AB=E5=8F=91=E9=80=81=E5=88=B0=E6=89=80=E8=BF=9E=E6=8E=A5=E7=9A=84PCH-PIC/P= CH-LPC=EF=BC=8C=E7=84=B6=E5=90=8E=E7=94=B1EIOINTC +=E7=BB=9F=E4=B8=80=E6=94=B6=E9=9B=86=EF=BC=8C=E5=86=8D=E7=9B=B4=E6=8E=A5= =E5=88=B0=E8=BE=BECPUINTC:: + + +-----+ +-----------------------+ +-------+ + | IPI | --> | CPUINTC | <-- | Timer | + +-----+ +-----------------------+ +-------+ + ^ ^ ^ + | | | + +---------+ +----------+ +---------+ +-------+ + | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs | + +---------+ +----------+ +---------+ +-------+ + ^ ^ + | | + +---------+ +---------+ + | PCH-PIC | | PCH-MSI | + +---------+ +---------+ + ^ ^ ^ + | | | + +---------+ +---------+ +---------+ + | Devices | | PCH-LPC | | Devices | + +---------+ +---------+ +---------+ + ^ + | + +---------+ + | Devices | + +---------+ + ACPI=E7=9B=B8=E5=85=B3=E7=9A=84=E5=AE=9A=E4=B9=89 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig index ebdb7156560c7..e30641fa80706 100644 --- a/arch/loongarch/Kconfig +++ b/arch/loongarch/Kconfig @@ -85,6 +85,7 @@ config LOONGARCH select GENERIC_ENTRY select GENERIC_GETTIMEOFDAY select GENERIC_IOREMAP if !ARCH_IOREMAP + select GENERIC_IRQ_MATRIX_ALLOCATOR select GENERIC_IRQ_MULTI_HANDLER select GENERIC_IRQ_PROBE select GENERIC_IRQ_SHOW diff --git a/arch/loongarch/include/asm/cpu-features.h b/arch/loongarch/inc= lude/asm/cpu-features.h index 2eafe6a6aca81..16a716f88a5ca 100644 --- a/arch/loongarch/include/asm/cpu-features.h +++ b/arch/loongarch/include/asm/cpu-features.h @@ -65,5 +65,6 @@ #define cpu_has_guestid cpu_opt(LOONGARCH_CPU_GUESTID) #define cpu_has_hypervisor cpu_opt(LOONGARCH_CPU_HYPERVISOR) #define cpu_has_ptw cpu_opt(LOONGARCH_CPU_PTW) +#define cpu_has_avecint cpu_opt(LOONGARCH_CPU_AVECINT) =20 #endif /* __ASM_CPU_FEATURES_H */ diff --git a/arch/loongarch/include/asm/cpu.h b/arch/loongarch/include/asm/= cpu.h index 48b9f7168bcca..843f9c4ec9807 100644 --- a/arch/loongarch/include/asm/cpu.h +++ b/arch/loongarch/include/asm/cpu.h @@ -99,6 +99,7 @@ enum cpu_type_enum { #define CPU_FEATURE_GUESTID 24 /* CPU has GuestID feature */ #define CPU_FEATURE_HYPERVISOR 25 /* CPU has hypervisor (running in VM) */ #define CPU_FEATURE_PTW 26 /* CPU has hardware page table walker */ +#define CPU_FEATURE_AVECINT 27 /* CPU has avec interrupt */ =20 #define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG) #define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM) @@ -127,5 +128,6 @@ enum cpu_type_enum { #define LOONGARCH_CPU_GUESTID BIT_ULL(CPU_FEATURE_GUESTID) #define LOONGARCH_CPU_HYPERVISOR BIT_ULL(CPU_FEATURE_HYPERVISOR) #define LOONGARCH_CPU_PTW BIT_ULL(CPU_FEATURE_PTW) +#define LOONGARCH_CPU_AVECINT BIT_ULL(CPU_FEATURE_AVECINT) =20 #endif /* _ASM_CPU_H */ diff --git a/arch/loongarch/include/asm/hardirq.h b/arch/loongarch/include/= asm/hardirq.h index 1d7feb7195157..10da8d6961cb0 100644 --- a/arch/loongarch/include/asm/hardirq.h +++ b/arch/loongarch/include/asm/hardirq.h @@ -12,12 +12,13 @@ extern void ack_bad_irq(unsigned int irq); #define ack_bad_irq ack_bad_irq =20 -#define NR_IPI 3 +#define NR_IPI 4 =20 enum ipi_msg_type { IPI_RESCHEDULE, IPI_CALL_FUNCTION, IPI_IRQ_WORK, + IPI_CLEAR_VECTOR, }; =20 typedef struct { diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/= irq.h index 480418bc5071a..1b255bf8168f0 100644 --- a/arch/loongarch/include/asm/irq.h +++ b/arch/loongarch/include/asm/irq.h @@ -39,11 +39,22 @@ void spurious_interrupt(void); =20 #define NR_IRQS_LEGACY 16 =20 +/* + * 256 Vectors Mapping for AVECINTC: + * + * 0 - 15: Mapping classic IPs, e.g. IP0-12. + * 16 - 255: Mapping vectors for external IRQ. + * + */ +#define NR_VECTORS 256 +#define NR_LEGACY_VECTORS 16 +#define IRQ_MATRIX_BITS NR_VECTORS + #define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace void arch_trigger_cpumask_backtrace(const struct cpumask *mask, int exclud= e_cpu); =20 #define MAX_IO_PICS 2 -#define NR_IRQS (64 + (256 * MAX_IO_PICS)) +#define NR_IRQS (64 + NR_VECTORS * (NR_CPUS + MAX_IO_PICS)) =20 struct acpi_vector_group { int node; @@ -65,7 +76,7 @@ extern struct acpi_vector_group msi_group[MAX_IO_PICS]; #define LOONGSON_LPC_LAST_IRQ (LOONGSON_LPC_IRQ_BASE + 15) =20 #define LOONGSON_CPU_IRQ_BASE 16 -#define LOONGSON_CPU_LAST_IRQ (LOONGSON_CPU_IRQ_BASE + 14) +#define LOONGSON_CPU_LAST_IRQ (LOONGSON_CPU_IRQ_BASE + 15) =20 #define LOONGSON_PCH_IRQ_BASE 64 #define LOONGSON_PCH_ACPI_IRQ (LOONGSON_PCH_IRQ_BASE + 47) @@ -92,15 +103,21 @@ int liointc_acpi_init(struct irq_domain *parent, struct acpi_madt_lio_pic *acpi_liointc); int eiointc_acpi_init(struct irq_domain *parent, struct acpi_madt_eio_pic *acpi_eiointc); +int avecintc_acpi_init(struct irq_domain *parent); + +void complete_irq_moving(void); =20 int htvec_acpi_init(struct irq_domain *parent, struct acpi_madt_ht_pic *acpi_htvec); int pch_lpc_acpi_init(struct irq_domain *parent, struct acpi_madt_lpc_pic *acpi_pchlpc); -int pch_msi_acpi_init(struct irq_domain *parent, - struct acpi_madt_msi_pic *acpi_pchmsi); int pch_pic_acpi_init(struct irq_domain *parent, struct acpi_madt_bio_pic *acpi_pchpic); +int pch_msi_acpi_init(struct irq_domain *parent, + struct acpi_madt_msi_pic *acpi_pchmsi); +int pch_msi_acpi_init_v2(struct irq_domain *parent, + struct acpi_madt_msi_pic *acpi_pchmsi); + int find_pch_pic(u32 gsi); struct fwnode_handle *get_pch_msi_handle(int pci_segment); =20 diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/includ= e/asm/loongarch.h index 04a78010fc725..70834a47257de 100644 --- a/arch/loongarch/include/asm/loongarch.h +++ b/arch/loongarch/include/asm/loongarch.h @@ -253,8 +253,8 @@ #define CSR_ESTAT_EXC_WIDTH 6 #define CSR_ESTAT_EXC (_ULCAST_(0x3f) << CSR_ESTAT_EXC_SHIFT) #define CSR_ESTAT_IS_SHIFT 0 -#define CSR_ESTAT_IS_WIDTH 14 -#define CSR_ESTAT_IS (_ULCAST_(0x3fff) << CSR_ESTAT_IS_SHIFT) +#define CSR_ESTAT_IS_WIDTH 15 +#define CSR_ESTAT_IS (_ULCAST_(0x7fff) << CSR_ESTAT_IS_SHIFT) =20 #define LOONGARCH_CSR_ERA 0x6 /* ERA */ =20 @@ -649,6 +649,13 @@ =20 #define LOONGARCH_CSR_CTAG 0x98 /* TagLo + TagHi */ =20 +#define LOONGARCH_CSR_ISR0 0xa0 +#define LOONGARCH_CSR_ISR1 0xa1 +#define LOONGARCH_CSR_ISR2 0xa2 +#define LOONGARCH_CSR_ISR3 0xa3 + +#define LOONGARCH_CSR_IRR 0xa4 + #define LOONGARCH_CSR_PRID 0xc0 =20 /* Shadow MCSR : 0xc0 ~ 0xff */ @@ -1011,7 +1018,7 @@ /* * CSR_ECFG IM */ -#define ECFG0_IM 0x00001fff +#define ECFG0_IM 0x00005fff #define ECFGB_SIP0 0 #define ECFGF_SIP0 (_ULCAST_(1) << ECFGB_SIP0) #define ECFGB_SIP1 1 @@ -1054,6 +1061,7 @@ #define IOCSRF_EIODECODE BIT_ULL(9) #define IOCSRF_FLATMODE BIT_ULL(10) #define IOCSRF_VM BIT_ULL(11) +#define IOCSRF_AVEC BIT_ULL(15) =20 #define LOONGARCH_IOCSR_VENDOR 0x10 =20 @@ -1065,6 +1073,7 @@ #define IOCSR_MISC_FUNC_SOFT_INT BIT_ULL(10) #define IOCSR_MISC_FUNC_TIMER_RESET BIT_ULL(21) #define IOCSR_MISC_FUNC_EXT_IOI_EN BIT_ULL(48) +#define IOCSR_MISC_FUNC_AVEC_EN BIT_ULL(51) =20 #define LOONGARCH_IOCSR_CPUTEMP 0x428 =20 @@ -1387,9 +1396,10 @@ __BUILD_CSR_OP(tlbidx) #define INT_TI 11 /* Timer */ #define INT_IPI 12 #define INT_NMI 13 +#define INT_AVEC 14 =20 /* ExcCodes corresponding to interrupts */ -#define EXCCODE_INT_NUM (INT_NMI + 1) +#define EXCCODE_INT_NUM (INT_AVEC + 1) #define EXCCODE_INT_START 64 #define EXCCODE_INT_END (EXCCODE_INT_START + EXCCODE_INT_NUM - 1) =20 diff --git a/arch/loongarch/include/asm/smp.h b/arch/loongarch/include/asm/= smp.h index 50db503f44e3c..3383c9d24e942 100644 --- a/arch/loongarch/include/asm/smp.h +++ b/arch/loongarch/include/asm/smp.h @@ -70,10 +70,12 @@ extern int __cpu_logical_map[NR_CPUS]; #define ACTION_RESCHEDULE 1 #define ACTION_CALL_FUNCTION 2 #define ACTION_IRQ_WORK 3 +#define ACTION_CLEAR_VECTOR 4 #define SMP_BOOT_CPU BIT(ACTION_BOOT_CPU) #define SMP_RESCHEDULE BIT(ACTION_RESCHEDULE) #define SMP_CALL_FUNCTION BIT(ACTION_CALL_FUNCTION) #define SMP_IRQ_WORK BIT(ACTION_IRQ_WORK) +#define SMP_CLEAR_VECTOR BIT(ACTION_CLEAR_VECTOR) =20 struct secondary_data { unsigned long stack; diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-= probe.c index 55320813ee081..14f0449f54520 100644 --- a/arch/loongarch/kernel/cpu-probe.c +++ b/arch/loongarch/kernel/cpu-probe.c @@ -106,7 +106,6 @@ static void cpu_probe_common(struct cpuinfo_loongarch *= c) elf_hwcap |=3D HWCAP_LOONGARCH_CRC32; } =20 - config =3D read_cpucfg(LOONGARCH_CPUCFG2); if (config & CPUCFG2_LAM) { c->options |=3D LOONGARCH_CPU_LAM; @@ -174,6 +173,8 @@ static void cpu_probe_common(struct cpuinfo_loongarch *= c) c->options |=3D LOONGARCH_CPU_FLATMODE; if (config & IOCSRF_EIODECODE) c->options |=3D LOONGARCH_CPU_EIODECODE; + if (config & IOCSRF_AVEC) + c->options |=3D LOONGARCH_CPU_AVECINT; if (config & IOCSRF_VM) c->options |=3D LOONGARCH_CPU_HYPERVISOR; =20 diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c index f4991c03514f4..1311546a7b4ee 100644 --- a/arch/loongarch/kernel/irq.c +++ b/arch/loongarch/kernel/irq.c @@ -87,6 +87,18 @@ static void __init init_vec_parent_group(void) acpi_table_parse(ACPI_SIG_MCFG, early_pci_mcfg_parse); } =20 +int __init arch_probe_nr_irqs(void) +{ + int nr_io_pics =3D bitmap_weight(loongson_sysconf.cores_io_master, NR_CPU= S); + + if (!cpu_has_avecint) + nr_irqs =3D (64 + NR_VECTORS * nr_io_pics); + else + nr_irqs =3D (64 + NR_VECTORS * (nr_cpu_ids + nr_io_pics)); + + return NR_IRQS_LEGACY; +} + void __init init_IRQ(void) { int i; @@ -102,7 +114,7 @@ void __init init_IRQ(void) mp_ops.init_ipi(); #endif =20 - for (i =3D 0; i < NR_IRQS; i++) + for (i =3D 0; i < nr_irqs; i++) irq_set_noprobe(i); =20 for_each_possible_cpu(i) { diff --git a/arch/loongarch/kernel/paravirt.c b/arch/loongarch/kernel/parav= irt.c index 9c9b75b76f62f..4d736a4e488dd 100644 --- a/arch/loongarch/kernel/paravirt.c +++ b/arch/loongarch/kernel/paravirt.c @@ -134,6 +134,11 @@ static irqreturn_t pv_ipi_interrupt(int irq, void *dev) info->ipi_irqs[IPI_IRQ_WORK]++; } =20 + if (action & SMP_CLEAR_VECTOR) { + complete_irq_moving(); + info->ipi_irqs[IPI_CLEAR_VECTOR]++; + } + return IRQ_HANDLED; } =20 diff --git a/arch/loongarch/kernel/smp.c b/arch/loongarch/kernel/smp.c index ca405ab86aaef..4adbbef3450ac 100644 --- a/arch/loongarch/kernel/smp.c +++ b/arch/loongarch/kernel/smp.c @@ -72,6 +72,7 @@ static const char *ipi_types[NR_IPI] __tracepoint_string = =3D { [IPI_RESCHEDULE] =3D "Rescheduling interrupts", [IPI_CALL_FUNCTION] =3D "Function call interrupts", [IPI_IRQ_WORK] =3D "IRQ work interrupts", + [IPI_CLEAR_VECTOR] =3D "Clear vector interrupts", }; =20 void show_ipi_list(struct seq_file *p, int prec) @@ -248,6 +249,11 @@ static irqreturn_t loongson_ipi_interrupt(int irq, voi= d *dev) per_cpu(irq_stat, cpu).ipi_irqs[IPI_IRQ_WORK]++; } =20 + if (action & SMP_CLEAR_VECTOR) { + complete_irq_moving(); + per_cpu(irq_stat, cpu).ipi_irqs[IPI_CLEAR_VECTOR]++; + } + return IRQ_HANDLED; } =20 diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 15635812b2d66..e3679ec2b9f76 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -110,7 +110,7 @@ obj-$(CONFIG_LS1X_IRQ) +=3D irq-ls1x.o obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) +=3D irq-ti-sci-intr.o obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) +=3D irq-ti-sci-inta.o obj-$(CONFIG_TI_PRUSS_INTC) +=3D irq-pruss-intc.o -obj-$(CONFIG_IRQ_LOONGARCH_CPU) +=3D irq-loongarch-cpu.o +obj-$(CONFIG_IRQ_LOONGARCH_CPU) +=3D irq-loongarch-cpu.o irq-loongarch-av= ec.o obj-$(CONFIG_LOONGSON_LIOINTC) +=3D irq-loongson-liointc.o obj-$(CONFIG_LOONGSON_EIOINTC) +=3D irq-loongson-eiointc.o obj-$(CONFIG_LOONGSON_HTPIC) +=3D irq-loongson-htpic.o diff --git a/drivers/irqchip/irq-loongarch-avec.c b/drivers/irqchip/irq-loo= ngarch-avec.c new file mode 100644 index 0000000000000..0033aafeb1ecf --- /dev/null +++ b/drivers/irqchip/irq-loongarch-avec.c @@ -0,0 +1,447 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020-2024 Loongson Technologies, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define VECTORS_PER_REG 64 +#define IRR_VECTOR_MASK 0xffUL +#define IRR_INVALID_MASK 0x80000000UL +#define AVEC_MSG_OFFSET 0x100000 + +static phys_addr_t msi_base_addr; + +#ifdef CONFIG_SMP +struct pending_list { + struct list_head head; +}; + +static struct cpumask intersect_mask; +static DEFINE_PER_CPU(struct pending_list, pending_list); +#endif + +static DEFINE_PER_CPU(struct irq_desc * [NR_VECTORS], irq_map); + +struct avecintc_chip { + struct fwnode_handle *fwnode; + struct irq_domain *domain; + struct irq_matrix *vector_matrix; + raw_spinlock_t lock; +}; + +static struct avecintc_chip loongarch_avec; + +struct avecintc_data { + struct list_head entry; + unsigned int cpu; + unsigned int vec; + unsigned int prev_cpu; + unsigned int prev_vec; + unsigned int moving : 1, + managed : 1; +}; + +static inline void avecintc_ack_irq(struct irq_data *d) +{ +} + +static inline void avecintc_mask_irq(struct irq_data *d) +{ +} + +static inline void avecintc_unmask_irq(struct irq_data *d) +{ +} + +#ifdef CONFIG_SMP +static inline void pending_list_init(int cpu) +{ + struct pending_list *plist =3D per_cpu_ptr(&pending_list, cpu); + + INIT_LIST_HEAD(&plist->head); +} + +static void avecintc_sync(struct avecintc_data *adata) +{ + struct pending_list *plist; + + if (cpu_online(adata->prev_cpu)) { + plist =3D per_cpu_ptr(&pending_list, adata->prev_cpu); + list_add_tail(&adata->entry, &plist->head); + adata->moving =3D 1; + mp_ops.send_ipi_single(adata->prev_cpu, ACTION_CLEAR_VECTOR); + } +} + +static int avecintc_set_affinity(struct irq_data *data, const struct cpuma= sk *dest, + bool force) +{ + unsigned int cpu, ret, vector; + unsigned long flags; + struct avecintc_data *adata; + + raw_spin_lock_irqsave(&loongarch_avec.lock, flags); + adata =3D irq_data_get_irq_chip_data(data); + + if (adata->vec && cpu_online(adata->cpu) && cpumask_test_cpu(adata->cpu, = dest)) { + raw_spin_unlock_irqrestore(&loongarch_avec.lock, flags); + return 0; + } + + if (adata->moving) + return -EBUSY; + + cpumask_and(&intersect_mask, dest, cpu_online_mask); + + ret =3D irq_matrix_alloc(loongarch_avec.vector_matrix, &intersect_mask, f= alse, &cpu); + if (ret < 0) { + raw_spin_unlock_irqrestore(&loongarch_avec.lock, flags); + return ret; + } + + vector =3D ret; + adata->cpu =3D cpu; + adata->vec =3D vector; + per_cpu_ptr(irq_map, adata->cpu)[adata->vec] =3D irq_data_to_desc(data); + avecintc_sync(adata); + + raw_spin_unlock_irqrestore(&loongarch_avec.lock, flags); + irq_data_update_effective_affinity(data, cpumask_of(cpu)); + + return IRQ_SET_MASK_OK; +} + +static int avecintc_cpu_online(unsigned int cpu) +{ + unsigned long flags; + + if (!loongarch_avec.vector_matrix) + return 0; + + raw_spin_lock_irqsave(&loongarch_avec.lock, flags); + + irq_matrix_online(loongarch_avec.vector_matrix); + + pending_list_init(cpu); + + raw_spin_unlock_irqrestore(&loongarch_avec.lock, flags); + + return 0; +} + +static int avecintc_cpu_offline(unsigned int cpu) +{ + unsigned long flags; + struct pending_list *plist =3D per_cpu_ptr(&pending_list, cpu); + + if (!loongarch_avec.vector_matrix) + return 0; + + raw_spin_lock_irqsave(&loongarch_avec.lock, flags); + if (list_empty(&plist->head)) + irq_matrix_offline(loongarch_avec.vector_matrix); + else + pr_warn("CPU#%d advanced vector is busy\n", cpu); + raw_spin_unlock_irqrestore(&loongarch_avec.lock, flags); + + return 0; +} + +void complete_irq_moving(void) +{ + struct pending_list *plist =3D this_cpu_ptr(&pending_list); + struct avecintc_data *adata, *tdata; + int cpu, vector, bias; + uint64_t isr; + + raw_spin_lock(&loongarch_avec.lock); + + list_for_each_entry_safe(adata, tdata, &plist->head, entry) { + cpu =3D adata->prev_cpu; + vector =3D adata->prev_vec; + bias =3D vector / VECTORS_PER_REG; + switch (bias) { + case 0: + isr =3D csr_read64(LOONGARCH_CSR_ISR0); + case 1: + isr =3D csr_read64(LOONGARCH_CSR_ISR1); + case 2: + isr =3D csr_read64(LOONGARCH_CSR_ISR2); + case 3: + isr =3D csr_read64(LOONGARCH_CSR_ISR3); + } + + if (isr & (1UL << (vector % VECTORS_PER_REG))) { + mp_ops.send_ipi_single(cpu, ACTION_CLEAR_VECTOR); + continue; + } + list_del(&adata->entry); + irq_matrix_free(loongarch_avec.vector_matrix, cpu, vector, adata->manage= d); + this_cpu_write(irq_map[vector], NULL); + adata->prev_cpu =3D adata->cpu; + adata->prev_vec =3D adata->vec; + adata->moving =3D 0; + } + + raw_spin_unlock(&loongarch_avec.lock); +} +#endif + +static void avecintc_compose_msi_msg(struct irq_data *d, struct msi_msg *m= sg) +{ + struct avecintc_data *adata; + + adata =3D irq_data_get_irq_chip_data(d); + + msg->address_hi =3D 0x0; + msg->address_lo =3D (msi_base_addr | (adata->vec & 0xff) << 4) | + ((cpu_logical_map(adata->cpu & 0xffff)) << 12); + msg->data =3D 0x0; +} + +static struct irq_chip avec_irq_controller =3D { + .name =3D "AVECINTC", + .irq_ack =3D avecintc_ack_irq, + .irq_mask =3D avecintc_mask_irq, + .irq_unmask =3D avecintc_unmask_irq, +#ifdef CONFIG_SMP + .irq_set_affinity =3D avecintc_set_affinity, +#endif + .irq_compose_msi_msg =3D avecintc_compose_msi_msg, +}; + +static void avecintc_irq_dispatch(struct irq_desc *desc) +{ + unsigned long vector; + struct irq_chip *chip =3D irq_desc_get_chip(desc); + struct irq_desc *d; + + chained_irq_enter(chip, desc); + + while (true) { + vector =3D csr_read64(LOONGARCH_CSR_IRR); + if (vector & IRR_INVALID_MASK) + break; + + vector &=3D IRR_VECTOR_MASK; + + d =3D this_cpu_read(irq_map[vector]); + if (d) + generic_handle_irq_desc(d); + else { + spurious_interrupt(); + pr_warn("Unexpected IRQ occurs on CPU#%d [vector %ld]\n", smp_processor= _id(), vector); + } + } + + chained_irq_exit(chip, desc); +} + +static int avecintc_domain_alloc(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs, void *arg) +{ + unsigned int cpu, i, ret; + unsigned long flags; + struct irq_data *irqd; + struct avecintc_data *adata; + + raw_spin_lock_irqsave(&loongarch_avec.lock, flags); + for (i =3D 0; i < nr_irqs; i++) { + irqd =3D irq_domain_get_irq_data(domain, virq + i); + adata =3D kzalloc(sizeof(*adata), GFP_KERNEL); + if (!adata) { + raw_spin_unlock_irqrestore(&loongarch_avec.lock, flags); + return -ENOMEM; + } + + ret =3D irq_matrix_alloc(loongarch_avec.vector_matrix, cpu_online_mask, = false, &cpu); + if (ret < 0) { + raw_spin_unlock_irqrestore(&loongarch_avec.lock, flags); + return ret; + } + + adata->prev_cpu =3D adata->cpu =3D cpu; + adata->prev_vec =3D adata->vec =3D ret; + adata->managed =3D irqd_affinity_is_managed(irqd); + irq_domain_set_info(domain, virq + i, virq + i, &avec_irq_controller, + adata, handle_edge_irq, NULL, NULL); + adata->moving =3D 0; + irqd_set_single_target(irqd); + irqd_set_affinity_on_activate(irqd); + + per_cpu_ptr(irq_map, adata->cpu)[adata->vec] =3D irq_data_to_desc(irqd); + } + raw_spin_unlock_irqrestore(&loongarch_avec.lock, flags); + + return 0; +} + +static void clear_free_vector(struct irq_data *irqd) +{ + bool managed =3D irqd_affinity_is_managed(irqd); + struct avecintc_data *adata =3D irq_data_get_irq_chip_data(irqd); + + per_cpu(irq_map, adata->cpu)[adata->vec] =3D NULL; + irq_matrix_free(loongarch_avec.vector_matrix, adata->cpu, adata->vec, man= aged); + adata->cpu =3D 0; + adata->vec =3D 0; + +#ifdef CONFIG_SMP + if (!adata->moving) + return; + + per_cpu(irq_map, adata->prev_cpu)[adata->prev_vec] =3D NULL; + irq_matrix_free(loongarch_avec.vector_matrix, + adata->prev_cpu, adata->prev_vec, adata->managed); + adata->moving =3D 0; + adata->prev_vec =3D 0; + adata->prev_cpu =3D 0; + list_del_init(&adata->entry); +#endif +} + +static void avecintc_domain_free(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs) +{ + unsigned int i; + unsigned long flags; + struct irq_data *d; + + raw_spin_lock_irqsave(&loongarch_avec.lock, flags); + for (i =3D 0; i < nr_irqs; i++) { + d =3D irq_domain_get_irq_data(domain, virq + i); + if (d) { + clear_free_vector(d); + irq_domain_reset_irq_data(d); + + } + } + + raw_spin_unlock_irqrestore(&loongarch_avec.lock, flags); +} + +static const struct irq_domain_ops avecintc_domain_ops =3D { + .alloc =3D avecintc_domain_alloc, + .free =3D avecintc_domain_free, +}; + +static int __init irq_matrix_init(void) +{ + int i; + + loongarch_avec.vector_matrix =3D irq_alloc_matrix(NR_VECTORS, 0, NR_VECTO= RS - 1); + if (!loongarch_avec.vector_matrix) + return -ENOMEM; + + for (i =3D 0; i < NR_LEGACY_VECTORS; i++) + irq_matrix_assign_system(loongarch_avec.vector_matrix, i, false); + + irq_matrix_online(loongarch_avec.vector_matrix); + + return 0; +} + +static int __init avecintc_init(struct irq_domain *parent) +{ + int ret, parent_irq; + unsigned long value; + + raw_spin_lock_init(&loongarch_avec.lock); + + loongarch_avec.fwnode =3D irq_domain_alloc_named_fwnode("AVECINTC"); + if (!loongarch_avec.fwnode) { + pr_err("Unable to allocate domain handle\n"); + ret =3D -ENOMEM; + goto out; + } + + loongarch_avec.domain =3D irq_domain_create_tree(loongarch_avec.fwnode, + &avecintc_domain_ops, NULL); + if (!loongarch_avec.domain) { + pr_err("Unable to create IRQ domain\n"); + ret =3D -ENOMEM; + goto out_free_handle; + } + + parent_irq =3D irq_create_mapping(parent, INT_AVEC); + if (!parent_irq) { + pr_err("Failed to mapping hwirq\n"); + ret =3D -EINVAL; + goto out_remove_domain; + } + irq_set_chained_handler_and_data(parent_irq, avecintc_irq_dispatch, NULL); + + ret =3D irq_matrix_init(); + if (ret < 0) { + pr_err("Failed to init irq matrix\n"); + goto out_free_matrix; + } +#ifdef CONFIG_SMP + pending_list_init(0); + ret =3D cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_AVECINTC_STARTING, + "irqchip/loongarch/avecintc:starting", + avecintc_cpu_online, avecintc_cpu_offline); +#endif + value =3D iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC); + value |=3D IOCSR_MISC_FUNC_AVEC_EN; + iocsr_write64(value, LOONGARCH_IOCSR_MISC_FUNC); + + return ret; + +out_free_matrix: + kfree(loongarch_avec.vector_matrix); +out_remove_domain: + irq_domain_remove(loongarch_avec.domain); +out_free_handle: + irq_domain_free_fwnode(loongarch_avec.fwnode); +out: + return ret; +} + +static int __init pch_msi_parse_madt(union acpi_subtable_headers *header, + const unsigned long end) +{ + struct acpi_madt_msi_pic *pchmsi_entry =3D (struct acpi_madt_msi_pic *)he= ader; + + msi_base_addr =3D pchmsi_entry->msg_address - AVEC_MSG_OFFSET; + + return pch_msi_acpi_init_v2(loongarch_avec.domain, pchmsi_entry); +} + +static inline int __init acpi_cascade_irqdomain_init(void) +{ + return acpi_table_parse_madt(ACPI_MADT_TYPE_MSI_PIC, pch_msi_parse_madt, = 1); +} + +int __init avecintc_acpi_init(struct irq_domain *parent) +{ + int ret; + + ret =3D avecintc_init(parent); + if (ret < 0) { + pr_err("Failed to init IRQ domain\n"); + return ret; + } + + ret =3D acpi_cascade_irqdomain_init(); + if (ret < 0) { + pr_err("Failed to init cascade IRQ domain\n"); + return ret; + } + + return ret; +} diff --git a/drivers/irqchip/irq-loongarch-cpu.c b/drivers/irqchip/irq-loon= garch-cpu.c index b35903a06902f..808d241c481fb 100644 --- a/drivers/irqchip/irq-loongarch-cpu.c +++ b/drivers/irqchip/irq-loongarch-cpu.c @@ -140,7 +140,10 @@ static int __init acpi_cascade_irqdomain_init(void) if (r < 0) return r; =20 - return 0; + if (cpu_has_avecint) + r =3D avecintc_acpi_init(irq_domain); + + return r; } =20 static int __init cpuintc_acpi_init(union acpi_subtable_headers *header, diff --git a/drivers/irqchip/irq-loongson-eiointc.c b/drivers/irqchip/irq-l= oongson-eiointc.c index b1f2080be2beb..895d15b96669e 100644 --- a/drivers/irqchip/irq-loongson-eiointc.c +++ b/drivers/irqchip/irq-loongson-eiointc.c @@ -360,6 +360,9 @@ static int __init acpi_cascade_irqdomain_init(void) if (r < 0) return r; =20 + if (cpu_has_avecint) + return 0; + r =3D acpi_table_parse_madt(ACPI_MADT_TYPE_MSI_PIC, pch_msi_parse_madt, 1= ); if (r < 0) return r; @@ -396,8 +399,8 @@ static int __init eiointc_init(struct eiointc_priv *pri= v, int parent_irq, =20 if (nr_pics =3D=3D 1) { register_syscore_ops(&eiointc_syscore_ops); - cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_LOONGARCH_STARTING, - "irqchip/loongarch/intc:starting", + cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_EIOINTC_STARTING, + "irqchip/loongarch/eiointc:starting", eiointc_router_init, NULL); } =20 diff --git a/drivers/irqchip/irq-loongson-pch-msi.c b/drivers/irqchip/irq-l= oongson-pch-msi.c index dd4d699170f4e..e4c22c239628e 100644 --- a/drivers/irqchip/irq-loongson-pch-msi.c +++ b/drivers/irqchip/irq-loongson-pch-msi.c @@ -268,11 +268,14 @@ struct fwnode_handle *get_pch_msi_handle(int pci_segm= ent) { int i; =20 + if (cpu_has_avecint) + return pch_msi_handle[0]; + for (i =3D 0; i < MAX_IO_PICS; i++) { if (msi_group[i].pci_segment =3D=3D pci_segment) return pch_msi_handle[i]; } - return NULL; + return pch_msi_handle[0]; } =20 int __init pch_msi_acpi_init(struct irq_domain *parent, @@ -289,4 +292,40 @@ int __init pch_msi_acpi_init(struct irq_domain *parent, =20 return ret; } + +static struct irq_chip pch_msi_irq_chip_v2 =3D { + .name =3D "PCH PCI MSI", + .irq_ack =3D irq_chip_ack_parent, +}; + +static struct msi_domain_info pch_msi_domain_info_v2 =3D { + .flags =3D MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX, + .chip =3D &pch_msi_irq_chip_v2, +}; + +int __init pch_msi_acpi_init_v2(struct irq_domain *parent, + struct acpi_madt_msi_pic *acpi_pchmsi) +{ + struct irq_domain *msi_domain; + + if (pch_msi_handle[0]) + return 0; + + pch_msi_handle[0] =3D irq_domain_alloc_fwnode(&acpi_pchmsi->msg_address); + if (!pch_msi_handle[0]) { + pr_err("Unable to allocate domain handle\n"); + return -ENOMEM; + } + + msi_domain =3D pci_msi_create_irq_domain(pch_msi_handle[0], + &pch_msi_domain_info_v2, parent); + if (!msi_domain) { + pr_err("Failed to create PCI MSI domain\n"); + kfree(pch_msi_handle[0]); + return -ENOMEM; + } + + return 0; +} #endif diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index 89f5c34ce4df9..287605bd5d4a7 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -144,7 +144,8 @@ enum cpuhp_state { CPUHP_AP_IRQ_ARMADA_XP_STARTING, CPUHP_AP_IRQ_BCM2836_STARTING, CPUHP_AP_IRQ_MIPS_GIC_STARTING, - CPUHP_AP_IRQ_LOONGARCH_STARTING, + CPUHP_AP_IRQ_EIOINTC_STARTING, + CPUHP_AP_IRQ_AVECINTC_STARTING, CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, CPUHP_AP_IRQ_RISCV_IMSIC_STARTING, CPUHP_AP_ARM_MVEBU_COHERENCY,