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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7a9f816db18sm2049645a12.33.2024.07.26.01.49.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jul 2024 01:49:45 -0700 (PDT) From: Yong-Xuan Wang To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, Yong-Xuan Wang , Jinyu Tang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrew Jones , Anup Patel , Conor Dooley , Mayuresh Chitale , Atish Patra , Samuel Ortiz , Daniel Henrique Barboza , Samuel Holland , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Evan Green , Andy Chiu , Xiao Wang , Alexandre Ghiti , Andrew Morton , David Hildenbrand , Kemeng Shi , Charlie Jenkins , Peter Xu , "Matthew Wilcox (Oracle)" , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Leonardo Bras Subject: [PATCH v8 1/5] RISC-V: Add Svade and Svadu Extensions Support Date: Fri, 26 Jul 2024 16:49:26 +0800 Message-Id: <20240726084931.28924-2-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240726084931.28924-1-yongxuan.wang@sifive.com> References: <20240726084931.28924-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Svade and Svadu extensions represent two schemes for managing the PTE A/D bits. When the PTE A/D bits need to be set, Svade extension intdicates that a related page fault will be raised. In contrast, the Svadu extension supports hardware updating of PTE A/D bits. Since the Svade extension is mandatory and the Svadu extension is optional in RVA23 profile, by default the M-mode firmware will enable the Svadu extension in the menvcfg CSR when only Svadu is present in DT. This patch detects Svade and Svadu extensions from DT and adds arch_has_hw_pte_young() to enable optimization in MGLRU and __wp_page_copy_user() when we have the PTE A/D bits hardware updating support. Co-developed-by: Jinyu Tang Signed-off-by: Jinyu Tang Signed-off-by: Yong-Xuan Wang Reviewed-by: Andrew Jones Reviewed-by: Alexandre Ghiti Acked-by: Palmer Dabbelt --- arch/riscv/Kconfig | 1 + arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/include/asm/pgtable.h | 13 ++++++++++++- arch/riscv/kernel/cpufeature.c | 12 ++++++++++++ 5 files changed, 28 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 3ceec2ca84fa..014e512854a6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -29,6 +29,7 @@ config RISCV select ARCH_HAS_FORTIFY_SOURCE select ARCH_HAS_GCOV_PROFILE_ALL select ARCH_HAS_GIGANTIC_PAGE + select ARCH_HAS_HW_PTE_YOUNG select ARCH_HAS_KCOV select ARCH_HAS_KERNEL_FPU_SUPPORT if 64BIT && FPU select ARCH_HAS_MEMBARRIER_CALLBACKS diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 25966995da04..524cd4131c71 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -195,6 +195,7 @@ /* xENVCFG flags */ #define ENVCFG_STCE (_AC(1, ULL) << 63) #define ENVCFG_PBMTE (_AC(1, ULL) << 62) +#define ENVCFG_ADUE (_AC(1, ULL) << 61) #define ENVCFG_CBZE (_AC(1, UL) << 7) #define ENVCFG_CBCFE (_AC(1, UL) << 6) #define ENVCFG_CBIE_SHIFT 4 diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index b18b202ca141..b0435fda09ae 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -93,6 +93,8 @@ #define RISCV_ISA_EXT_ZCF 84 #define RISCV_ISA_EXT_ZCMOP 85 #define RISCV_ISA_EXT_ZAWRS 86 +#define RISCV_ISA_EXT_SVADE 87 +#define RISCV_ISA_EXT_SVADU 88 =20 #define RISCV_ISA_EXT_XLINUXENVCFG 127 =20 diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgta= ble.h index 089f3c9f56a3..6f1a0534f319 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -120,6 +120,7 @@ #include #include #include +#include =20 #define __page_val_to_pfn(_val) (((_val) & _PAGE_PFN_MASK) >> _PAGE_PFN_S= HIFT) =20 @@ -288,7 +289,6 @@ static inline pte_t pud_pte(pud_t pud) } =20 #ifdef CONFIG_RISCV_ISA_SVNAPOT -#include =20 static __always_inline bool has_svnapot(void) { @@ -649,6 +649,17 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _p= rot) return __pgprot(prot); } =20 +/* + * Both Svade and Svadu control the hardware behavior when the PTE A/D bit= s need to be set. By + * default the M-mode firmware enables the hardware updating scheme when o= nly Svadu is present in + * DT. + */ +#define arch_has_hw_pte_young arch_has_hw_pte_young +static inline bool arch_has_hw_pte_young(void) +{ + return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU); +} + /* * THP functions */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 0366dc3baf33..2a9cdfae21c6 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -156,6 +156,16 @@ static int riscv_ext_zcf_validate(const struct riscv_i= sa_ext_data *data, return -EPROBE_DEFER; } =20 +static int riscv_ext_svadu_validate(const struct riscv_isa_ext_data *data, + const unsigned long *isa_bitmap) +{ + /* SVADE has already been detected, use SVADE only */ + if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_SVADE)) + return -EOPNOTSUPP; + + return 0; +} + static const unsigned int riscv_zk_bundled_exts[] =3D { RISCV_ISA_EXT_ZBKB, RISCV_ISA_EXT_ZBKC, @@ -402,6 +412,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), + __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE), + __RISCV_ISA_EXT_DATA_VALIDATE(svadu, RISCV_ISA_EXT_SVADU, riscv_ext_svadu= _validate), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), --=20 2.17.1 From nobody Fri Oct 18 08:36:31 2024 Received: from mail-oo1-f50.google.com (mail-oo1-f50.google.com [209.85.161.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E644178375 for ; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7a9f816db18sm2049645a12.33.2024.07.26.01.49.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jul 2024 01:49:50 -0700 (PDT) From: Yong-Xuan Wang To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, Yong-Xuan Wang , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , devicetree@vger.kernel.org Subject: [PATCH v8 2/5] dt-bindings: riscv: Add Svade and Svadu Entries Date: Fri, 26 Jul 2024 16:49:27 +0800 Message-Id: <20240726084931.28924-3-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240726084931.28924-1-yongxuan.wang@sifive.com> References: <20240726084931.28924-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add entries for the Svade and Svadu extensions to the riscv,isa-extensions property. Signed-off-by: Yong-Xuan Wang Acked-by: Conor Dooley Reviewed-by: Alexandre Ghiti Reviewed-by: Samuel Holland Acked-by: Palmer Dabbelt --- .../devicetree/bindings/riscv/extensions.yaml | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index a06dbc6b4928..b3885756766d 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -153,6 +153,34 @@ properties: ratified at commit 3f9ed34 ("Add ability to manually trigger workflow. (#2)") of riscv-time-compare. =20 + - const: svade + description: | + The standard Svade supervisor-level extension for SW-managed P= TE A/D + bit updates as ratified in the 20240213 version of the privile= ged + ISA specification. + + Both Svade and Svadu extensions control the hardware behavior = when + the PTE A/D bits need to be set. The default behavior for the = four + possible combinations of these extensions in the device tree a= re: + 1) Neither Svade nor Svadu present in DT =3D> It is technically + unknown whether the platform uses Svade or Svadu. Supervisor + software should be prepared to handle either hardware updat= ing + of the PTE A/D bits or page faults when they need updated. + 2) Only Svade present in DT =3D> Supervisor must assume Svade = to be + always enabled. + 3) Only Svadu present in DT =3D> Supervisor must assume Svadu = to be + always enabled. + 4) Both Svade and Svadu present in DT =3D> Supervisor must ass= ume + Svadu turned-off at boot time. To use Svadu, supervisor must + explicitly enable it using the SBI FWFT extension. + + - const: svadu + description: | + The standard Svadu supervisor-level extension for hardware upd= ating + of PTE A/D bits as ratified in the 20240528 version of the + privileged ISA specification. Please refer to Svade dt-binding + description for more details. + - const: svinval description: The standard Svinval supervisor-level extension for fine-grain= ed --=20 2.17.1 From nobody Fri Oct 18 08:36:31 2024 Received: from mail-pg1-f173.google.com (mail-pg1-f173.google.com [209.85.215.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 670CF17839F for ; Fri, 26 Jul 2024 08:49:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721983796; cv=none; b=RIHJA0dPZXh3OGdX5yQfvGzTxiT5E1a8JhLUK4+KhtHJsUDO2Bz2o9dy4Bvakw7JH/oNV5rq4wFrAPUkB3q1CEkXIz3kJdBq4N2qKxIwfbOm70q0NbkGxv/FO2DDgq/ujmJ6XWp8w6Itg9V/JtjnfoZJRh2o4M754jb7KwYlO+k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721983796; c=relaxed/simple; bh=DIBSkAyKBd3D8uYoYD7uVG9VrUtkXQY9MnQFWDRTPX4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=eNmufCwJsxhgxMr+1IPUt7edmY11M21RB7ykBMgcNp6HX8PuhFGPFbLtOZfH5xfCq/28rLC3pNt0emhjBKksY8KwKU9iYXlsO/iQmdrN0GdU0K8eaXlw7GuFHw0xJzC8J6SUCxxiPtGNGm15rY98G2nnfPwiNK5bAZbYAaLH8vA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=IlSpURJy; arc=none smtp.client-ip=209.85.215.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="IlSpURJy" Received: by mail-pg1-f173.google.com with SMTP id 41be03b00d2f7-656d8b346d2so528377a12.2 for ; Fri, 26 Jul 2024 01:49:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1721983794; x=1722588594; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=34BL/sh0DZ6mInNrtxWV/KGc2m1HMCFv7aaLw74E+qY=; b=IlSpURJyAtcHFgWLVIfGCB8ky6Zm27p+rHywQi4d3D2HyRNab5Hutyuqs4dTPhvFp2 oyOiQ20qeyUolVdf9pfnJMdfIPptoTZ1/B8+K5JmDKOSGGAmV3FeZyQjgxk1yTbervcM cTecCpq0RMoq54BK9J9GezPjpsug2gekqwSJoyjQWr1W0STI5Vumv8jQis/+hzt53Kty tt/iwgVsTL3St0BACmLTFzKy4Rx6QAnLLhT39smIY6btD8Lh2w6SVDRwLOLrAAj0awcF RF1B2e2kCRxuao/QH0TLCk4+ZwoZI3T15/FPROPm44pJohf4mXq9MtkoCPUNuG9IgpPP vaeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721983794; x=1722588594; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=34BL/sh0DZ6mInNrtxWV/KGc2m1HMCFv7aaLw74E+qY=; b=aDATSbCX+d1vn9Li4XrS2x/mDD7nwaS8PfmZQfl/BL9wryNqhMYyab3EwYCjjGDYtD GkZlfPONrjFnGOulFwjJleh7RCOEH3ZZ/yArWuJIlSkNt+vbK4Lz2CeWnyEvZVWZeLaN viuCICQ7ti1yQTP+tGxeD059otC1bUjq38X0/mQkqQayrq/cIFsMtKsxlV6sS6Xoh1MT 5wvejTfHZJ4BSGp5maLTLI+ykTyTe/TRaYbdxJgxie20POsIDjq3UOJqdZbk0UERgJTr tHoyKYNdmZ/P+dMjx1xrX9C5bzPYXS0iEYdGWh7VLzvUWLD8Z9bc5JvuX+9n4Koemrnk hvRQ== X-Gm-Message-State: AOJu0YwPuqOJ7RrMT4soVq3H/7Z+zlGZ6MWoMHab40XgwMeUl2qiew7u iUFyDnT77/6mI+1+T5S87iGSsy0HIq7qV97EFCYpXPrZHnkSyTWKGgiVSPY3XdKivbktLTmSnEb DyIjb4bK1YOy+99a/pAWhN3G4Tzo9fcQ86ttVyX3Jgv6YIRkugC+5ssJPX+1e+v6dOGZlaZhBKo EChzIA/wAFh5embqmdS9G1vfL467yw35XKiRqexHL2bCh9XRL9fNRA8Q== X-Google-Smtp-Source: AGHT+IEsc2Lj8N3rTxeNWx9ih1V5tMTbZiHBB2CSobNOVFD8y6Tw1gE2nmjH3/iQ9cJEnLEnKggdVw== X-Received: by 2002:a05:6a20:a115:b0:1c2:8904:14c2 with SMTP id adf61e73a8af0-1c47b2d151amr5398963637.37.1721983794278; Fri, 26 Jul 2024 01:49:54 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7a9f816db18sm2049645a12.33.2024.07.26.01.49.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jul 2024 01:49:54 -0700 (PDT) From: Yong-Xuan Wang To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, Yong-Xuan Wang , Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou Subject: [PATCH v8 3/5] RISC-V: KVM: Add Svade and Svadu Extensions Support for Guest/VM Date: Fri, 26 Jul 2024 16:49:28 +0800 Message-Id: <20240726084931.28924-4-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240726084931.28924-1-yongxuan.wang@sifive.com> References: <20240726084931.28924-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We extend the KVM ISA extension ONE_REG interface to allow VMM tools to detect and enable Svade and Svadu extensions for Guest/VM. Since the henvcfg.ADUE is read-only zero if the menvcfg.ADUE is zero, the Svadu extension is available for Guest/VM and the Svade extension is allowed to disabledonly when arch_has_hw_pte_young() is true. Signed-off-by: Yong-Xuan Wang Reviewed-by: Andrew Jones Reviewed-by: Samuel Holland Acked-by: Palmer Dabbelt --- arch/riscv/include/uapi/asm/kvm.h | 2 ++ arch/riscv/kvm/vcpu.c | 4 ++++ arch/riscv/kvm/vcpu_onereg.c | 15 +++++++++++++++ 3 files changed, 21 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index e97db3296456..85bbc472989d 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -175,6 +175,8 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZCF, KVM_RISCV_ISA_EXT_ZCMOP, KVM_RISCV_ISA_EXT_ZAWRS, + KVM_RISCV_ISA_EXT_SVADE, + KVM_RISCV_ISA_EXT_SVADU, KVM_RISCV_ISA_EXT_MAX, }; =20 diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 8d7d381737ee..c78061a6d68b 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -544,6 +544,10 @@ static void kvm_riscv_vcpu_setup_config(struct kvm_vcp= u *vcpu) if (riscv_isa_extension_available(isa, ZICBOZ)) cfg->henvcfg |=3D ENVCFG_CBZE; =20 + if (riscv_isa_extension_available(isa, SVADU) && + !riscv_isa_extension_available(isa, SVADE)) + cfg->henvcfg |=3D ENVCFG_ADUE; + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) { cfg->hstateen0 |=3D SMSTATEEN0_HSENVCFG; if (riscv_isa_extension_available(isa, SSAIA)) diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index b319c4c13c54..b3f58908902a 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -15,6 +15,7 @@ #include #include #include +#include #include =20 #define KVM_RISCV_BASE_ISA_MASK GENMASK(25, 0) @@ -38,6 +39,8 @@ static const unsigned long kvm_isa_ext_arr[] =3D { KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSCOFPMF), KVM_ISA_EXT_ARR(SSTC), + KVM_ISA_EXT_ARR(SVADE), + KVM_ISA_EXT_ARR(SVADU), KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), KVM_ISA_EXT_ARR(SVPBMT), @@ -110,6 +113,12 @@ static bool kvm_riscv_vcpu_isa_enable_allowed(unsigned= long ext) case KVM_RISCV_ISA_EXT_SSCOFPMF: /* Sscofpmf depends on interrupt filtering defined in ssaia */ return __riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSAIA); + case KVM_RISCV_ISA_EXT_SVADU: + /* + * The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero. + * Guest OS can use Svadu only when host OS enable Svadu. + */ + return arch_has_hw_pte_young(); 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7a9f816db18sm2049645a12.33.2024.07.26.01.49.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jul 2024 01:49:58 -0700 (PDT) From: Yong-Xuan Wang To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, Yong-Xuan Wang , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan , Paul Walmsley , Palmer Dabbelt , Albert Ou , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , linux-kselftest@vger.kernel.org Subject: [PATCH v8 4/5] KVM: riscv: selftests: Fix compile error Date: Fri, 26 Jul 2024 16:49:29 +0800 Message-Id: <20240726084931.28924-5-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240726084931.28924-1-yongxuan.wang@sifive.com> References: <20240726084931.28924-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Fix compile error introduced by commit d27c34a73514 ("KVM: riscv: selftests: Add some Zc* extensions to get-reg-list test"). These 4 lines should be end with ";". Fixes: d27c34a73514 ("KVM: riscv: selftests: Add some Zc* extensions to get= -reg-list test") Signed-off-by: Yong-Xuan Wang Acked-by: Palmer Dabbelt Reviewed-by: Cl=C3=A9ment L=C3=A9ger --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testi= ng/selftests/kvm/riscv/get-reg-list.c index f92c2fb23fcd..8e34f7fa44e9 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -961,10 +961,10 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zbkb, ZBKB); KVM_ISA_EXT_SIMPLE_CONFIG(zbkc, ZBKC); KVM_ISA_EXT_SIMPLE_CONFIG(zbkx, ZBKX); KVM_ISA_EXT_SIMPLE_CONFIG(zbs, ZBS); -KVM_ISA_EXT_SIMPLE_CONFIG(zca, ZCA), -KVM_ISA_EXT_SIMPLE_CONFIG(zcb, ZCB), -KVM_ISA_EXT_SIMPLE_CONFIG(zcd, ZCD), -KVM_ISA_EXT_SIMPLE_CONFIG(zcf, ZCF), +KVM_ISA_EXT_SIMPLE_CONFIG(zca, ZCA); +KVM_ISA_EXT_SIMPLE_CONFIG(zcb, ZCB); +KVM_ISA_EXT_SIMPLE_CONFIG(zcd, ZCD); +KVM_ISA_EXT_SIMPLE_CONFIG(zcf, ZCF); KVM_ISA_EXT_SIMPLE_CONFIG(zcmop, ZCMOP); KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA); KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH); --=20 2.17.1 From nobody Fri Oct 18 08:36:31 2024 Received: from mail-il1-f179.google.com (mail-il1-f179.google.com [209.85.166.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0A171779A9 for ; Fri, 26 Jul 2024 08:50:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.166.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721983805; cv=none; b=FGoeAWS4E0uMr65p/Pmo/CciLQAYQrFGNbK3GTIdGcuGABAt8j9gWeByVkI7FllrxRQ04e5oXC9kaRaSPpfn+EwwDwIcuKHoFk/lyyCUK7ZiMZYVreMrh8+/oQEzt2LmpIB+lKzLlAdCMUPtdSAcWd/lRSNlruGWf7fgodwYxrc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721983805; c=relaxed/simple; bh=4H9XgVVG6KE+T4f63WGdvgt8zwDFpGPootH+0VeKvxw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=Zs1E6H5oZjn8i0vW9UZulPGnFLexwfWv7XdaSKX+bPhS1RlwLszePwOvDTxFB6k0g8mF94wQrPcYeR0Y429/oaDGiqK0mkBU5dkWv9deu4RgbPVUW6TF8t7kkMNWEbgShAT0mZD3TEhZ1SdZvxcQpAZkkr4EQHGRZb/QwSI5Ip8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=KoMRq+5l; arc=none smtp.client-ip=209.85.166.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="KoMRq+5l" Received: by mail-il1-f179.google.com with SMTP id e9e14a558f8ab-396e2d21812so5765835ab.2 for ; Fri, 26 Jul 2024 01:50:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1721983803; x=1722588603; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=Bh0dPmnNd790JEXkCnnwPZ9r1VDA3UO+2QohszDGqoo=; b=KoMRq+5lPnFFuYAKSjnc+Wqmva1825wGQFI42L8cnHb6au2dt4KKI/ExvkBgzB3yuI ghGGhGszQ6X61Cndo0NrJ4p95G3vHVLPuoyPfJqwMRdlnjWiQdspHvItUqEPim+zH5XH Zl2Wth25tKU0d5Orj0dKK5a7VEmlfWjuWIXgTjvTjWr91F+KBk3gz/7mGHZqx6BCoDjT isEY0YRKrYTY/cLkR9NfqfF8Ky1vFWUTlDab6Ieo00c4QOyQo4S7kNvU+WJOT13G3smL hVmzOkqkeERNCAweuA3ce7X6SnfUC1KdB0QzKxc1ov0zAvmqN9J6PnckmzOjRJh9ynHq FRag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721983803; x=1722588603; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Bh0dPmnNd790JEXkCnnwPZ9r1VDA3UO+2QohszDGqoo=; b=qZ2puwGL3/5FYHMGJ1Hk9TaS80Od/cjDFrFBgJJgadQv3yUF3en57rosgagknqkcg1 gOoaGUGFyouP20JUUqivlS63uMfGV04d6MEEj68ML9wXYbXCr2q376OwAnqnjH3GbUV8 3lPPJrOCEQOjYKsMxvaBdkbU2iQTGd5BhjpyxSJAWEaSqv7b25UbVnynaRH5sysHmSec RRzb2I+8wm6kiDhUnjwIoz9A4gtjwew2HS8ZGEKpgaOVxLaGdajLG5VKqJ7T7DeFz0Qk NWy6QkikvjsofhqU5E8FSzk6iKrAjP1eJobb6iODsINaLlkF24Rb4kYg2LSUCuT+z9w/ 5kcA== X-Gm-Message-State: AOJu0YzjSpSHwry/FVpGRntmxionidgebkhUUuqXU7FSyLLanrP/Dbg8 0XA+gSFGZ64iSUZ6PMGfTSvxrBMDlxSeQjJd1CIpMjFgb9mrCxjCgpR98hJjvo9vmIcF4BgRqbj /lWUcRznV+dqFepYPaeVXqwbnz4CClnGgFmYstJ98d7zXkPCeHPP/3Yq5YiMRQVh+7LCoapEpT9 If5O8AQ2q7yPw407MDoKz43hXp0yXl/Y/2hC3FAAS8J06j7FFEc6KmZw== X-Google-Smtp-Source: AGHT+IEC0sacpJpGdjediwFUkg9JGJyg+dOU1D2hf0SgxjyukSNI0E33M4o24q3PFduqql67IyeZjQ== X-Received: by 2002:a05:6e02:2162:b0:374:9c67:1df6 with SMTP id e9e14a558f8ab-39a21814055mr55639775ab.22.1721983802742; Fri, 26 Jul 2024 01:50:02 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7a9f816db18sm2049645a12.33.2024.07.26.01.50.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jul 2024 01:50:02 -0700 (PDT) From: Yong-Xuan Wang To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, Yong-Xuan Wang , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-kselftest@vger.kernel.org Subject: [PATCH v8 5/5] KVM: riscv: selftests: Add Svade and Svadu Extension to get-reg-list test Date: Fri, 26 Jul 2024 16:49:30 +0800 Message-Id: <20240726084931.28924-6-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240726084931.28924-1-yongxuan.wang@sifive.com> References: <20240726084931.28924-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Update the get-reg-list test to test the Svade and Svadu Extensions are available for guest OS. Signed-off-by: Yong-Xuan Wang Reviewed-by: Andrew Jones Acked-by: Palmer Dabbelt --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testi= ng/selftests/kvm/riscv/get-reg-list.c index 8e34f7fa44e9..aac40652e181 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -45,6 +45,8 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SSAIA: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SSCOFPMF: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SSTC: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SVADE: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SVADU: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SVINVAL: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SVNAPOT: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SVPBMT: @@ -418,6 +420,8 @@ static const char *isa_ext_single_id_to_str(__u64 reg_o= ff) KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSCOFPMF), KVM_ISA_EXT_ARR(SSTC), + KVM_ISA_EXT_ARR(SVADE), + KVM_ISA_EXT_ARR(SVADU), KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), KVM_ISA_EXT_ARR(SVPBMT), @@ -949,6 +953,8 @@ KVM_ISA_EXT_SIMPLE_CONFIG(h, H); KVM_ISA_EXT_SUBLIST_CONFIG(smstateen, SMSTATEEN); KVM_ISA_EXT_SIMPLE_CONFIG(sscofpmf, SSCOFPMF); KVM_ISA_EXT_SIMPLE_CONFIG(sstc, SSTC); +KVM_ISA_EXT_SIMPLE_CONFIG(svade, SVADE); +KVM_ISA_EXT_SIMPLE_CONFIG(svadu, SVADU); KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL); KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT); KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT); @@ -1012,6 +1018,8 @@ struct vcpu_reg_list *vcpu_configs[] =3D { &config_smstateen, &config_sscofpmf, &config_sstc, + &config_svade, + &config_svadu, &config_svinval, &config_svnapot, &config_svpbmt, --=20 2.17.1