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Fri, 26 Jul 2024 01:09:20 -0700 (PDT) Received: from [127.0.1.1] ([82.79.124.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427f93e6883sm105939045e9.37.2024.07.26.01.09.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jul 2024 01:09:20 -0700 (PDT) From: Abel Vesa Date: Fri, 26 Jul 2024 11:09:14 +0300 Subject: [PATCH] phy: qcom: qmp-pcie: Configure all tables on port B PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240726-phy-qcom-qmp-pcie-write-all-tbls-second-port-v1-1-751b9ee01184@linaro.org> X-B4-Tracking: v=1; b=H4sIAKlZo2YC/x3NQQ6CMBBG4auQWTsJNirEqxgX0P6VSUpb2gYhh LvbuPw27x2UkQSZns1BCatkCb7iemlIT4P/gMVUk2rVre3UneO086LDzMscOWoBf5MU8OAcl9F lztDBG44hFe5hoWH67jFaqsmYYGX7717v8/wBUxbgnn4AAAA= To: Vinod Koul , Kishon Vijay Abraham I Cc: Johan Hovold , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Qiang Yu , Abel Vesa X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE From: Qiang Yu Currently, only the RX and TX tables are written to the second PHY (port B) when the 4-lanes mode is configured, but according to Qualcomm internal documentation, the pcs, pcs_misc, serdes and ln_shrd tables need to be written as well. Signed-off-by: Qiang Yu Signed-off-by: Abel Vesa --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index 5b36cc7ac78b..fd59ebd32f5f 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -3660,18 +3660,30 @@ static void qmp_pcie_init_port_b(struct qmp_pcie *q= mp, const struct qmp_phy_cfg_ { const struct qmp_phy_cfg *cfg =3D qmp->cfg; const struct qmp_pcie_offsets *offs =3D cfg->offsets; - void __iomem *tx3, *rx3, *tx4, *rx4; + void __iomem *tx3, *rx3, *tx4, *rx4, *pcs, *pcs_misc, *ln_shrd, *serdes; =20 tx3 =3D qmp->port_b + offs->tx; rx3 =3D qmp->port_b + offs->rx; tx4 =3D qmp->port_b + offs->tx2; rx4 =3D qmp->port_b + offs->rx2; + serdes =3D qmp->port_b + offs->serdes; + pcs =3D qmp->port_b + offs->pcs; + pcs_misc =3D qmp->port_b + offs->pcs_misc; + ln_shrd =3D qmp->port_b + offs->ln_shrd; =20 qmp_configure_lane(tx3, tbls->tx, tbls->tx_num, 1); qmp_configure_lane(rx3, tbls->rx, tbls->rx_num, 1); =20 qmp_configure_lane(tx4, tbls->tx, tbls->tx_num, 2); qmp_configure_lane(rx4, tbls->rx, tbls->rx_num, 2); + + qmp_configure(serdes, tbls->serdes, tbls->serdes_num); + qmp_configure(serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num); + + qmp_configure(pcs, tbls->pcs, tbls->pcs_num); + qmp_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); + + qmp_configure(ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); } =20 static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp= _phy_cfg_tbls *tbls) --- base-commit: 864b1099d16fc7e332c3ad7823058c65f890486c change-id: 20240725-phy-qcom-qmp-pcie-write-all-tbls-second-port-8efeced876= bf Best regards, --=20 Abel Vesa