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[2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-36b367c0338sm5500985f8f.1.2024.07.26.08.20.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jul 2024 08:20:17 -0700 (PDT) From: Julien Stephan Date: Fri, 26 Jul 2024 17:20:06 +0200 Subject: [PATCH 1/5] dt-bindings: iio: adc: ad7380: add single-ended compatible parts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240726-ad7380-add-single-ended-chips-v1-1-2d628b60ccd1@baylibre.com> References: <20240726-ad7380-add-single-ended-chips-v1-0-2d628b60ccd1@baylibre.com> In-Reply-To: <20240726-ad7380-add-single-ended-chips-v1-0-2d628b60ccd1@baylibre.com> To: Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Lars-Peter Clausen , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Cc: Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Julien Stephan X-Mailer: b4 0.13.0 Adding ad7386/7/8 single-ended compatible parts, and the corresponding ad7386-4/7-4/8-4 4 channels. Signed-off-by: Julien Stephan Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml | 13 +++++++++++= ++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7380.yaml index 899b777017ce..bd19abb867d9 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml @@ -15,10 +15,17 @@ description: | * https://www.analog.com/en/products/ad7381.html * https://www.analog.com/en/products/ad7383.html * https://www.analog.com/en/products/ad7384.html + * https://www.analog.com/en/products/ad7386.html + * https://www.analog.com/en/products/ad7387.html + * https://www.analog.com/en/products/ad7388.html * https://www.analog.com/en/products/ad7380-4.html * https://www.analog.com/en/products/ad7381-4.html * https://www.analog.com/en/products/ad7383-4.html * https://www.analog.com/en/products/ad7384-4.html + * https://www.analog.com/en/products/ad7386-4.html + * https://www.analog.com/en/products/ad7387-4.html + * https://www.analog.com/en/products/ad7388-4.html + =20 $ref: /schemas/spi/spi-peripheral-props.yaml# =20 @@ -29,10 +36,16 @@ properties: - adi,ad7381 - adi,ad7383 - adi,ad7384 + - adi,ad7386 + - adi,ad7387 + - adi,ad7388 - adi,ad7380-4 - adi,ad7381-4 - adi,ad7383-4 - adi,ad7384-4 + - adi,ad7386-4 + - adi,ad7387-4 + - adi,ad7388-4 =20 reg: maxItems: 1 --=20 2.45.1 From nobody Mon Sep 16 19:09:03 2024 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8CA8B178CC5 for ; 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[2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-36b367c0338sm5500985f8f.1.2024.07.26.08.20.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jul 2024 08:20:18 -0700 (PDT) From: Julien Stephan Date: Fri, 26 Jul 2024 17:20:07 +0200 Subject: [PATCH 2/5] ad7380: prepare driver for single-ended parts support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240726-ad7380-add-single-ended-chips-v1-2-2d628b60ccd1@baylibre.com> References: <20240726-ad7380-add-single-ended-chips-v1-0-2d628b60ccd1@baylibre.com> In-Reply-To: <20240726-ad7380-add-single-ended-chips-v1-0-2d628b60ccd1@baylibre.com> To: Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Lars-Peter Clausen , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Cc: Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Julien Stephan X-Mailer: b4 0.13.0 ad738x family contains single-ended parts that have a 2:1 mux in front of ADC, so the number of IIO channels is different from the number of simultaneous channels that can be sampled. To prepare the support for single-ended parts, introduce a new num_simultaneous_channels variable. For currently supported parts, num_simultaneous_channels is equal to num_channels minus 1 (the timestamps channel) Signed-off-by: Julien Stephan --- drivers/iio/adc/ad7380.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index 7568cd0a2b32..03bbd561fb23 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -80,6 +80,7 @@ struct ad7380_chip_info { const char *name; const struct iio_chan_spec *channels; unsigned int num_channels; + unsigned int num_simult_channels; const char * const *vcm_supplies; unsigned int num_vcm_supplies; const unsigned long *available_scan_masks; @@ -208,6 +209,7 @@ static const struct ad7380_chip_info ad7380_chip_info = =3D { .name =3D "ad7380", .channels =3D ad7380_channels, .num_channels =3D ARRAY_SIZE(ad7380_channels), + .num_simult_channels =3D 2, .available_scan_masks =3D ad7380_2_channel_scan_masks, .timing_specs =3D &ad7380_timing, }; @@ -216,6 +218,7 @@ static const struct ad7380_chip_info ad7381_chip_info = =3D { .name =3D "ad7381", .channels =3D ad7381_channels, .num_channels =3D ARRAY_SIZE(ad7381_channels), + .num_simult_channels =3D 2, .available_scan_masks =3D ad7380_2_channel_scan_masks, .timing_specs =3D &ad7380_timing, }; @@ -224,6 +227,7 @@ static const struct ad7380_chip_info ad7383_chip_info = =3D { .name =3D "ad7383", .channels =3D ad7383_channels, .num_channels =3D ARRAY_SIZE(ad7383_channels), + .num_simult_channels =3D 2, .vcm_supplies =3D ad7380_2_channel_vcm_supplies, .num_vcm_supplies =3D ARRAY_SIZE(ad7380_2_channel_vcm_supplies), .available_scan_masks =3D ad7380_2_channel_scan_masks, @@ -234,6 +238,7 @@ static const struct ad7380_chip_info ad7384_chip_info = =3D { .name =3D "ad7384", .channels =3D ad7384_channels, .num_channels =3D ARRAY_SIZE(ad7384_channels), + .num_simult_channels =3D 2, .vcm_supplies =3D ad7380_2_channel_vcm_supplies, .num_vcm_supplies =3D ARRAY_SIZE(ad7380_2_channel_vcm_supplies), .available_scan_masks =3D ad7380_2_channel_scan_masks, @@ -244,6 +249,7 @@ static const struct ad7380_chip_info ad7380_4_chip_info= =3D { .name =3D "ad7380-4", .channels =3D ad7380_4_channels, .num_channels =3D ARRAY_SIZE(ad7380_4_channels), + .num_simult_channels =3D 4, .available_scan_masks =3D ad7380_4_channel_scan_masks, .timing_specs =3D &ad7380_4_timing, }; @@ -252,6 +258,7 @@ static const struct ad7380_chip_info ad7381_4_chip_info= =3D { .name =3D "ad7381-4", .channels =3D ad7381_4_channels, .num_channels =3D ARRAY_SIZE(ad7381_4_channels), + .num_simult_channels =3D 4, .available_scan_masks =3D ad7380_4_channel_scan_masks, .timing_specs =3D &ad7380_4_timing, }; @@ -260,6 +267,7 @@ static const struct ad7380_chip_info ad7383_4_chip_info= =3D { .name =3D "ad7383-4", .channels =3D ad7383_4_channels, .num_channels =3D ARRAY_SIZE(ad7383_4_channels), + .num_simult_channels =3D 4, .vcm_supplies =3D ad7380_4_channel_vcm_supplies, .num_vcm_supplies =3D ARRAY_SIZE(ad7380_4_channel_vcm_supplies), .available_scan_masks =3D ad7380_4_channel_scan_masks, @@ -270,6 +278,7 @@ static const struct ad7380_chip_info ad7384_4_chip_info= =3D { .name =3D "ad7384-4", .channels =3D ad7384_4_channels, .num_channels =3D ARRAY_SIZE(ad7384_4_channels), + .num_simult_channels =3D 4, .vcm_supplies =3D ad7380_4_channel_vcm_supplies, .num_vcm_supplies =3D ARRAY_SIZE(ad7380_4_channel_vcm_supplies), .available_scan_masks =3D ad7380_4_channel_scan_masks, @@ -407,7 +416,7 @@ static void ad7380_update_xfers(struct ad7380_state *st, */ st->xfer[1].bits_per_word =3D scan_type->realbits; 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[2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-36b367c0338sm5500985f8f.1.2024.07.26.08.20.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jul 2024 08:20:19 -0700 (PDT) From: Julien Stephan Date: Fri, 26 Jul 2024 17:20:08 +0200 Subject: [PATCH 3/5] ad7380: add support for single-ended parts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240726-ad7380-add-single-ended-chips-v1-3-2d628b60ccd1@baylibre.com> References: <20240726-ad7380-add-single-ended-chips-v1-0-2d628b60ccd1@baylibre.com> In-Reply-To: <20240726-ad7380-add-single-ended-chips-v1-0-2d628b60ccd1@baylibre.com> To: Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Lars-Peter Clausen , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Cc: Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Julien Stephan X-Mailer: b4 0.13.0 Adding ad7386/7/8 (16/14/12 bits) unsigned, dual simultaneous sampling, single-ended compatible parts, and the corresponding ad7386-4/7-4/8-4 4 channels. These parts have a 2:1 multiplexer in front of each ADC. They also include additional configuration registers that allow for either manual selection or automatic switching (sequencer mode), of the multiplexer inputs. This commit focus on integrating manual selection. Sequencer mode will be implemented later. From an IIO point of view, all inputs are exported, i.e ad7386/7/8 export 4 channels and ad7386-4/7-4/8-4 export 8 channels. Inputs AinX0 of multiplexers correspond to the first half of IIO channels (i.e 0-1 or 0-3) and inputs AinX1 correspond to second half (i.e 2-3 or 4-7). Example for AD7386/7/8 (2 channels parts): IIO | AD7386/7/8 | +---------------------------- | | _____ ______ | | | | | | voltage0 | AinA0 --|--->| | | | | | | mux |----->| ADCA |--- voltage2 | AinA1 --|--->| | | | | | |_____| |_____ | | | _____ ______ | | | | | | voltage1 | AinB0 --|--->| | | | | | | mux |----->| ADCB |--- voltage3 | AinB1 --|--->| | | | | | |_____| |______| | | | +---------------------------- When switching channel, the ADC require an additional settling time. According to the datasheet, data is valid on the third CS low. We already have an extra toggle before each read (either direct reads or buffered reads) to sample correct data, so we just add a single CS toggle at the end of the register write. Signed-off-by: Julien Stephan --- drivers/iio/adc/ad7380.c | 352 +++++++++++++++++++++++++++++++++++++++++--= ---- 1 file changed, 310 insertions(+), 42 deletions(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index 03bbd561fb23..25d42fff1839 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -8,9 +8,11 @@ * Datasheets of supported parts: * ad7380/1 : https://www.analog.com/media/en/technical-documentation/data= -sheets/AD7380-7381.pdf * ad7383/4 : https://www.analog.com/media/en/technical-documentation/data= -sheets/ad7383-7384.pdf + * ad7386/7/8 : https://www.analog.com/media/en/technical-documentation/da= ta-sheets/AD7386-7387-7388.pdf * ad7380-4 : https://www.analog.com/media/en/technical-documentation/data= -sheets/ad7380-4.pdf * ad7381-4 : https://www.analog.com/media/en/technical-documentation/data= -sheets/ad7381-4.pdf * ad7383/4-4 : https://www.analog.com/media/en/technical-documentation/da= ta-sheets/ad7383-4-ad7384-4.pdf + * ad7386/7/8-4 : https://www.analog.com/media/en/technical-documentation/= data-sheets/ad7386-4-7387-4-7388-4.pdf */ =20 #include @@ -49,6 +51,7 @@ #define AD7380_REG_ADDR_ALERT_LOW_TH 0x4 #define AD7380_REG_ADDR_ALERT_HIGH_TH 0x5 =20 +#define AD7380_CONFIG1_CH BIT(11) #define AD7380_CONFIG1_OS_MODE BIT(9) #define AD7380_CONFIG1_OSR GENMASK(8, 6) #define AD7380_CONFIG1_CRC_W BIT(5) @@ -81,6 +84,7 @@ struct ad7380_chip_info { const struct iio_chan_spec *channels; unsigned int num_channels; unsigned int num_simult_channels; + bool has_mux; const char * const *vcm_supplies; unsigned int num_vcm_supplies; const unsigned long *available_scan_masks; @@ -92,8 +96,24 @@ enum { AD7380_SCAN_TYPE_RESOLUTION_BOOST, }; =20 -/* Extended scan types for 14-bit chips. */ -static const struct iio_scan_type ad7380_scan_type_14[] =3D { +/* Extended scan types for 12-bit unsigned chips. */ +static const struct iio_scan_type ad7380_scan_type_12_u[] =3D { + [AD7380_SCAN_TYPE_NORMAL] =3D { + .sign =3D 'u', + .realbits =3D 12, + .storagebits =3D 16, + .endianness =3D IIO_CPU + }, + [AD7380_SCAN_TYPE_RESOLUTION_BOOST] =3D { + .sign =3D 'u', + .realbits =3D 14, + .storagebits =3D 16, + .endianness =3D IIO_CPU + }, +}; + +/* Extended scan types for 14-bit signed chips. */ +static const struct iio_scan_type ad7380_scan_type_14_s[] =3D { [AD7380_SCAN_TYPE_NORMAL] =3D { .sign =3D 's', .realbits =3D 14, @@ -108,8 +128,24 @@ static const struct iio_scan_type ad7380_scan_type_14[= ] =3D { }, }; =20 -/* Extended scan types for 16-bit chips. */ -static const struct iio_scan_type ad7380_scan_type_16[] =3D { +/* Extended scan types for 14-bit unsigned chips. */ +static const struct iio_scan_type ad7380_scan_type_14_u[] =3D { + [AD7380_SCAN_TYPE_NORMAL] =3D { + .sign =3D 'u', + .realbits =3D 14, + .storagebits =3D 16, + .endianness =3D IIO_CPU + }, + [AD7380_SCAN_TYPE_RESOLUTION_BOOST] =3D { + .sign =3D 'u', + .realbits =3D 16, + .storagebits =3D 16, + .endianness =3D IIO_CPU + }, +}; + +/* Extended scan types for 16-bit signed_chips. */ +static const struct iio_scan_type ad7380_scan_type_16_s[] =3D { [AD7380_SCAN_TYPE_NORMAL] =3D { .sign =3D 's', .realbits =3D 16, @@ -124,50 +160,87 @@ static const struct iio_scan_type ad7380_scan_type_16= [] =3D { }, }; =20 -#define AD7380_CHANNEL(index, bits, diff) { \ - .type =3D IIO_VOLTAGE, \ - .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ - ((diff) ? 0 : BIT(IIO_CHAN_INFO_OFFSET)), \ - .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE) | \ - BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ - .info_mask_shared_by_type_available =3D \ - BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ - .indexed =3D 1, \ - .differential =3D (diff), \ - .channel =3D (diff) ? (2 * (index)) : (index), \ - .channel2 =3D (diff) ? (2 * (index) + 1) : 0, \ - .scan_index =3D (index), \ - .has_ext_scan_type =3D 1, \ - .ext_scan_type =3D ad7380_scan_type_##bits, \ - .num_ext_scan_type =3D ARRAY_SIZE(ad7380_scan_type_##bits),\ +/* Extended scan types for 16-bit unsigned chips. */ +static const struct iio_scan_type ad7380_scan_type_16_u[] =3D { + [AD7380_SCAN_TYPE_NORMAL] =3D { + .sign =3D 'u', + .realbits =3D 16, + .storagebits =3D 16, + .endianness =3D IIO_CPU + }, + [AD7380_SCAN_TYPE_RESOLUTION_BOOST] =3D { + .sign =3D 'u', + .realbits =3D 18, + .storagebits =3D 32, + .endianness =3D IIO_CPU + }, +}; + +#define AD7380_CHANNEL(index, bits, diff, sign) { \ + .type =3D IIO_VOLTAGE, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ + ((diff) ? 0 : BIT(IIO_CHAN_INFO_OFFSET)), \ + .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .info_mask_shared_by_type_available =3D \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .indexed =3D 1, \ + .differential =3D (diff), \ + .channel =3D (diff) ? (2 * (index)) : (index), \ + .channel2 =3D (diff) ? (2 * (index) + 1) : 0, \ + .scan_index =3D (index), \ + .has_ext_scan_type =3D 1, \ + .ext_scan_type =3D ad7380_scan_type_##bits##_##sign, \ + .num_ext_scan_type =3D ARRAY_SIZE(ad7380_scan_type_##bits##_##sign), \ } =20 -#define DEFINE_AD7380_2_CHANNEL(name, bits, diff) \ +#define DEFINE_AD7380_2_CHANNEL(name, bits, diff, sign) \ static const struct iio_chan_spec name[] =3D { \ - AD7380_CHANNEL(0, bits, diff), \ - AD7380_CHANNEL(1, bits, diff), \ + AD7380_CHANNEL(0, bits, diff, sign), \ + AD7380_CHANNEL(1, bits, diff, sign), \ IIO_CHAN_SOFT_TIMESTAMP(2), \ } =20 -#define DEFINE_AD7380_4_CHANNEL(name, bits, diff) \ +#define DEFINE_AD7380_4_CHANNEL(name, bits, diff, sign) \ static const struct iio_chan_spec name[] =3D { \ - AD7380_CHANNEL(0, bits, diff), \ - AD7380_CHANNEL(1, bits, diff), \ - AD7380_CHANNEL(2, bits, diff), \ - AD7380_CHANNEL(3, bits, diff), \ + AD7380_CHANNEL(0, bits, diff, sign), \ + AD7380_CHANNEL(1, bits, diff, sign), \ + AD7380_CHANNEL(2, bits, diff, sign), \ + AD7380_CHANNEL(3, bits, diff, sign), \ IIO_CHAN_SOFT_TIMESTAMP(4), \ } =20 +#define DEFINE_AD7380_8_CHANNEL(name, bits, diff, sign) \ +static const struct iio_chan_spec name[] =3D { \ + AD7380_CHANNEL(0, bits, diff, sign), \ + AD7380_CHANNEL(1, bits, diff, sign), \ + AD7380_CHANNEL(2, bits, diff, sign), \ + AD7380_CHANNEL(3, bits, diff, sign), \ + AD7380_CHANNEL(4, bits, diff, sign), \ + AD7380_CHANNEL(5, bits, diff, sign), \ + AD7380_CHANNEL(6, bits, diff, sign), \ + AD7380_CHANNEL(7, bits, diff, sign), \ + IIO_CHAN_SOFT_TIMESTAMP(8), \ +} + /* fully differential */ -DEFINE_AD7380_2_CHANNEL(ad7380_channels, 16, 1); -DEFINE_AD7380_2_CHANNEL(ad7381_channels, 14, 1); -DEFINE_AD7380_4_CHANNEL(ad7380_4_channels, 16, 1); -DEFINE_AD7380_4_CHANNEL(ad7381_4_channels, 14, 1); +DEFINE_AD7380_2_CHANNEL(ad7380_channels, 16, 1, s); +DEFINE_AD7380_2_CHANNEL(ad7381_channels, 14, 1, s); +DEFINE_AD7380_4_CHANNEL(ad7380_4_channels, 16, 1, s); +DEFINE_AD7380_4_CHANNEL(ad7381_4_channels, 14, 1, s); /* pseudo differential */ -DEFINE_AD7380_2_CHANNEL(ad7383_channels, 16, 0); -DEFINE_AD7380_2_CHANNEL(ad7384_channels, 14, 0); -DEFINE_AD7380_4_CHANNEL(ad7383_4_channels, 16, 0); -DEFINE_AD7380_4_CHANNEL(ad7384_4_channels, 14, 0); +DEFINE_AD7380_2_CHANNEL(ad7383_channels, 16, 0, s); +DEFINE_AD7380_2_CHANNEL(ad7384_channels, 14, 0, s); +DEFINE_AD7380_4_CHANNEL(ad7383_4_channels, 16, 0, s); +DEFINE_AD7380_4_CHANNEL(ad7384_4_channels, 14, 0, s); + +/* Single ended */ +DEFINE_AD7380_4_CHANNEL(ad7386_channels, 16, 0, u); +DEFINE_AD7380_4_CHANNEL(ad7387_channels, 14, 0, u); +DEFINE_AD7380_4_CHANNEL(ad7388_channels, 12, 0, u); +DEFINE_AD7380_8_CHANNEL(ad7386_4_channels, 16, 0, u); +DEFINE_AD7380_8_CHANNEL(ad7387_4_channels, 14, 0, u); +DEFINE_AD7380_8_CHANNEL(ad7388_4_channels, 12, 0, u); =20 static const char * const ad7380_2_channel_vcm_supplies[] =3D { "aina", "ainb", @@ -188,6 +261,48 @@ static const unsigned long ad7380_4_channel_scan_masks= [] =3D { 0 }; =20 +/* + * Single ended parts have a 2:1 multiplexer in front of each ADC. + * + * From an IIO point of view, all inputs are exported, i.e ad7386/7/8 + * export 4 channels and ad7386-4/7-4/8-4 export 8 channels. + * + * Inputs AinX0 of multiplexers correspond to the first half of IIO channe= ls + * (i.e 0-1 or 0-3) and inputs AinX1 correspond to second half (i.e 2-3 or + * 4-7). Example for AD7386/7/8 (2 channels parts): + * + * IIO | AD7386/7/8 + * | +---------------------------- + * | | _____ ______ + * | | | | | | + * voltage0 | AinA0 --|--->| | | | + * | | | mux |----->| ADCA |--- + * voltage2 | AinA1 --|--->| | | | + * | | |_____| |_____ | + * | | _____ ______ + * | | | | | | + * voltage1 | AinB0 --|--->| | | | + * | | | mux |----->| ADCB |--- + * voltage3 | AinB1 --|--->| | | | + * | | |_____| |______| + * | | + * | +---------------------------- + * + * Since this is simultaneous sampling for AinX0 OR AinX1 we have two sepa= rate + * scan masks. + */ +static const unsigned long ad7380_2x2_channel_scan_masks[] =3D { + GENMASK(1, 0), + GENMASK(3, 2), + 0 +}; + +static const unsigned long ad7380_2x4_channel_scan_masks[] =3D { + GENMASK(3, 0), + GENMASK(7, 4), + 0 +}; + static const struct ad7380_timing_specs ad7380_timing =3D { .t_csh_ns =3D 10, }; @@ -245,6 +360,36 @@ static const struct ad7380_chip_info ad7384_chip_info = =3D { .timing_specs =3D &ad7380_timing, }; =20 +static const struct ad7380_chip_info ad7386_chip_info =3D { + .name =3D "ad7386", + .channels =3D ad7386_channels, + .num_channels =3D ARRAY_SIZE(ad7386_channels), + .num_simult_channels =3D 2, + .has_mux =3D true, + .available_scan_masks =3D ad7380_2x2_channel_scan_masks, + .timing_specs =3D &ad7380_timing, +}; + +static const struct ad7380_chip_info ad7387_chip_info =3D { + .name =3D "ad7387", + .channels =3D ad7387_channels, + .num_channels =3D ARRAY_SIZE(ad7387_channels), + .num_simult_channels =3D 2, + .has_mux =3D true, + .available_scan_masks =3D ad7380_2x2_channel_scan_masks, + .timing_specs =3D &ad7380_timing, +}; + +static const struct ad7380_chip_info ad7388_chip_info =3D { + .name =3D "ad7388", + .channels =3D ad7388_channels, + .num_channels =3D ARRAY_SIZE(ad7388_channels), + .num_simult_channels =3D 2, + .has_mux =3D true, + .available_scan_masks =3D ad7380_2x2_channel_scan_masks, + .timing_specs =3D &ad7380_timing, +}; + static const struct ad7380_chip_info ad7380_4_chip_info =3D { .name =3D "ad7380-4", .channels =3D ad7380_4_channels, @@ -285,12 +430,43 @@ static const struct ad7380_chip_info ad7384_4_chip_in= fo =3D { .timing_specs =3D &ad7380_4_timing, }; =20 +static const struct ad7380_chip_info ad7386_4_chip_info =3D { + .name =3D "ad7386-4", + .channels =3D ad7386_4_channels, + .num_channels =3D ARRAY_SIZE(ad7386_4_channels), + .num_simult_channels =3D 4, + .has_mux =3D true, + .available_scan_masks =3D ad7380_2x4_channel_scan_masks, + .timing_specs =3D &ad7380_4_timing, +}; + +static const struct ad7380_chip_info ad7387_4_chip_info =3D { + .name =3D "ad7387-4", + .channels =3D ad7387_4_channels, + .num_channels =3D ARRAY_SIZE(ad7387_4_channels), + .num_simult_channels =3D 4, + .has_mux =3D true, + .available_scan_masks =3D ad7380_2x4_channel_scan_masks, + .timing_specs =3D &ad7380_4_timing, +}; + +static const struct ad7380_chip_info ad7388_4_chip_info =3D { + .name =3D "ad7388-4", + .channels =3D ad7388_4_channels, + .num_channels =3D ARRAY_SIZE(ad7388_4_channels), + .num_simult_channels =3D 4, + .has_mux =3D true, + .available_scan_masks =3D ad7380_2x4_channel_scan_masks, + .timing_specs =3D &ad7380_4_timing, +}; + struct ad7380_state { const struct ad7380_chip_info *chip_info; struct spi_device *spi; struct regmap *regmap; unsigned int oversampling_ratio; bool resolution_boost_enabled; + unsigned int ch; unsigned int vref_mv; unsigned int vcm_mv[MAX_NUM_CHANNELS]; /* xfers, message an buffer for reading sample data */ @@ -388,6 +564,43 @@ static int ad7380_debugfs_reg_access(struct iio_dev *i= ndio_dev, u32 reg, unreachable(); } =20 +/* + * When switching channel, the ADC require an additional settling time. + * According to the datasheet, data is value on the third CS low. We alrea= dy + * have an extra toggle before each read (either direct reads or buffered = reads) + * to sample correct data, so we just add a single CS toggle at the end of= the + * register write. + */ +static int ad7380_set_ch(struct ad7380_state *st, unsigned int ch) +{ + struct spi_transfer xfer =3D { + .delay =3D { + .value =3D T_CONVERT_NS, + .unit =3D SPI_DELAY_UNIT_NSECS, + } + }; + int ret; + + if (st->ch =3D=3D ch) + return 0; + + ret =3D regmap_update_bits(st->regmap, + AD7380_REG_ADDR_CONFIG1, + AD7380_CONFIG1_CH, + FIELD_PREP(AD7380_CONFIG1_CH, ch)); + + if (ret) + return ret; + + st->ch =3D ch; + + if (st->oversampling_ratio > 1) + xfer.delay.value =3D T_CONVERT_0_NS + + T_CONVERT_X_NS * (st->oversampling_ratio - 1); + + return spi_sync_transfer(st->spi, &xfer, 1); +} + /** * ad7380_update_xfers - update the SPI transfers base on the current scan= type * @st: device instance specific state @@ -432,6 +645,25 @@ static int ad7380_triggered_buffer_preenable(struct ii= o_dev *indio_dev) if (IS_ERR(scan_type)) return PTR_ERR(scan_type); =20 + if (st->chip_info->has_mux) { + unsigned int num_simult_channels =3D st->chip_info->num_simult_channels; + unsigned long active_scan_mask =3D *indio_dev->active_scan_mask; + unsigned int ch =3D 0; + int ret; + + /* + * Depending on the requested scan_mask and current state, + * we need to change CH bit to sample correct data. + */ + if (active_scan_mask =3D=3D GENMASK(2 * num_simult_channels - 1, + num_simult_channels)) + ch =3D 1; + + ret =3D ad7380_set_ch(st, ch); + if (ret) + return ret; + } + ad7380_update_xfers(st, scan_type); =20 return spi_optimize_message(st->spi, &st->msg); @@ -474,20 +706,43 @@ static irqreturn_t ad7380_trigger_handler(int irq, vo= id *p) static int ad7380_read_direct(struct ad7380_state *st, unsigned int scan_i= ndex, const struct iio_scan_type *scan_type, int *val) { + unsigned int index =3D scan_index; int ret; =20 + if (st->chip_info->has_mux) { + unsigned int ch =3D 0; + + if (index >=3D st->chip_info->num_simult_channels) { + index -=3D st->chip_info->num_simult_channels; + ch =3D 1; + } + + ret =3D ad7380_set_ch(st, ch); + if (ret) + return ret; + } + ad7380_update_xfers(st, scan_type); =20 ret =3D spi_sync(st->spi, &st->msg); if (ret < 0) return ret; =20 - if (scan_type->storagebits > 16) - *val =3D sign_extend32(*(u32 *)(st->scan_data + 4 * scan_index), - scan_type->realbits - 1); - else - *val =3D sign_extend32(*(u16 *)(st->scan_data + 2 * scan_index), - scan_type->realbits - 1); + if (scan_type->storagebits > 16) { + if (scan_type->sign =3D=3D 's') + *val =3D sign_extend32(*(u32 *)(st->scan_data + 4 * index), + scan_type->realbits - 1); + else + *val =3D *(u32 *)(st->scan_data + 4 * index) & + GENMASK(scan_type->realbits - 1, 0); + } else { + if (scan_type->sign =3D=3D 's') + *val =3D sign_extend32(*(u16 *)(st->scan_data + 2 * index), + scan_type->realbits - 1); + else + *val =3D *(u16 *)(st->scan_data + 2 * index) & + GENMASK(scan_type->realbits - 1, 0); + } =20 return IIO_VAL_INT; } @@ -664,6 +919,7 @@ static int ad7380_init(struct ad7380_state *st, struct = regulator *vref) =20 /* This is the default value after reset. */ st->oversampling_ratio =3D 1; + st->ch =3D 0; =20 /* SPI 1-wire mode */ return regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, @@ -807,10 +1063,16 @@ static const struct of_device_id ad7380_of_match_tab= le[] =3D { { .compatible =3D "adi,ad7381", .data =3D &ad7381_chip_info }, { .compatible =3D "adi,ad7383", .data =3D &ad7383_chip_info }, { .compatible =3D "adi,ad7384", .data =3D &ad7384_chip_info }, + { .compatible =3D "adi,ad7386", .data =3D &ad7386_chip_info }, + { .compatible =3D "adi,ad7387", .data =3D &ad7387_chip_info }, + { .compatible =3D "adi,ad7388", .data =3D &ad7388_chip_info }, { .compatible =3D "adi,ad7380-4", .data =3D &ad7380_4_chip_info }, { .compatible =3D "adi,ad7381-4", .data =3D &ad7381_4_chip_info }, { .compatible =3D "adi,ad7383-4", .data =3D &ad7383_4_chip_info }, { .compatible =3D "adi,ad7384-4", .data =3D &ad7384_4_chip_info }, + { .compatible =3D "adi,ad7386-4", .data =3D &ad7386_4_chip_info }, + { .compatible =3D "adi,ad7387-4", .data =3D &ad7387_4_chip_info }, + { .compatible =3D "adi,ad7388-4", .data =3D &ad7388_4_chip_info }, { } }; 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[2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-36b367c0338sm5500985f8f.1.2024.07.26.08.20.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jul 2024 08:20:20 -0700 (PDT) From: Julien Stephan Date: Fri, 26 Jul 2024 17:20:09 +0200 Subject: [PATCH 4/5] ad7380: enable sequencer for single-ended parts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240726-ad7380-add-single-ended-chips-v1-4-2d628b60ccd1@baylibre.com> References: <20240726-ad7380-add-single-ended-chips-v1-0-2d628b60ccd1@baylibre.com> In-Reply-To: <20240726-ad7380-add-single-ended-chips-v1-0-2d628b60ccd1@baylibre.com> To: Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Lars-Peter Clausen , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Cc: Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Julien Stephan X-Mailer: b4 0.13.0 ad7386/7/8(-4) single-ended parts have a 2:1 mux in front of each ADC. From an IIO point of view, all inputs are exported, i.e ad7386/7/8 export 4 channels and ad7386-4/7-4/8-4 export 8 channels. First inputs of muxes correspond to the first half of IIO channels (i.e 0-1 or 0-3) and second inputs correspond to second half (i.e 2-3 or 4-7) Currently, the driver supports only sampling first half OR second half of the IIO channels. To enable sampling all channels simultaneously, these parts have an internal sequencer that automatically cycle through the mux entries. When enabled, the maximum throughput is divided by two. Moreover, the ADCs need additional settling time, so we add an extra CS toggle to correctly propagate setting, and an additional spi transfer to read the second half. Signed-off-by: Julien Stephan --- drivers/iio/adc/ad7380.c | 164 ++++++++++++++++++++++++++++++++++---------= ---- 1 file changed, 121 insertions(+), 43 deletions(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index 25d42fff1839..11ed010431cf 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -33,7 +33,7 @@ #include #include =20 -#define MAX_NUM_CHANNELS 4 +#define MAX_NUM_CHANNELS 8 /* 2.5V internal reference voltage */ #define AD7380_INTERNAL_REF_MV 2500 =20 @@ -52,6 +52,7 @@ #define AD7380_REG_ADDR_ALERT_HIGH_TH 0x5 =20 #define AD7380_CONFIG1_CH BIT(11) +#define AD7380_CONFIG1_SEQ BIT(10) #define AD7380_CONFIG1_OS_MODE BIT(9) #define AD7380_CONFIG1_OSR GENMASK(8, 6) #define AD7380_CONFIG1_CRC_W BIT(5) @@ -290,16 +291,22 @@ static const unsigned long ad7380_4_channel_scan_mask= s[] =3D { * * Since this is simultaneous sampling for AinX0 OR AinX1 we have two sepa= rate * scan masks. + * When sequencer mode is enabled, chip automatically cycle through + * AinX0 and AinX1 channels. From an IIO point of view, we ca enable all + * channels, at the cost of an extra read, thus dividing the maximum rate = by + * two. */ static const unsigned long ad7380_2x2_channel_scan_masks[] =3D { GENMASK(1, 0), GENMASK(3, 2), + GENMASK(3, 0), 0 }; =20 static const unsigned long ad7380_2x4_channel_scan_masks[] =3D { GENMASK(3, 0), GENMASK(7, 4), + GENMASK(7, 0), 0 }; =20 @@ -467,11 +474,14 @@ struct ad7380_state { unsigned int oversampling_ratio; bool resolution_boost_enabled; unsigned int ch; + bool seq; unsigned int vref_mv; unsigned int vcm_mv[MAX_NUM_CHANNELS]; /* xfers, message an buffer for reading sample data */ - struct spi_transfer xfer[2]; - struct spi_message msg; + struct spi_transfer normal_xfer[2]; + struct spi_message normal_msg; + struct spi_transfer seq_xfer[4]; + struct spi_message seq_msg; /* * DMA (thus cache coherency maintenance) requires the transfer buffers * to live in their own cache lines. @@ -609,33 +619,47 @@ static int ad7380_set_ch(struct ad7380_state *st, uns= igned int ch) static void ad7380_update_xfers(struct ad7380_state *st, const struct iio_scan_type *scan_type) { - /* - * First xfer only triggers conversion and has to be long enough for - * all conversions to complete, which can be multiple conversion in the - * case of oversampling. Technically T_CONVERT_X_NS is lower for some - * chips, but we use the maximum value for simplicity for now. - */ - if (st->oversampling_ratio > 1) - st->xfer[0].delay.value =3D T_CONVERT_0_NS + T_CONVERT_X_NS * - (st->oversampling_ratio - 1); - else - st->xfer[0].delay.value =3D T_CONVERT_NS; - - st->xfer[0].delay.unit =3D SPI_DELAY_UNIT_NSECS; + struct spi_transfer *xfer =3D st->seq ? st->seq_xfer : st->normal_xfer; + unsigned int t_convert =3D T_CONVERT_NS; =20 /* - * Second xfer reads all channels. Data size depends on if resolution - * boost is enabled or not. + * In the case of oversampling, conversion time is higher than in normal + * mode. Technically T_CONVERT_X_NS is lower for some chips, but we use + * the maximum value for simplicity for now. */ - st->xfer[1].bits_per_word =3D scan_type->realbits; - st->xfer[1].len =3D BITS_TO_BYTES(scan_type->storagebits) * - st->chip_info->num_simult_channels; + if (st->oversampling_ratio > 1) + t_convert =3D T_CONVERT_0_NS + T_CONVERT_X_NS * + (st->oversampling_ratio - 1); + + if (st->seq) { + xfer[0].delay.value =3D xfer[1].delay.value =3D t_convert; + xfer[0].delay.unit =3D xfer[1].delay.unit =3D SPI_DELAY_UNIT_NSECS; + xfer[2].bits_per_word =3D xfer[3].bits_per_word =3D + scan_type->realbits; + xfer[2].len =3D xfer[3].len =3D + BITS_TO_BYTES(scan_type->storagebits) * + st->chip_info->num_simult_channels; + xfer[3].rx_buf =3D xfer[2].rx_buf + xfer[2].len; + /* Additional delay required here when oversampling is enabled */ + if (st->oversampling_ratio > 1) + xfer[2].delay.value =3D t_convert; + else + xfer[2].delay.value =3D 0; + xfer[2].delay.unit =3D SPI_DELAY_UNIT_NSECS; + } else { + xfer[0].delay.value =3D t_convert; + xfer[0].delay.unit =3D SPI_DELAY_UNIT_NSECS; + xfer[1].bits_per_word =3D scan_type->realbits; + xfer[1].len =3D BITS_TO_BYTES(scan_type->storagebits) * + st->chip_info->num_simult_channels; + } } =20 static int ad7380_triggered_buffer_preenable(struct iio_dev *indio_dev) { struct ad7380_state *st =3D iio_priv(indio_dev); const struct iio_scan_type *scan_type; + struct spi_message *msg =3D &st->normal_msg; =20 /* * Currently, we always read all channels at the same time. The scan_type @@ -646,34 +670,62 @@ static int ad7380_triggered_buffer_preenable(struct i= io_dev *indio_dev) return PTR_ERR(scan_type); =20 if (st->chip_info->has_mux) { - unsigned int num_simult_channels =3D st->chip_info->num_simult_channels; + unsigned int num_simult_channels =3D + st->chip_info->num_simult_channels; unsigned long active_scan_mask =3D *indio_dev->active_scan_mask; unsigned int ch =3D 0; int ret; =20 /* * Depending on the requested scan_mask and current state, - * we need to change CH bit to sample correct data. + * we need to either change CH bit, or enable sequencer mode + * to sample correct data. + * Sequencer mode is enabled if active mask corresponds to all + * IIO channels enabled. Otherwise, CH bit is set. */ - if (active_scan_mask =3D=3D GENMASK(2 * num_simult_channels - 1, - num_simult_channels)) - ch =3D 1; + if (active_scan_mask =3D=3D GENMASK(2 * num_simult_channels - 1, 0)) { + ret =3D regmap_update_bits(st->regmap, + AD7380_REG_ADDR_CONFIG1, + AD7380_CONFIG1_SEQ, + FIELD_PREP(AD7380_CONFIG1_SEQ, 1)); + msg =3D &st->seq_msg; + st->seq =3D true; + } else { + if (active_scan_mask =3D=3D GENMASK(2 * num_simult_channels - 1, + num_simult_channels)) + ch =3D 1; + + ret =3D ad7380_set_ch(st, ch); + } =20 - ret =3D ad7380_set_ch(st, ch); if (ret) return ret; } =20 ad7380_update_xfers(st, scan_type); =20 - return spi_optimize_message(st->spi, &st->msg); + return spi_optimize_message(st->spi, msg); } =20 static int ad7380_triggered_buffer_postdisable(struct iio_dev *indio_dev) { struct ad7380_state *st =3D iio_priv(indio_dev); + struct spi_message *msg =3D &st->normal_msg; + int ret; + + if (st->seq) { + ret =3D regmap_update_bits(st->regmap, + AD7380_REG_ADDR_CONFIG1, + AD7380_CONFIG1_SEQ, + FIELD_PREP(AD7380_CONFIG1_SEQ, 0)); + if (ret) + return ret; + + msg =3D &st->seq_msg; + st->seq =3D false; + } =20 - spi_unoptimize_message(&st->msg); + spi_unoptimize_message(msg); =20 return 0; } @@ -688,9 +740,10 @@ static irqreturn_t ad7380_trigger_handler(int irq, voi= d *p) struct iio_poll_func *pf =3D p; struct iio_dev *indio_dev =3D pf->indio_dev; struct ad7380_state *st =3D iio_priv(indio_dev); + struct spi_message *msg =3D st->seq ? &st->seq_msg : &st->normal_msg; int ret; =20 - ret =3D spi_sync(st->spi, &st->msg); + ret =3D spi_sync(st->spi, msg); if (ret) goto out; =20 @@ -724,7 +777,7 @@ static int ad7380_read_direct(struct ad7380_state *st, = unsigned int scan_index, =20 ad7380_update_xfers(st, scan_type); =20 - ret =3D spi_sync(st->spi, &st->msg); + ret =3D spi_sync(st->spi, &st->normal_msg); if (ret < 0) return ret; =20 @@ -920,6 +973,7 @@ static int ad7380_init(struct ad7380_state *st, struct = regulator *vref) /* This is the default value after reset. */ st->oversampling_ratio =3D 1; st->ch =3D 0; + st->seq =3D false; =20 /* SPI 1-wire mode */ return regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, @@ -1021,21 +1075,45 @@ static int ad7380_probe(struct spi_device *spi) "failed to allocate register map\n"); =20 /* - * Setting up a low latency read for getting sample data. Used for both - * direct read an triggered buffer. Additional fields will be set up in - * ad7380_update_xfers() based on the current state of the driver at the - * time of the read. + * Setting up xfer structures for both normal and sequence mode. These + * struct are used for both direct read and triggered buffer. Additional + * fields will be set up in ad7380_update_xfers() based on the current + * state of the driver at the time of the read. */ =20 - /* toggle CS (no data xfer) to trigger a conversion */ - st->xfer[0].cs_change =3D 1; - st->xfer[0].cs_change_delay.value =3D st->chip_info->timing_specs->t_csh_= ns; - st->xfer[0].cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS; - - /* then do a second xfer to read the data */ - st->xfer[1].rx_buf =3D st->scan_data; + /* + * In normal mode a read is composed of two steps: + * - first, toggle CS (no data xfer) to trigger a conversion + * - then, read data + */ + st->normal_xfer[0].cs_change =3D 1; + st->normal_xfer[0].cs_change_delay.value =3D st->chip_info->timing_specs-= >t_csh_ns; + st->normal_xfer[0].cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS; + st->normal_xfer[1].rx_buf =3D st->scan_data; =20 - spi_message_init_with_transfers(&st->msg, st->xfer, ARRAY_SIZE(st->xfer)); + spi_message_init_with_transfers(&st->normal_msg, st->normal_xfer, + ARRAY_SIZE(st->normal_xfer)); + /* + * In sequencer mode a read is composed of four steps: + * - CS toggle (no data xfer) to get the right point in the sequence + * - CS toggle (no data xfer) to trigger a conversion of AinX0 and + * acquisition of AinX1 + * - 2 data reads, to read AinX0 and AinX1 + */ + st->seq_xfer[0].cs_change =3D 1; + st->seq_xfer[0].cs_change_delay.value =3D st->chip_info->timing_specs->t_= csh_ns; + st->seq_xfer[0].cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS; + st->seq_xfer[1].cs_change =3D 1; + st->seq_xfer[1].cs_change_delay.value =3D st->chip_info->timing_specs->t_= csh_ns; + st->seq_xfer[1].cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS; + + st->seq_xfer[2].rx_buf =3D st->scan_data; + st->seq_xfer[2].cs_change =3D 1; + st->seq_xfer[2].cs_change_delay.value =3D st->chip_info->timing_specs->t_= csh_ns; + st->seq_xfer[2].cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS; + + spi_message_init_with_transfers(&st->seq_msg, st->seq_xfer, + ARRAY_SIZE(st->seq_xfer)); =20 indio_dev->channels =3D st->chip_info->channels; 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[2a02:842a:d52e:6101:6f8f:5617:c4b6:8627]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-36b367c0338sm5500985f8f.1.2024.07.26.08.20.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jul 2024 08:20:21 -0700 (PDT) From: Julien Stephan Date: Fri, 26 Jul 2024 17:20:10 +0200 Subject: [PATCH 5/5] docs: iio: ad7380: add support for single-ended parts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240726-ad7380-add-single-ended-chips-v1-5-2d628b60ccd1@baylibre.com> References: <20240726-ad7380-add-single-ended-chips-v1-0-2d628b60ccd1@baylibre.com> In-Reply-To: <20240726-ad7380-add-single-ended-chips-v1-0-2d628b60ccd1@baylibre.com> To: Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Lars-Peter Clausen , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Cc: Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Julien Stephan X-Mailer: b4 0.13.0 The AD7380 family has some compatible single-ended chips: AD7386/7/8(-4). These single-ended chips have a 2:1 multiplexer in front of each ADC. They also include additional configuration registers that allow for either manual selection or automatic switching (sequencer mode), of the multiplexer inputs. Add a section to describe this. Signed-off-by: Julien Stephan --- Documentation/iio/ad7380.rst | 42 ++++++++++++++++++++++++++++++++++++++++= ++ 1 file changed, 42 insertions(+) diff --git a/Documentation/iio/ad7380.rst b/Documentation/iio/ad7380.rst index 061cd632b5df..81dfa39519fb 100644 --- a/Documentation/iio/ad7380.rst +++ b/Documentation/iio/ad7380.rst @@ -17,10 +17,16 @@ The following chips are supported by this driver: * `AD7381 `_ * `AD7383 `_ * `AD7384 `_ +* `AD7386 `_ +* `AD7387 `_ +* `AD7388 `_ * `AD7380-4 `_ * `AD7381-4 `_ * `AD7383-4 `_ * `AD7384-4 `_ +* `AD7386-4 `_ +* `AD7387-4 `_ +* `AD7388-4 `_ =20 =20 Supported features @@ -69,6 +75,42 @@ must restart iiod using the following command: =20 root:~# systemctl restart iiod =20 +Channel selection and sequencer (single-end chips only) +------------------------------------------------------- + +Single-ended chips of this family (ad7386/7/8(-4)) have a 2:1 multiplexer = in +front of each ADC. They also include additional configuration registers th= at +allow for either manual selection or automatic switching (sequencer mode),= of the +multiplexer inputs. + +From an IIO point of view, all inputs are exported, i.e ad7386/7/8 +export 4 channels and ad7386-4/7-4/8-4 export 8 channels. + +Inputs ``AinX0`` of multiplexers correspond to the first half of IIO chann= els (i.e +0-1 or 0-3) and inputs ``AinX1`` correspond to second half (i.e 2-3 or 4-7= ). +Example for AD7386/7/8 (2 channels parts): + +.. code-block:: + + IIO | AD7386/7/8 + | +---------------------------- + | | _____ ______ + | | | | | | + voltage0 | AinA0 --|--->| | | | + | | | mux |----->| ADCA |--- + voltage2 | AinA1 --|--->| | | | + | | |_____| |_____ | + | | _____ ______ + | | | | | | + voltage1 | AinB0 --|--->| | | | + | | | mux |----->| ADCB |--- + voltage3 | AinB1 --|--->| | | | + | | |_____| |______| + | | + | +---------------------------- + + +When enabling sequencer mode, the effective sampling rate is divided by tw= o. =20 Unimplemented features ---------------------- --=20 2.45.1