From nobody Thu Dec 18 19:25:15 2025 Received: from mail-pg1-f176.google.com (mail-pg1-f176.google.com [209.85.215.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DAC916F826 for ; Wed, 24 Jul 2024 18:36:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721846214; cv=none; b=GnrWUrCOlTDMaNQe2B0asQUbBc+dmC64s8sDU48YrMMC+e85p7qSZWep3xiua79hUmw35HDwtH9YbbdPmPoKSsXXnJBZTa/DQ/MNJuLD09zTsQZ3tsD4+UYRsyFzQ3jKxcZub+swYEpZFNY+cgvyN1naPKaxV7QJ6DJM4rXb8G8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721846214; c=relaxed/simple; bh=a1/mTzZfYWixOKvw7hZJPsNckjOGKvrprzOVGR3f+AI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fbYZ0uXlJ5CYxjcfExINJT2twxT3rLK0gbZ8yReIjjW1aRlybeWdL6agZ/RMqUHpOsyfiR1k3gxAEmIMz05cw7JFXG/UBiiT3O8TYRm4ap2h3oKN8m3i5G+PDVLxgKxjYesyDIczN+mxqaxc2RFdJncqjfKM4Y5Qg1uZv0bcPHg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=qYfacdvw; arc=none smtp.client-ip=209.85.215.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="qYfacdvw" Received: by mail-pg1-f176.google.com with SMTP id 41be03b00d2f7-7a2123e9ad5so864504a12.1 for ; Wed, 24 Jul 2024 11:36:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1721846213; x=1722451013; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EB5PDESy6Qo0Jcu13SGskHFDRhed/H4Oxxes6IQLnyg=; b=qYfacdvwxE87alPlFYRl6yItQaO4caMDifwmP+517389oqUxGCNsdUkE+8JSaN5+C3 wvWGzt7C6TyJDszw1Vd2l8gBjNS+cBO9GXr1yL80nT0sRbc/iC34TW3h1NMBeNzOmFGE Cnjnp7oYXPvxfPiEggxyET+RR/PaKNniMPcOQ7H6I7obUHWBdQ5EGR+o3HG2zLe8ZO71 1bn7dT3XsT4DXRkmCYA9rzt4yly0KkDGleP0QWqU3NoCPhM97UPffFaok4SZgFS4ohPQ TzR/9uHIKCMGSVjyeJh+C2KcBBt5T7UsGQ50auRHwDvizGB7cvo/q0lEUM0dGeJMhVcF DItg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721846213; x=1722451013; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EB5PDESy6Qo0Jcu13SGskHFDRhed/H4Oxxes6IQLnyg=; b=SHhPlwFozHMoESLtYBCKfuxX7Q++1V/ufRGaXgS3Tp6ztRjAWx+ZnZvXu/nFv3Q3cO ywSFsq/kL6U5NOUUXxtWzwZ1djOH2KdmTuP7y1mczdA3AbbUXJVaTC+fngEqAvTJw238 39lKd1X5hfzIbK8DkYGdRYikHPvmcgC71h5IcIK8RyyFzQ5yKy7uQUnBnMbK5pgO/rDQ z2+hN7V6pIHCQQl8vWrHfZBUw+lIhWRgNclXYsIj+ZWRMBNmHLosOQ+802cB94NWtJua oJ8G1Y8GonmYD7Q8hNEkqdE/pZMMSQ6GFrhDw1FBLNJFJY8dM9q9NYXt936Q5bImR+MX J3Ag== X-Forwarded-Encrypted: i=1; AJvYcCU61P4KhQSMAHyDfCLs81MasrygUrEAh9V9Ydi/vIm3XH16Bs48nSI9VLYdEJkGL/W8IrxxspBlPkHjfXd2XUbLDGQucfTMvoaR8R6G X-Gm-Message-State: AOJu0Yxfuzp+055xzCAq+pLNYNQsmFa5gQaA21UgIgj6/DOYO61uEPjF x/hqNFFayOBL/GovqdkthM1b4FvxRkl5wt+C/RGQHXichsKDM+QeyB/E/+KoFy0= X-Google-Smtp-Source: AGHT+IFVaKgpzXil+XU1Q9k4O5zrYBjVM25TgY3w5TlHHmjl9+GYW2Lt07senY0UmNriHZYrgPG/Gw== X-Received: by 2002:a17:90b:1b06:b0:2c2:d6ca:3960 with SMTP id 98e67ed59e1d1-2cf21f48eaamr801050a91.17.1721846212621; Wed, 24 Jul 2024 11:36:52 -0700 (PDT) Received: from jesse-desktop.ba.rivosinc.com (pool-108-26-179-17.bstnma.fios.verizon.net. [108.26.179.17]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2cdb73a189esm1997830a91.2.2024.07.24.11.36.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jul 2024 11:36:51 -0700 (PDT) From: Jesse Taube To: linux-riscv@lists.infradead.org Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Evan Green , Andrew Jones , Jesse Taube , Charlie Jenkins , Xiao Wang , Andy Chiu , Eric Biggers , Greentime Hu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Heiko Stuebner , Costa Shulyupin , Andrew Morton , Baoquan He , Anup Patel , Zong Li , Sami Tolvanen , Ben Dooks , Alexandre Ghiti , "Gustavo A. R. Silva" , Erick Archer , Joel Granados , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 8/8] RISC-V: hwprobe: Document unaligned vector perf key Date: Wed, 24 Jul 2024 14:36:05 -0400 Message-ID: <20240724183605.4038597-9-jesse@rivosinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240724183605.4038597-1-jesse@rivosinc.com> References: <20240724183605.4038597-1-jesse@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document key for reporting the speed of unaligned vector accesses. The descriptions are the same as the scalar equivalent values. Signed-off-by: Jesse Taube Reviewed-by: Charlie Jenkins --- V1 -> V2: - New patch V2 -> V3: - Specify access width V3 -> V4: - Clarify we're talking about byte accesses using vector registers - Spell out _VECTOR_ in macros V4 -> V5: - No changes V5 -> V6: - No changes --- Documentation/arch/riscv/hwprobe.rst | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index 78acd37b6477..f83a13dc4cbc 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -238,3 +238,19 @@ The following keys are defined: =20 * :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which represents the size of the Zicboz block in bytes. + +* :c:macro:`RISCV_HWPROBE_KEY_VECTOR_MISALIGNED_PERF`: An enum value descr= ibing the + performance of misaligned vector accesses on the selected set of proc= essors. + + * :c:macro:`RISCV_HWPROBE_VECTOR_MISALIGNED_UNKNOWN`: The performance of= misaligned + vector accesses is unknown. + + * :c:macro:`RISCV_HWPROBE_VECTOR_MISALIGNED_SLOW`: 32-bit misaligned acc= esses using vector + registers are slower than the equivalent quantity of byte accesses via= vector registers. + Misaligned accesses may be supported directly in hardware, or trapped = and emulated by software. + + * :c:macro:`RISCV_HWPROBE_VECTOR_MISALIGNED_FAST`: 32-bit misaligned acc= esses using vector + registers are faster than the equivalent quantity of byte accesses via= vector registers. + + * :c:macro:`RISCV_HWPROBE_VECTOR_MISALIGNED_UNSUPPORTED`: Misaligned vec= tor accesses are + not supported at all and will generate a misaligned address fault. --=20 2.45.2