From nobody Mon Sep 16 18:54:19 2024 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ECCBE15748D; Tue, 23 Jul 2024 15:16:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=162.243.120.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721747770; cv=none; b=WrqGxDoSNbIuRRAi6M1PvkRGU3xIMKHWJIuDJTUmMuvjLt5iAzZxWlpCOQDWkBHdeikjThWwgTeNCP2AQbzWF3WAaHKQ4DWFu447OdTJipDsK3MDzrm/MvxPWu24IOa/4fNvw1gcQupPuIbGltt+0qd5FWyGkQftHpz38LtBc8A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721747770; c=relaxed/simple; bh=4jfFjzSmJAQ162k5ga/BtjW7bw/StNFGZ2KK7CY8gNk=; h=From:To:Cc:Date:Message-Id:In-Reply-To:References:MIME-Version: Subject; b=BJ84tqFW3MixoV8HQq6jOGSVWKW3XwrLJJPJ2V0O9y5Q6aFoWZMa+uE5pCQ6swkeHdaMFMiWk3zJSaLPfsh2vHWRt7hlgzPeiez5KUXvrcOeKkmDyLaVuVXmBPzHTOnrOpRigFgIAbzmD26O6Y7Elvjvl9V4m1YD34zNgEE5D/0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=hugovil.com; spf=pass smtp.mailfrom=hugovil.com; dkim=pass (1024-bit key) header.d=hugovil.com header.i=@hugovil.com header.b=NfLHNP12; arc=none smtp.client-ip=162.243.120.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=hugovil.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=hugovil.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=hugovil.com header.i=@hugovil.com header.b="NfLHNP12" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:Message-Id:Date:Cc:To :From:subject:date:message-id:reply-to; bh=/Th7PbQe17ZO8imAYvfXDCOwBpwSLlcd+atsqmiSDTI=; b=NfLHNP12RF/tv2A8ie+vd0amY3 DERaaMhrhcYFPb1a3ltUW/1q12tnEuMtfimEw7YCK1bcpFZZ3cx53e4nRUkk/ZtW3VpywebZ2biMd vZZ7uVN3ah33VC6Rovkdr8xlFnGp1L3A+AYq5O6hxa10PE4C4Y0vncXMWzGLZRXnu6AA=; Received: from modemcable061.19-161-184.mc.videotron.ca ([184.161.19.61]:36238 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1sWGwI-0003Y2-FB; Tue, 23 Jul 2024 10:56:30 -0400 From: Hugo Villeneuve To: gregkh@linuxfoundation.org, jirislaby@kernel.org, hvilleneuve@dimonoff.com, jringle@gridpoint.com Cc: linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, hugo@hugovil.com, stable@vger.kernel.org Date: Tue, 23 Jul 2024 08:53:00 -0400 Message-Id: <20240723125302.1305372-2-hugo@hugovil.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240723125302.1305372-1-hugo@hugovil.com> References: <20240723125302.1305372-1-hugo@hugovil.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 184.161.19.61 X-SA-Exim-Mail-From: hugo@hugovil.com X-Spam-Level: X-Spam-Report: * -1.0 ALL_TRUSTED Passed through trusted hosts only via SMTP Subject: [PATCH 1/2] serial: sc16is7xx: fix TX fifo corruption X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve Sometimes, when a packet is received on channel A at almost the same time as a packet is about to be transmitted on channel B, we observe with a logic analyzer that the received packet on channel A is transmitted on channel B. In other words, the Tx buffer data on channel B is corrupted with data from channel A. The problem appeared since commit 4409df5866b7 ("serial: sc16is7xx: change EFR lock to operate on each channels"), which changed the EFR locking to operate on each channel instead of chip-wise. This commit has introduced a regression, because the EFR lock is used not only to protect the EFR registers access, but also, in a very obscure and undocumented way, to protect access to the data buffer, which is shared by the Tx and Rx handlers, but also by each channel of the IC. Fix this regression first by switching to kfifo_out_linear_ptr() in sc16is7xx_handle_tx() to eliminate the need for a shared Rx/Tx buffer. Secondly, replace the chip-wise Rx buffer with a separate Rx buffer for each channel. Fixes: 4409df5866b7 ("serial: sc16is7xx: change EFR lock to operate on each= channels") Cc: Signed-off-by: Hugo Villeneuve --- drivers/tty/serial/sc16is7xx.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c index c79dcd7c8d1a..58696e05492c 100644 --- a/drivers/tty/serial/sc16is7xx.c +++ b/drivers/tty/serial/sc16is7xx.c @@ -327,6 +327,7 @@ struct sc16is7xx_one { struct kthread_work reg_work; struct kthread_delayed_work ms_work; struct sc16is7xx_one_config config; + unsigned char buf[SC16IS7XX_FIFO_SIZE]; /* Rx buffer. */ unsigned int old_mctrl; u8 old_lcr; /* Value before EFR access. */ bool irda_mode; @@ -340,7 +341,6 @@ struct sc16is7xx_port { unsigned long gpio_valid_mask; #endif u8 mctrl_mask; - unsigned char buf[SC16IS7XX_FIFO_SIZE]; struct kthread_worker kworker; struct task_struct *kworker_task; struct sc16is7xx_one p[]; @@ -612,18 +612,18 @@ static int sc16is7xx_set_baud(struct uart_port *port,= int baud) static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen, unsigned int iir) { - struct sc16is7xx_port *s =3D dev_get_drvdata(port->dev); + struct sc16is7xx_one *one =3D to_sc16is7xx_one(port, port); unsigned int lsr =3D 0, bytes_read, i; bool read_lsr =3D (iir =3D=3D SC16IS7XX_IIR_RLSE_SRC) ? true : false; u8 ch, flag; =20 - if (unlikely(rxlen >=3D sizeof(s->buf))) { + if (unlikely(rxlen >=3D sizeof(one->buf))) { dev_warn_ratelimited(port->dev, "ttySC%i: Possible RX FIFO overrun: %d\n", port->line, rxlen); port->icount.buf_overrun++; /* Ensure sanity of RX level */ - rxlen =3D sizeof(s->buf); + rxlen =3D sizeof(one->buf); } =20 while (rxlen) { @@ -636,10 +636,10 @@ static void sc16is7xx_handle_rx(struct uart_port *por= t, unsigned int rxlen, lsr =3D 0; =20 if (read_lsr) { - s->buf[0] =3D sc16is7xx_port_read(port, SC16IS7XX_RHR_REG); + one->buf[0] =3D sc16is7xx_port_read(port, SC16IS7XX_RHR_REG); bytes_read =3D 1; } else { - sc16is7xx_fifo_read(port, s->buf, rxlen); + sc16is7xx_fifo_read(port, one->buf, rxlen); bytes_read =3D rxlen; } =20 @@ -672,7 +672,7 @@ static void sc16is7xx_handle_rx(struct uart_port *port,= unsigned int rxlen, } =20 for (i =3D 0; i < bytes_read; ++i) { - ch =3D s->buf[i]; + ch =3D one->buf[i]; if (uart_handle_sysrq_char(port, ch)) continue; =20 @@ -690,10 +690,10 @@ static void sc16is7xx_handle_rx(struct uart_port *por= t, unsigned int rxlen, =20 static void sc16is7xx_handle_tx(struct uart_port *port) { - struct sc16is7xx_port *s =3D dev_get_drvdata(port->dev); struct tty_port *tport =3D &port->state->port; unsigned long flags; unsigned int txlen; + unsigned char *tail; =20 if (unlikely(port->x_char)) { sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char); @@ -718,8 +718,9 @@ static void sc16is7xx_handle_tx(struct uart_port *port) txlen =3D 0; } =20 - txlen =3D uart_fifo_out(port, s->buf, txlen); - sc16is7xx_fifo_write(port, s->buf, txlen); + txlen =3D kfifo_out_linear_ptr(&tport->xmit_fifo, &tail, txlen); + sc16is7xx_fifo_write(port, tail, txlen); + uart_xmit_advance(port, txlen); =20 uart_port_lock_irqsave(port, &flags); if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) --=20 2.39.2 From nobody Mon Sep 16 18:54:19 2024 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F69E156F4A; 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charset="utf-8" From: Hugo Villeneuve When enabling access to the special register set, Receiver time-out and RHR interrupts can happen. In this case, the IRQ handler will try to read from the FIFO thru the RHR register at address 0x00, but address 0x00 is mapped to DLL register, resulting in erroneous FIFO reading. Call graph example: sc16is7xx_startup(): entry sc16is7xx_ms_proc(): entry sc16is7xx_set_termios(): entry sc16is7xx_set_baud(): DLH/DLL =3D $009C --> access special register set sc16is7xx_port_irq() entry --> IIR is 0x0C sc16is7xx_handle_rx() entry sc16is7xx_fifo_read(): --> unable to access FIFO (RHR) because it is mapped to DLL (LCR=3DLCR_CONF_MODE_A) sc16is7xx_set_baud(): exit --> Restore access to general register set Fix the problem by claiming the efr_lock mutex when accessing the Special register set. Fixes: dfeae619d781 ("serial: sc16is7xx") Cc: Signed-off-by: Hugo Villeneuve --- drivers/tty/serial/sc16is7xx.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c index 58696e05492c..b4c1798a1df2 100644 --- a/drivers/tty/serial/sc16is7xx.c +++ b/drivers/tty/serial/sc16is7xx.c @@ -592,6 +592,8 @@ static int sc16is7xx_set_baud(struct uart_port *port, i= nt baud) SC16IS7XX_MCR_CLKSEL_BIT, prescaler =3D=3D 1 ? 0 : SC16IS7XX_MCR_CLKSEL_BIT); =20 + mutex_lock(&one->efr_lock); + /* Backup LCR and access special register set (DLL/DLH) */ lcr =3D sc16is7xx_port_read(port, SC16IS7XX_LCR_REG); sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, @@ -606,6 +608,8 @@ static int sc16is7xx_set_baud(struct uart_port *port, i= nt baud) /* Restore LCR and access to general register set */ sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); =20 + mutex_unlock(&one->efr_lock); + return DIV_ROUND_CLOSEST((clk / prescaler) / 16, div); } =20 --=20 2.39.2