From nobody Tue Dec 16 19:40:49 2025 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4DE3446A2 for ; Mon, 22 Jul 2024 21:58:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721685495; cv=none; b=PY47sAH4h6Mmt77EdbWs4+nfQ5OOYI9ZW+hTFr10JqcYO3GZh8X+XJZCKQqjYpmQi/3/Kt0nNtC7OY4CqomWRNcx+mMbiUb3dKx6YejRIahwK5V+xdJnd6yVwZ+9v5w1dumyYLWU+AMV9slCjwv2y8UV9m6kE3eyUMJVqvyNLAY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721685495; c=relaxed/simple; bh=ZzH0VgSdYutk/uKY2omj651o9v+E5HP1BijtgXJzAp0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AI6+1lGJFLyC1t63vcqUBBx2/SWdTop08vN3BTOU/l9DaRtgNEH1rSFZTZ1yh52w+I5wv+E2uXGay0c2UaEpuwFC954ufQaYenOuEAmLvWZCvfYphrz+o7WbbldVL2k7az20y8U4onXJ43QA5vSDsrlVA8AcxN2ZUhMNUHCP2YY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=olQnCKl3; arc=none smtp.client-ip=209.85.214.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="olQnCKl3" Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-1fd66cddd4dso1156485ad.2 for ; Mon, 22 Jul 2024 14:58:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1721685493; x=1722290293; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=GWtR9ZjYZiSKNZtqnpkUxp+qNZzbKrCzo+6HVfyCbsc=; b=olQnCKl3AieIkZcrRuaABkl9o11ZO1iHeP5giFbSwwHDnVm6kVT/pkyOZtUGProuMm j2IDkre07igoU1eC2BNPKuZcPN0oJP3a8b8Hy4H/3cwan26/JLHde3vrkOWZga8UpNsC QN0ePW6aFXJv4QW4p9ZLZp3zGupa+G2dRbrHOmTTrilH+p1SedD6GOJ4dAiiRsB1v1Ur EnWkW8nlnGNQvt9eG+Ac6if6d0Bhw9XQo8xIGbiqxCzB5yp6ydrlYbdKfSsXkSmXqLEn Qd6/rV8tfcEs08bP9LncfQ+NTJFrVYfzfjrUgcYhsV/I8VMshQXoERn24nSu+AXLjWXM mQsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721685493; x=1722290293; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GWtR9ZjYZiSKNZtqnpkUxp+qNZzbKrCzo+6HVfyCbsc=; b=vScMrHfb0TZT6PjpZXG0OOLU5zMWFxEpi+DzIDoPUZb7ceMosD5jOWbYGFTIuBFHIU o9lfWd0dEVvL29nX5z3gE9SHCQ4Knu1+B4ixymfqS7A2VDVGhb7cdKhQOV3YqkcjDiIU XKR/w1JjYL+20Rtuf51JEnsR66FZLlfsVHL1DEK3gMD/oe0rrUQP6bF57rjxqr4mjDyz JZD8mvcomdnWaw96PaQezoROpldmxfIOQqkuth35LCLMhLbB3F9Z6gdhl+BpfA8Af8b4 AVxVPSVGGiXJyESJnsx7eTN2V6MpmS3ejTFrEekTjv6KoCmrFWi3gkQ1UPg+NzMip3g3 N6mw== X-Forwarded-Encrypted: i=1; AJvYcCXnna4NhFT1GEsKC/bBdUvrGj9mHRwI2bpXkwttXlw3JIQJeS1JL75CYBpPw2wV2apf3ber4CoMDXxbV2X+O+SoFPLwsSg9UP8AyPyy X-Gm-Message-State: AOJu0Yy9leZWljPqAvBuei21bIEG0X9kC4JIJR/9tnu4UBYRkNZAqBJ4 TtJu53m1kRMlp2yF8Jt3mQDuCU+nJTrp0aho4i3Wu6+zaOk2BMdRlQk3ogVF41Q= X-Google-Smtp-Source: AGHT+IHTkfkTbO9687i4Pn2+RihIVEo5h0oCdzVOneV1P9azYW/tvjOn1QPbNPDGhVqGXxDgJEBHuw== X-Received: by 2002:a17:903:41cc:b0:1fb:7c7f:6447 with SMTP id d9443c01a7336-1fdb5f6b353mr10313025ad.25.1721685493071; Mon, 22 Jul 2024 14:58:13 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fd6f44f0d4sm59997775ad.219.2024.07.22.14.58.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jul 2024 14:58:12 -0700 (PDT) From: Charlie Jenkins Date: Mon, 22 Jul 2024 14:58:05 -0700 Subject: [PATCH v6 01/13] dt-bindings: riscv: Add xtheadvector ISA extension description Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240722-xtheadvector-v6-1-c9af0130fa00@rivosinc.com> References: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com> In-Reply-To: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins , Conor Dooley X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721685488; l=1788; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=ZzH0VgSdYutk/uKY2omj651o9v+E5HP1BijtgXJzAp0=; b=nZEeYwaJqqmvsjfP3STCkMzgTO0YV5QHpTcK9EbgMZdRapnAEgagfXnzOhMbcFXpInDpLxRU4 H+rbxMq8H8mA7REaKmytn+kSbxVFuc5Ssov3TqrIQwafO799xnPzEis X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= The xtheadvector ISA extension is described on the T-Head extension spec Github page [1] at commit 95358cb2cca9. Link: https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9= 489361c61d335e03d3134b14133f/xtheadvector.adoc [1] Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/extensions.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index a06dbc6b4928..1a3d01aedde6 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -556,6 +556,10 @@ properties: latency, as ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. =20 + # vendor extensions, each extension sorted alphanumerically under = the + # vendor they belong to. Vendors are sorted alphanumerically as we= ll. + + # Andes - const: xandespmu description: The Andes Technology performance monitor extension for counter= overflow @@ -563,6 +567,12 @@ properties: Registers in the AX45MP datasheet. https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.= 0.0-Datasheet.pdf =20 + # T-HEAD + - const: xtheadvector + description: + The T-HEAD specific 0.7.1 vector implementation as written in + https://github.com/T-head-Semi/thead-extension-spec/blob/95358= cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc. + allOf: # Zcb depends on Zca - if: --=20 2.44.0 From nobody Tue Dec 16 19:40:49 2025 Received: from mail-pf1-f173.google.com (mail-pf1-f173.google.com [209.85.210.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 253294778E for ; Mon, 22 Jul 2024 21:58:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721685497; cv=none; b=hKsnXbr1WUHurQwbnfU/XofFQsh4PZNabgbSeZ/ZkmUbY1Phw6E4V+XkcmFbEHZullcy735YT8itCC0dmmONQuMz//Pn2mBgfIGQNiQ9sTzFBeZXxcUCH5o2A07zR8uVQKltU/IZoH8cSvqUNsc4QA3FoORroAf9QvvhChuRRC4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721685497; c=relaxed/simple; bh=lK25kSvuXBbjCsm1KOScKY69sa4rMHinL5Ye8aockR0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gwTU0aFIp/1hOPIY3ivxMtG3joEnzllfTMbBFOLlE/LDE62TVnjhZhFuC+K83U7xXD58/DYtw6BahLdhATd+c8C426nCEQ3RAopXE3T8NysCqZ4GblIddPkCnDi4NXrPYSMu0oT3TI7r8UlzaWc3CtzZOEu7EJaeZZPIiR+Rrjc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=hfH7PIMZ; arc=none smtp.client-ip=209.85.210.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="hfH7PIMZ" Received: by mail-pf1-f173.google.com with SMTP id d2e1a72fcca58-70cec4aa1e4so2341174b3a.1 for ; Mon, 22 Jul 2024 14:58:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1721685495; x=1722290295; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=0RiVgzby/fIL0Kxxx3Y50ysZFHbsEJYdDMqDhTheyzc=; b=hfH7PIMZEuSCXYPnzhwdtyJp4+TunM3HOJTj9TxPbkVySPTJwiMt3QH0rlincP6T5c 5ZNdOdcrf+9YRIsFvCm3Ukj8UPd77nk8v969isBDZBWJufLJISpJyiIvAyfyuUcZKZNw SV7TQsdSMxUzB+E4afAMBCC+6XWyfcRZIBaNCh29S2p/1aOa1/lIgn2qiiJUI4ptBn9A EwiseDfYYQ+w9SzNt6X4Z29tyN9RxXhbTpvaOclP5AiiiIxLaWyYnMNFL56sKrc0tTuF a81oSsjdEtADfnnXAcnk7cMFotEfhP+8SWs5+WuBa6DVslEX33tVsR5I6DoXhJUFsqXi hyqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721685495; x=1722290295; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0RiVgzby/fIL0Kxxx3Y50ysZFHbsEJYdDMqDhTheyzc=; b=SRI34fY6tunBrXDD+4Tiz9ZETb4GwUinP+WLJjjS6WkzAmno68m21LKXh4YOMJiURU Z5dLPboCn73c8BsryreCyRNj0tMsyVlAWagcBC5PkaHQFEWK+lcskUOxWw4q3oB11Byv HwqNiG1E2CY2xn/SbsplynEGH68tPnHEODhaMJut7GDxan45dGmtEm6b16XDZbR3FaCK 9FO03QPIlmveE53h3qRF6RXBxk028+QZZ7BfnX7s8ZZ6jeeMx1UHURyJlTCDbJz2Vd0T hozsBRkrUlwBKatP31Brp84Dzk7tVVnCPtepDcvzJFeufAwFUt8GAEtqmUNkyc7eZr58 qurA== X-Forwarded-Encrypted: i=1; AJvYcCUoHGwLQixeq+m77GppLT/d98laMz+qHYUwwwjonHyk9s3AyJxRYwtrF4YT44Xs5438zMpFPTlntZkNharswnkDC0F12AoQL5yEQcUn X-Gm-Message-State: AOJu0YyRz/eAvrFFnZjwO11c2MrkvomLHKlEuG2MlQc1xx4sFIyDhpG1 niDcKiMXF83VOzWF3RBG9sl2VHQY+LgP7eG1BZmJKvzovXxxq4uOYAlw+6Tlc5s= X-Google-Smtp-Source: AGHT+IGnAoJ5NYdojrpk5kNKJAL/+A9oPWkqoZylV5Y3F1ZmyUCdRxQIgDj1CJDkY811t3vfT0g/Uw== X-Received: by 2002:a05:6a21:612:b0:1c3:b20f:de15 with SMTP id adf61e73a8af0-1c44f9696d1mr927612637.52.1721685495398; Mon, 22 Jul 2024 14:58:15 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fd6f44f0d4sm59997775ad.219.2024.07.22.14.58.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jul 2024 14:58:14 -0700 (PDT) From: Charlie Jenkins Date: Mon, 22 Jul 2024 14:58:06 -0700 Subject: [PATCH v6 02/13] dt-bindings: cpus: add a thead vlen register length property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240722-xtheadvector-v6-2-c9af0130fa00@rivosinc.com> References: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com> In-Reply-To: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins , Conor Dooley X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721685488; l=1911; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=lK25kSvuXBbjCsm1KOScKY69sa4rMHinL5Ye8aockR0=; b=W8J1yxGjPC+Bnnprr/HHbu8w/Ykizyg24i4N6mFJiAW32HSh9qI/PyEGVc60fweu2c5CDTN1W AxCC+NW/3zQBWqBTUHCkqRhgYF2Rrr8gXrY1cDWPE5Er/t5Eit1QIdy X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Add a property analogous to the vlenb CSR so that software can detect the vector length of each CPU prior to it being brought online. Currently software has to assume that the vector length read from the boot CPU applies to all possible CPUs. On T-Head CPUs implementing pre-ratification vector, reading the th.vlenb CSR may produce an illegal instruction trap, so this property is required on such systems. Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/cpus.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index 8edc8261241a..c0cf6cf56749 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -26,6 +26,18 @@ description: | allOf: - $ref: /schemas/cpu.yaml# - $ref: extensions.yaml + - if: + not: + properties: + compatible: + contains: + enum: + - thead,c906 + - thead,c910 + - thead,c920 + then: + properties: + thead,vlenb: false =20 properties: compatible: @@ -95,6 +107,13 @@ properties: description: The blocksize in bytes for the Zicboz cache operations. =20 + thead,vlenb: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + VLEN/8, the vector register length in bytes. This property is requir= ed on + thead systems where the vector register length is not identical on a= ll harts, or + the vlenb CSR is not available. + # RISC-V has multiple properties for cache op block sizes as the sizes # differ between individual CBO extensions cache-op-block-size: false --=20 2.44.0 From nobody Tue Dec 16 19:40:49 2025 Received: from mail-pg1-f171.google.com (mail-pg1-f171.google.com [209.85.215.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18C504964A for ; Mon, 22 Jul 2024 21:58:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721685499; cv=none; b=Br3BxByY4rIQjaiql1y7VUvH5vkfBTiXS4BzdPv6bRZaVAP81X6/saN7MbvjDEQ5prrz349el2so3d6+rsujcHwFQefDkQ8c1BDv71C0AOyOVhqN0xLj5Cau2PGL7XRLBOFyRiDbJaU4Uj+Q6Is+wkapkIqooV848B/TfJ/Vc9U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721685499; c=relaxed/simple; bh=I9BB6+DSsEot7edtm0hreUvYP0RvytEdbSv790C0uE4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AJx9f041ZsZQP/WN/giOloqtotSogTueTcGFZ+GKXm5fnfweuezJfXnoTQ2F8aDVdHtLa6z+k6pqSQmHal4UituhSkYR6Ck+E9olaZEtmxp+szf8ToLaOXzkvVa578BHTBCdiNfla+YRJsFX8WvRM9O4tob5dMVBX51hUGyJDAs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=evV45bRa; arc=none smtp.client-ip=209.85.215.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="evV45bRa" Received: by mail-pg1-f171.google.com with SMTP id 41be03b00d2f7-7a10b293432so90813a12.0 for ; Mon, 22 Jul 2024 14:58:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1721685497; x=1722290297; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=0g1DxVy9Ij2OMsYu7oTE9l+cI+PV2f969LKgw+PL+a8=; b=evV45bRaOamvLB0PcqEPmnl80aF3UCMhnEYhyycaZ5pKb/p8tf1vnxr9Sqc9QMDHx7 mOyq09amSEBJQ0wyqemxbVvHPYjZtm4+752zdtBZZqnzWg5ejw9lFHzFOLkjH04gqeBL qEKPDug2ldasL3Q8wUqRBO9FfhImWTHTLogpM+r4acOv1x+pBhuLBfYMv1M1ZBdyce7q 75mDF+6weAbMO8Sg59YLC0z+J5kOYmsEp1RIcMpPqWDWdpisPM+TCJvTGOVpF6ORV15p /0l3begeSUdOpw+XAzQtPjNLyMyQuIWG7VGDw5wmWrtRV7W/HiabpEUGSeJ7ftGy8UmT /HTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721685497; x=1722290297; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0g1DxVy9Ij2OMsYu7oTE9l+cI+PV2f969LKgw+PL+a8=; b=SsoXd8ie1wW679BnXYVfocpSONCl+p5qSHeMIUubQHbpwURkmbjOuhB9qciVgAFD++ 2YPNMgpw8+3w/OkFCQHeuke6H1sM0qOmrPdDMHqEjdsAPBZWvDQKuydku5+49iMKPcI5 jZ/2vw9se1LzXOO7XSyTKz+ts97cquWZox6fp+CTDtt53I9Q7aXH5/dpxnDtICk9hpSD vYy4Om4PHJp/QfBXbDI1nfRpjyyUdnEGOR+GF1929as3no8vcF7bG6qB6TnsXvs3eRnU +19Ft3C6y+22jkxi4zRK5skNsNmUxbnUOfHQuNkvEPTjgG/KCfZUiVa8Gg7n8w4NKjFS 47bA== X-Forwarded-Encrypted: i=1; AJvYcCVkr3QfDSD2lSfkvSohwdMLePzQ7Nu820l/Az9Cj1NN2b0z2bHczOIDOfTGp7zUQkU8v1rVNS3emYiHpVsrhvUEapA3Qde9aAV99Lq0 X-Gm-Message-State: AOJu0Yzbj1Vq5b2cMFUg22BnTtkodBnzWvoP32n7Lw6UDkSgWjJsDZaT VdeL+Jf0PN2ev1BRWn2z1siWcB6ZdtEHgHoZOr6+qjLTWgCBXaJtKGTSygkFWXE= X-Google-Smtp-Source: AGHT+IFIcgz7HARCdDrV5W8AAjYNm6XpC7WdcgHj9xNl+u1lsoc3o8CsMZxn17S3ppWeaBN7sAGQTg== X-Received: by 2002:a05:6a21:7881:b0:1c2:8cc4:908a with SMTP id adf61e73a8af0-1c4285db7e2mr7544150637.46.1721685497425; Mon, 22 Jul 2024 14:58:17 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fd6f44f0d4sm59997775ad.219.2024.07.22.14.58.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jul 2024 14:58:16 -0700 (PDT) From: Charlie Jenkins Date: Mon, 22 Jul 2024 14:58:07 -0700 Subject: [PATCH v6 03/13] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240722-xtheadvector-v6-3-c9af0130fa00@rivosinc.com> References: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com> In-Reply-To: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins , Conor Dooley X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721685488; l=960; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=I9BB6+DSsEot7edtm0hreUvYP0RvytEdbSv790C0uE4=; b=0QcF5MOvwNThO8NaS/lKWq5VAiR/iEGql6uw4zAt+lOorHLAdp8R5/hl57aFXb0GgjrdhiJy+ LF1VgV1VUUSB4jFlWmXdN0rWKHp5a/ASB87utx28kucPM7yzo/B2hBx X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= The D1/D1s SoCs support xtheadvector so it can be included in the devicetree. Also include vlenb for the cpu. Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley Acked-by: Chen-Yu Tsai --- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boo= t/dts/allwinner/sun20i-d1s.dtsi index 64c3c2e6cbe0..6367112e614a 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -27,7 +27,8 @@ cpu0: cpu@0 { riscv,isa =3D "rv64imafdc"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr= ", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xtheadvector"; + thead,vlenb =3D <128>; #cooling-cells =3D <2>; =20 cpu0_intc: interrupt-controller { --=20 2.44.0 From nobody Tue Dec 16 19:40:49 2025 Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF6FD5380F for ; Mon, 22 Jul 2024 21:58:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721685502; cv=none; b=oRU8dwnhaBfbi63hNdmbQ+IHPAz+POJw8d9bFMsDDoTYGhmKhOjYtuGslWjc6sUDUjk79kcg8I7RCsBmOvxdGrMYLe5eaqHLJJ7vUCMBCKt9md18mHOt8e8md/KP3jRbxpc/kQ7ntOfYzsXn3+Gp2+zMPeK5ZBlW/5kmdCbPwao= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721685502; c=relaxed/simple; bh=M+1BS68dt7Jh5BDKNUbAmq4jayBxd0dfxnDuF0LILQU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZSMPfecZzogBroM89x1bNhZlVU08/VqRdjpaLs+NmhSRpcICJA2PgOv7WG2fkoGSvtgEILPrkMw9srNioXV2xdvaoqZdm5Bn/ueiUAPTY07YVa1xspNfuE/+Inz3lfsAmDDEyFA+hy5mTBCTbHqhdLZ+YjNCfTEDvBmhnUlRCZo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=PCPc+55b; arc=none smtp.client-ip=209.85.214.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="PCPc+55b" Received: by mail-pl1-f170.google.com with SMTP id d9443c01a7336-1fa9ecfb321so934615ad.0 for ; Mon, 22 Jul 2024 14:58:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1721685500; x=1722290300; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=sBB60L3vIBLp+F/JpYya3NHcSC2vXYtRWb/t7HsnMxM=; b=PCPc+55brsW2G4B0o48BY4lpEjUe3F6726E0uTjS+I2wWLjTWQ/9jLNfl3Xx6B3qdc u0QyD/h3ISaR1tz8NQcSA2oEk0thKjMb1Ud3srpGq73Jy1R2yq02ngEezaEgvWLkBWoa 20xW5WBnjgnVM1PXEWc3fv7CGfAiOOJDQnyc7gjWcaxyPj/XUtYcTXvaYrSDrUrwJi5D UTkiCKHo99Pc42yadgDJvrXZdUK54ZsHARNrNDm9K2PAogfg6oYJU9sdbS6NWc5xA5dV QZnqXJR0JQ5WKaziHX+Qgtn2QsUVryx1IiETU/9V85jhqIUToMi2zz4I4n0Zron+ggjg JMnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721685500; x=1722290300; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sBB60L3vIBLp+F/JpYya3NHcSC2vXYtRWb/t7HsnMxM=; b=ssBgvcW+ox22oPzUbXtsErMMFS10RrICX1EQiB9dl2OKNjM5xqm82pgl4EshasyxGa HHnDZSUsxTfr4fgFylrlIgXwkWc2wNQhSO5T/U1CSPgcP4NKGEWxdt4WSUhEx2LxOchZ N6IWF8SgY+5ZOfiPVZjDiF+VJlMCOZj9Sar3fu+hujGoHbGfnJHSNhWfDN1qOa/j8ku3 xvUV3FaKLXWMhu6HAJgyY6eNmYoM0OBSIrsAWJwJmxnjmRy0ezaFZgAK5myFy1RXohUz 7ONlcPKJNjJeVFCE8GOC1HJFk0QryS2rq/wFc8VBmOrM3BVAN/D8Z80Xn4yRJxecOm/l ZVbg== X-Forwarded-Encrypted: i=1; AJvYcCWJ1mftbThbYauShdKHW4BJFLEDdjmKMij9KVfvHQD7TmTLUMUwKoiF3SNex33VMHT1fIIg7X746wXwapAkHdfmuaugMoPIf1p1HHU2 X-Gm-Message-State: AOJu0YyiCwpVIOikaA3h/RiR4tubzwel0iKTIv5f8ANmNSCN1hsk3U2a B38zjfGuCfYaAdzlr1HKRUjNtyPMNnkhB0csfI7RUCYWXLiY/ZmH1z8ebxCE220= X-Google-Smtp-Source: AGHT+IFaN4ESbI6ZNVa4slRvmiP1LMcMzLp5st8yebAA+cetMuy2jWf+ntmzE8fyAXUuZj4P9Hjxcg== X-Received: by 2002:a17:903:41c7:b0:1fd:5eab:8c73 with SMTP id d9443c01a7336-1fdb5ee31e7mr9787365ad.35.1721685499502; Mon, 22 Jul 2024 14:58:19 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fd6f44f0d4sm59997775ad.219.2024.07.22.14.58.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jul 2024 14:58:18 -0700 (PDT) From: Charlie Jenkins Date: Mon, 22 Jul 2024 14:58:08 -0700 Subject: [PATCH v6 04/13] riscv: Add thead and xtheadvector as a vendor extension Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240722-xtheadvector-v6-4-c9af0130fa00@rivosinc.com> References: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com> In-Reply-To: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins , Conor Dooley X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721685488; l=5053; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=M+1BS68dt7Jh5BDKNUbAmq4jayBxd0dfxnDuF0LILQU=; b=nQvPKPQlIVxPHZH2ECRhvw5ZElfE6yU1elJPvior8/401GnYFXHYVcVha1ZI/EstflzMO3a1n qcTZ6jNLhkiAvPR9i9ZfSLHxKHfalFsmmowwyoq145ETE5nVpooMfbm X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Add support to the kernel for THead vendor extensions with the target of the new extension xtheadvector. Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley --- arch/riscv/Kconfig.vendor | 13 +++++++++++++ arch/riscv/include/asm/vendor_extensions/thead.h | 16 ++++++++++++++++ arch/riscv/kernel/cpufeature.c | 1 + arch/riscv/kernel/vendor_extensions.c | 10 ++++++++++ arch/riscv/kernel/vendor_extensions/Makefile | 1 + arch/riscv/kernel/vendor_extensions/thead.c | 18 ++++++++++++++++++ 6 files changed, 59 insertions(+) diff --git a/arch/riscv/Kconfig.vendor b/arch/riscv/Kconfig.vendor index 6f1cdd32ed29..9897442bd44f 100644 --- a/arch/riscv/Kconfig.vendor +++ b/arch/riscv/Kconfig.vendor @@ -16,4 +16,17 @@ config RISCV_ISA_VENDOR_EXT_ANDES If you don't know what to do here, say Y. endmenu =20 +menu "T-Head" +config RISCV_ISA_VENDOR_EXT_THEAD + bool "T-Head vendor extension support" + select RISCV_ISA_VENDOR_EXT + default y + help + Say N here to disable detection of and support for all T-Head vendor + extensions. Without this option enabled, T-Head vendor extensions will + not be detected at boot and their presence not reported to userspace. + + If you don't know what to do here, say Y. +endmenu + endmenu diff --git a/arch/riscv/include/asm/vendor_extensions/thead.h b/arch/riscv/= include/asm/vendor_extensions/thead.h new file mode 100644 index 000000000000..48421d1553ad --- /dev/null +++ b/arch/riscv/include/asm/vendor_extensions/thead.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_H +#define _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_H + +#include + +#include + +/* + * Extension keys must be strictly less than RISCV_ISA_VENDOR_EXT_MAX. + */ +#define RISCV_ISA_VENDOR_EXT_XTHEADVECTOR 0 + +extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_the= ad; + +#endif diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 271bb0917fcb..041e5e8f8312 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -25,6 +25,7 @@ #include #include #include +#include =20 #define NUM_ALPHA_EXTS ('z' - 'a' + 1) =20 diff --git a/arch/riscv/kernel/vendor_extensions.c b/arch/riscv/kernel/vend= or_extensions.c index b6c1e7b5d34b..662ba64a8f93 100644 --- a/arch/riscv/kernel/vendor_extensions.c +++ b/arch/riscv/kernel/vendor_extensions.c @@ -6,6 +6,7 @@ #include #include #include +#include =20 #include #include @@ -14,6 +15,9 @@ struct riscv_isa_vendor_ext_data_list *riscv_isa_vendor_e= xt_list[] =3D { #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_ANDES &riscv_isa_vendor_ext_list_andes, #endif +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD + &riscv_isa_vendor_ext_list_thead, +#endif }; =20 const size_t riscv_isa_vendor_ext_list_size =3D ARRAY_SIZE(riscv_isa_vendo= r_ext_list); @@ -41,6 +45,12 @@ bool __riscv_isa_vendor_extension_available(int cpu, uns= igned long vendor, unsig cpu_bmap =3D &riscv_isa_vendor_ext_list_andes.per_hart_isa_bitmap[cpu]; break; #endif + #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD + case THEAD_VENDOR_ID: + bmap =3D &riscv_isa_vendor_ext_list_thead.all_harts_isa_bitmap; + cpu_bmap =3D &riscv_isa_vendor_ext_list_thead.per_hart_isa_bitmap[cpu]; + break; + #endif default: return false; } diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kern= el/vendor_extensions/Makefile index 6a61aed944f1..353522cb3bf0 100644 --- a/arch/riscv/kernel/vendor_extensions/Makefile +++ b/arch/riscv/kernel/vendor_extensions/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only =20 obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) +=3D andes.o +obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) +=3D thead.o diff --git a/arch/riscv/kernel/vendor_extensions/thead.c b/arch/riscv/kerne= l/vendor_extensions/thead.c new file mode 100644 index 000000000000..0934a2086473 --- /dev/null +++ b/arch/riscv/kernel/vendor_extensions/thead.c @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include + +#include +#include + +/* All T-Head vendor extensions supported in Linux */ +const struct riscv_isa_ext_data riscv_isa_vendor_ext_thead[] =3D { + __RISCV_ISA_EXT_DATA(xtheadvector, RISCV_ISA_VENDOR_EXT_XTHEADVECTOR), +}; + +struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_thead =3D { + .ext_data_count =3D ARRAY_SIZE(riscv_isa_vendor_ext_thead), + .ext_data =3D riscv_isa_vendor_ext_thead, +}; --=20 2.44.0 From nobody Tue Dec 16 19:40:49 2025 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45B0C61FD7 for ; Mon, 22 Jul 2024 21:58:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721685505; cv=none; b=lLCAkdbON5EEU+p8vumpR+acn+aSLf0jhPoTpPIMfwPiM06vTAD3LsbmpuGNR+v3x4oYVdPutkFhi7bqK8iShYhJJbHEwcxmxjvDhyOnCPK8x2MPMyQZ0c7ln4fi1V7AhuBW3+TSeOtFGJ/GDUYGpriclQrBsygVB1+OAWkIjfs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721685505; c=relaxed/simple; bh=K+roXVx59nBWzGVd/j10XnzknGtMw9TY/ZlmKWcsED4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cEAyuyZ2Z8wwVjQqrVa0yDL5AtcF8FqF2CXR2g8lgbBVigjSa38R2raUlG3K137LYLBZxKvNd94sh/v3ZmwqEtYEasJu8X4hEyG2XqjKaZR6GRRkn+OOYQCQDuoDqAgZt7ptF4r5mNpqPkiW6t8sX+Kkw37By3LoN0ktXl72iG4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=g16oLaid; arc=none smtp.client-ip=209.85.214.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="g16oLaid" Received: by mail-pl1-f173.google.com with SMTP id d9443c01a7336-1fc587361b6so36293665ad.2 for ; Mon, 22 Jul 2024 14:58:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1721685502; x=1722290302; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=9o2be5FktIdX69DunJPm+I88K7Op3K5NkCKgmd4N1yw=; b=g16oLaidCJjFTE/MOqDdaSoMIWjtcpeOd3ZK1BZTt4L3EXbWNpDg20oqU4Bmftg3uO r+WSRPZRD4rFmpJ+AzkI/UYuVSR6KHTDZUKQdNJ/NVdvlVOMi2a1cInwC79h2e3G5wxV HCVyoZC3bz7X/3Tr2xHd/qaxMzDOXK2uMMQ+0174qEeE4DMc6kSk5Vu72XabbK9r33SZ Qq8DnvzVKP/wi99OxlTzjeGhVH3nIksj3mJM+ZNzelyReSW53JKoCsMN8/xBHA+uL0H8 fmiaNGFm4X/e2P7ISubrWeJ1ToAM55OZXh6cNGQRTB8YEVEPz0nXzgmqKYgM4tlTRJQx 9OdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721685502; x=1722290302; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9o2be5FktIdX69DunJPm+I88K7Op3K5NkCKgmd4N1yw=; b=vMZSKY+40A5VbzC43kyGwuf1GKwaISMYhKXEE+Er4sQdTtD70Cd2jJzq+LJ/kw9W+5 Pl8HkrycKdlaEVsGYMcZJumdrb5PG9hv+Ka94KBgTzsYfnd+Vn5NEwNt5yta5wBfh0ZD iDpDXQi8ms3LsD160/1N2eDOdVNPjR8eIDKhOD/dtuGqfYt9x/hiRIK0+htMzJ21HDoc fLH7K8hrFtYCl6cZ6hhFzv56Bfo+7kM5q5F5+NDlGvEwrRINTsGB24iLucEin9EKnEjo fVwtdrq/Z0Yh3ewRQBnMgmLO3A24E/N9yvy2L2OKXmCDn7CP3HNcTeXLmC8zNYLOHRQ3 rBNQ== X-Forwarded-Encrypted: i=1; AJvYcCVzjMFHACDN5ytjNCK7xhGr5iSqvmwi2OscMtRHAwRX7n1/j1cT/7OhDFmFPv3Dj2DuxmWgC+X806xAx4O8myeLLEjfetAntOf+fT5/ X-Gm-Message-State: AOJu0Yzl+P+L4oCh6TqeFboXsIGuDE5NuA5fnch2JxwoYIjF7PdebQyh YzpGDRaJGCnMA5qRZdRq65lsroUXI63VQQRvRKAfJVvozizd+BqEMfnDpRdmxFU= X-Google-Smtp-Source: AGHT+IGKNlAtO6rZVRRnrgWCDgWtuHR8Fis6cN+vrzFPXf1APrlXu2h+fV+Vle0MjURqbTVX1adJBw== X-Received: by 2002:a17:902:f547:b0:1fd:8e8d:8669 with SMTP id d9443c01a7336-1fd8e8d8b26mr33769225ad.2.1721685501671; Mon, 22 Jul 2024 14:58:21 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fd6f44f0d4sm59997775ad.219.2024.07.22.14.58.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jul 2024 14:58:20 -0700 (PDT) From: Charlie Jenkins Date: Mon, 22 Jul 2024 14:58:09 -0700 Subject: [PATCH v6 05/13] riscv: vector: Use vlenb from DT for thead Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240722-xtheadvector-v6-5-c9af0130fa00@rivosinc.com> References: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com> In-Reply-To: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins , Conor Dooley X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721685488; l=4541; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=K+roXVx59nBWzGVd/j10XnzknGtMw9TY/ZlmKWcsED4=; b=4Y6We49ontTCJlLKvHMg2b5DNGO/VcLls0RnnyMu52Y38BbHV6jRAVvpDWrfU6YVcM1SDiAU7 6Dx3kl/kl+xAaDZEvLFnSXyS97AXbCpQyOG+Uvpg658cEMfPEojvkr/ X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= If thead,vlenb is provided in the device tree, prefer that over reading the vlenb csr. Signed-off-by: Charlie Jenkins Acked-by: Conor Dooley --- arch/riscv/Kconfig.vendor | 13 ++++++++++ arch/riscv/include/asm/cpufeature.h | 2 ++ arch/riscv/kernel/cpufeature.c | 48 +++++++++++++++++++++++++++++++++= ++++ arch/riscv/kernel/vector.c | 12 +++++++++- 4 files changed, 74 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig.vendor b/arch/riscv/Kconfig.vendor index 9897442bd44f..b096548fe0ff 100644 --- a/arch/riscv/Kconfig.vendor +++ b/arch/riscv/Kconfig.vendor @@ -26,6 +26,19 @@ config RISCV_ISA_VENDOR_EXT_THEAD extensions. Without this option enabled, T-Head vendor extensions will not be detected at boot and their presence not reported to userspace. =20 + If you don't know what to do here, say Y. + +config RISCV_ISA_XTHEADVECTOR + bool "xtheadvector extension support" + depends on RISCV_ISA_VENDOR_EXT_THEAD + depends on RISCV_ISA_V + depends on FPU + default y + help + Say N here if you want to disable all xtheadvector related procedures + in the kernel. This will disable vector for any T-Head board that + contains xtheadvector rather than the standard vector. + If you don't know what to do here, say Y. endmenu =20 diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index 45f9c1171a48..28bdeb1005e0 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -31,6 +31,8 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); /* Per-cpu ISA extensions. */ extern struct riscv_isainfo hart_isa[NR_CPUS]; =20 +extern u32 thead_vlenb_of; + void riscv_user_isa_enable(void); =20 #define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size, _= validate) { \ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 041e5e8f8312..bf25215bad24 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -37,6 +37,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __rea= d_mostly; /* Per-cpu ISA extensions. */ struct riscv_isainfo hart_isa[NR_CPUS]; =20 +u32 thead_vlenb_of; + /** * riscv_isa_extension_base() - Get base extension word * @@ -772,6 +774,46 @@ static void __init riscv_fill_vendor_ext_list(int cpu) } } =20 +static int has_thead_homogeneous_vlenb(void) +{ + int cpu; + u32 prev_vlenb =3D 0; + u32 vlenb; + + /* Ignore thead,vlenb property if xtheavector is not enabled in the kerne= l */ + if (!IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR)) + return 0; + + for_each_possible_cpu(cpu) { + struct device_node *cpu_node; + + cpu_node =3D of_cpu_device_node_get(cpu); + if (!cpu_node) { + pr_warn("Unable to find cpu node\n"); + return -ENOENT; + } + + if (of_property_read_u32(cpu_node, "thead,vlenb", &vlenb)) { + of_node_put(cpu_node); + + if (prev_vlenb) + return -ENOENT; + continue; + } + + if (prev_vlenb && vlenb !=3D prev_vlenb) { + of_node_put(cpu_node); + return -ENOENT; + } + + prev_vlenb =3D vlenb; + of_node_put(cpu_node); + } + + thead_vlenb_of =3D vlenb; + return 0; +} + static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) { unsigned int cpu; @@ -828,6 +870,12 @@ static int __init riscv_fill_hwcap_from_ext_list(unsig= ned long *isa2hwcap) riscv_fill_vendor_ext_list(cpu); } =20 + if (riscv_isa_vendor_extension_available(THEAD_VENDOR_ID, XTHEADVECTOR) && + has_thead_homogeneous_vlenb() < 0) { + pr_warn("Unsupported heterogeneous vlenb detected, vector extension disa= bled.\n"); + elf_hwcap &=3D ~COMPAT_HWCAP_ISA_V; + } + if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) return -ENOENT; =20 diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c index 682b3feee451..9775d6a9c8ee 100644 --- a/arch/riscv/kernel/vector.c +++ b/arch/riscv/kernel/vector.c @@ -33,7 +33,17 @@ int riscv_v_setup_vsize(void) { unsigned long this_vsize; =20 - /* There are 32 vector registers with vlenb length. */ + /* + * There are 32 vector registers with vlenb length. + * + * If the thead,vlenb property was provided by the firmware, use that + * instead of probing the CSRs. + */ + if (thead_vlenb_of) { + this_vsize =3D thead_vlenb_of * 32; + return 0; + } + riscv_v_enable(); this_vsize =3D csr_read(CSR_VLENB) * 32; riscv_v_disable(); --=20 2.44.0 From nobody Tue Dec 16 19:40:49 2025 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E00260263 for ; Mon, 22 Jul 2024 21:58:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721685505; cv=none; b=UJVbjsc8o8wqWhqf64ZvgLqZcoGhD5XBU+halCiJN+9EEhotosIk7PDdisdF41NiMQ8jXElRq8l1CL2Ujlz4z3peGS7QuzuWOSVl/HHjVSl/1Bl8WBkTfDz/47jhENjgXM3RQOO1iftj39CUAyOlF5dHtQW2xglclNUEW+zEcPI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721685505; c=relaxed/simple; bh=wrX0uryyy89vYlAinvVr2O6QBZz257uuEBuSnzas59I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DC+VUluwIqX/PQb3AXEsiEHr4WyL+jCCvJWYoWoY1eJR0m0jmQUtH/x3YPqB5WlyhrRbk1EERz1WnkO2yh9lQ/YnP4ejUgiPD2hiOQPKONlvHwrPm5QizN5qHDM0Fdu5PCzDPEBECtGNeZpcqiswxGnCJWrXDqtFfUPzC1WtysQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=S6JCyKDt; arc=none smtp.client-ip=209.85.214.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="S6JCyKDt" Received: by mail-pl1-f169.google.com with SMTP id d9443c01a7336-1fb53bfb6easo146095ad.2 for ; Mon, 22 Jul 2024 14:58:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1721685504; x=1722290304; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=425S2jEpk/4yk63j4Ow9jwZmOCFjeEcHZbKGmEqnWN8=; b=S6JCyKDtlTjCD2AVeql+DLdmwxa2fIcfB91V8PCvJnhxBaQolx5ebx5XUIRtWWvNbu b/lzk3NHPvPY/27Xnq0g+AJqC6yZUT5tIriSw+KI9tusARIDSrtumuBZNpsXbweNlY66 vY5TBVXEl33B3/L84qOXX4YhxuQwJvwCTJiFtFLpGZJO1GjnbAwxFiYNJuS0BTLflDlq aU/YmGcojeHT35ucXhK9dc1+PvjsF7RM2B7vrvM+shxIqwyEUTyKPe+W9ZQC6EQUfnt0 iFDhqEyuoHCRLaHrO8wl16YULePcqPGNB62nCHvq1vyqF3M98CHaHzAHQjyR3ZjcmlXx /teQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721685504; x=1722290304; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=425S2jEpk/4yk63j4Ow9jwZmOCFjeEcHZbKGmEqnWN8=; b=CgMhkrd6otcLek7sFpxYcqVM0e3vlByaHkx+tJ8z0TAaBHpSONPuCZxGmWUE0A2W3y rJ/HLgOrwSGsogM1kJNl0ER2AJvUIpyVj6M62+05tYOQUl6LKpw+28xZY+AQpFPJ5ofI cze8U1qmILZYwSPDyDWgMv/g3suFmyrA64+jpI+nGQqjRR4DknkVcE77yeiEJ5m1mZ4u HanXUdT/iNfm8FAWt1xijV+VqbzYMuv1+JcZv+l7wr9K4o5E6JK/QewjMwTH6yHDATRh Zd35OpaLu1NwohoCmiOv5X+3meOt/fhzv1qX/BqaELHfuDET1oDkRECdJ99vLWgNrC1J UGBw== X-Forwarded-Encrypted: i=1; AJvYcCVHk+YjY8jIb6xxO2R54xytooMN7PH0MHlsFCeeQHsnvjM3Gd1eIX+kH5cnOI6+kvfhUNTjkFjrUDdiD/NVDxfH9eENtooNcD1KLzXJ X-Gm-Message-State: AOJu0YzVbcgGPw8AhxJFBmg1Lp/I8IKh4x1qXbJ4au5bGhvf/FnFww5V wKwLASZTcuRhKIkdJNY6ycwS3AvHBYam+7xp3osD+7lJhTCW+6Q/1d1b5hBmlPQ= X-Google-Smtp-Source: AGHT+IEoJN1pCcgoeebixEMdeRFm+lX7Fz51AAK3F3aCHBFtjYtz91oZywD8oyA7iNOCpmg2SBax6g== X-Received: by 2002:a17:902:e5cd:b0:1fd:96e1:802a with SMTP id d9443c01a7336-1fd96e181ddmr34308645ad.59.1721685503730; Mon, 22 Jul 2024 14:58:23 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fd6f44f0d4sm59997775ad.219.2024.07.22.14.58.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jul 2024 14:58:23 -0700 (PDT) From: Charlie Jenkins Date: Mon, 22 Jul 2024 14:58:10 -0700 Subject: [PATCH v6 06/13] RISC-V: define the elements of the VCSR vector CSR Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240722-xtheadvector-v6-6-c9af0130fa00@rivosinc.com> References: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com> In-Reply-To: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins , Heiko Stuebner , Conor Dooley , Heiko Stuebner X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721685488; l=930; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=0jkC45FH0LUvSVfvCEJuCBZ027fqPbAipPAnc4zFoN4=; b=0RZc5Y7+dPFte3RfQycOhdYrS0o9oSHCnJx5nucXwKbADyIcT6a8rMi+tKbs59EJDNFM7h/IW hf3xB+tD++5AswmTbacfCC/pWDHRloSyAPnBD8iVQF4NrrEQ4Jj9uG8 X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= From: Heiko Stuebner The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0]. Define constants for those to access the elements in a readable way. Acked-by: Guo Ren Reviewed-by: Conor Dooley Signed-off-by: Heiko Stuebner Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/csr.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 25966995da04..3eeb07d73065 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -300,6 +300,10 @@ #define CSR_STIMECMP 0x14D #define CSR_STIMECMPH 0x15D =20 +#define VCSR_VXRM_MASK 3 +#define VCSR_VXRM_SHIFT 1 +#define VCSR_VXSAT_MASK 1 + /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ #define CSR_SISELECT 0x150 #define CSR_SIREG 0x151 --=20 2.44.0 From nobody Tue Dec 16 19:40:49 2025 Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8962D6A339 for ; Mon, 22 Jul 2024 21:58:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721685508; cv=none; b=gHNEiR6pYe3ono1amfWCwRvz+GKEXHFc6V5/UQ/wV9vOQXy8irLrlWWthJTGZyRRjKsWhC9WfrUL0m1kl/ZZl+o69NFI6xAfYGSR6XPDZdqdYrFk0cwRgnQ8kjfBSc9sWSUAVLGdGh90dLSpkvLfY0pbkdOwRSc9jvHSRXVYPBM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721685508; c=relaxed/simple; bh=/awdvkpT37Pcv9l+R6WHhK0Ytr8TrWH5wurC23dujZY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZaJmyCFRL0G7R7v0/VnU5eb9mMTjMCfDKc4zxvb5mJKSoTCsHHUrDFDLodmFDpX9dpydm1c8MNER5gQZzA4strsPZ2MXFA26C+yiiDT7/+s0PngyZqt1QzbLu12OZK4VAYwZgIb+Bhka0KGhMG+2xshE+uWoDlX/z93pLG8id/8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=wAIV6Gh6; arc=none smtp.client-ip=209.85.214.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="wAIV6Gh6" Received: by mail-pl1-f181.google.com with SMTP id d9443c01a7336-1fc5549788eso36622225ad.1 for ; Mon, 22 Jul 2024 14:58:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1721685506; x=1722290306; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=7liFIbqG3XLVQtLXjuEuZ9H5FIup228+UAuRj2s502A=; b=wAIV6Gh6IyCg6aHC98bxC5muRWXa4ja0gHiWodDHiWRbrAsAohgjDdjhbbvNsAJ84o llRESt3buUyOsHyci1PmdnKTexTgTRgPYUcCf/glJvwKRSLH0YMNl8xrgGSYECaS8pC9 3XHDapoTjPSTyTY3Rop1m+DSJ1IGiqslKR5CtnDYWCSC2Ca3/d8JVfNUWYtv1bpfrXQA p+hi2RSPotiTsfX9sz6fq8K+6b/Q22Gy6GhU/EkxC2+bsD0cHKs2b+k0YGnqJ+kwAZOR vBXE36B4VwTxixmscGtC0owxfTntrbmeWnt+xMxpAQvMJblCW0iYKwe7OUDxUrsbJc4+ 4Atg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721685506; x=1722290306; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7liFIbqG3XLVQtLXjuEuZ9H5FIup228+UAuRj2s502A=; b=Bl9hq0cpOaBnFS0qFLoknG9Oz1oBTPOh43ceUIZ83T8sIwGoCFg82MX/UP8Iaw2Zlj 8scjOsCQgqcGSKEuD8L1LwRRnSAR8oib6P+2VxdVfehyDP0oWGunvvRwBwCPMwAkoSd4 y1BKq4lzsTdLfZSzZ9tJRYR9ihuwhO71q0XNCDp0OcMrKY5P5nLhFU8eFly4gQaHRZDA nBwD8MR/ZnMWJXTMARx08kIx+XYjGq1i/dWshzZ4OI6VAqh9+ZyBUDT5OVJjL9rkbYPP iMP9Hbd9eRZhHdx8Bz5X5uFWUP5REceiKV7+Ci8FkHf/7uQdj5JIYVEPoLIp8+4RxVTd HnnA== X-Forwarded-Encrypted: i=1; AJvYcCVSfjntOnKMNKaIDA1c92TmKILZR6k2Cc4B+yZmgs3UlXBSWPAXMzW0UmmLPPF7NBrgxxKKGrfplwVnmunY7Uv24Z3bsQe6Qm162n1P X-Gm-Message-State: AOJu0YxWD4gQ082vQUcw5vt6QkvZIA+wlhKHpVDpNXWzrwbaryEMXXmB 0Mu53RR1jlu+/AiCIvrAc410X+nYXTsCl0I9iQW0KwmAyA5/DL4XSFMiCQFJq6g= X-Google-Smtp-Source: AGHT+IEhQYp1BZWLj9eFDI4F+59SR/8t3UUInGJ4gX5TJPVL1PbpSo7Q3rXHcGW/E8u/+YVve3sRYQ== X-Received: by 2002:a17:903:18d:b0:1fd:9fd8:1b2f with SMTP id d9443c01a7336-1fd9fd82008mr51936315ad.8.1721685505924; Mon, 22 Jul 2024 14:58:25 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fd6f44f0d4sm59997775ad.219.2024.07.22.14.58.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jul 2024 14:58:25 -0700 (PDT) From: Charlie Jenkins Date: Mon, 22 Jul 2024 14:58:11 -0700 Subject: [PATCH v6 07/13] riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240722-xtheadvector-v6-7-c9af0130fa00@rivosinc.com> References: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com> In-Reply-To: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins , Heiko Stuebner X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721685488; l=1045; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=/awdvkpT37Pcv9l+R6WHhK0Ytr8TrWH5wurC23dujZY=; b=HkA9GryhuoQSbrAEZ95j95Hqi2eIuaKpw8ZKsmN39SZQzbRBNWPE66zVFn20eiWNCV9omY0DH m+/5MZAQ7RODwQ/ViRBSsCcS8JUhXwkT+4tZRvwC/Z2ygfj/aiygn8J X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= The VXRM vector csr for xtheadvector has an encoding of 0xa and VXSAT has an encoding of 0x9. Co-developed-by: Heiko Stuebner Signed-off-by: Heiko Stuebner Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/csr.h | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 3eeb07d73065..c0a60c4ed911 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -300,9 +300,14 @@ #define CSR_STIMECMP 0x14D #define CSR_STIMECMPH 0x15D =20 -#define VCSR_VXRM_MASK 3 -#define VCSR_VXRM_SHIFT 1 -#define VCSR_VXSAT_MASK 1 +/* xtheadvector symbolic CSR names */ +#define CSR_VXSAT 0x9 +#define CSR_VXRM 0xa + +/* xtheadvector CSR masks */ +#define CSR_VXRM_MASK 3 +#define CSR_VXRM_SHIFT 1 +#define CSR_VXSAT_MASK 1 =20 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ #define CSR_SISELECT 0x150 --=20 2.44.0 From nobody Tue Dec 16 19:40:49 2025 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E4077604F for ; Mon, 22 Jul 2024 21:58:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721685510; cv=none; b=C6g4VjAJ7b5E/MX0+RUnyUgW1lPnhf+7yzYQziYyH12wcsOCNIb0IyyNPo+3t7lja3Rk/6mB5sc8PRPmprbFN9qyxWEmvyjEkuUtylR6DhzErpO2yUYPsDvDbVo9AjqFpn7USOgmBUZe1/sCdnZfnH0SfkoiTsJbsdihv4lAcq4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721685510; c=relaxed/simple; bh=L3aaRS2j1B7ly0GhgM86XDS3MRCOslmFg/ArzwGxzO0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ggKnbxJ6zJZME+gglsfiZSKy1jDzCIAlhnkpXcFvjswK7V0TU/NOg0auID1GMX2HA7vCZHpi4eY7G+r+yhOyf1kMAtMs6WKKfdzWQzIx6ku+tRozzFhnQm1WhcWZ0XkoetHyPveXeE30eQ8C4K5nmbiobKQKmSRtodRFrmJTcy4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=eEsZdZ4K; arc=none smtp.client-ip=209.85.214.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="eEsZdZ4K" Received: by mail-pl1-f178.google.com with SMTP id d9443c01a7336-1fc49c1f3e5so35826155ad.1 for ; Mon, 22 Jul 2024 14:58:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1721685508; x=1722290308; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=UhITSSlteAMwmsPUv9TpJ8KEJQbK1ok0BXYvmwnIXKY=; b=eEsZdZ4KsCrjj7TAwmZqCUcq1hBHXmklA19TlvGZBjmHWi0btvwebV1lodtdjreLZc Rpd3mCVkACt659ZBhziHVkfe7c1tfmvvgg1XfXiefX8EHcCNNF2L4J3JLNV4lau+G4xf G+nOFJ12xlqA9+h3OMIhxRxoGU9Bdk90gOOqPIViPGBedyrep09QH52gtWzzUfX7ypBi wsVHg6BzjhWsf58amQP7rewzQ4lLdiwrzBwCTg4seH5opJo5AdKoupVWl4/LAPKC2lO2 +wbu6On3OgQATxjeLArJ6x99hqhx8FkNSjw/IjiVEyIkvHVWarqTg4FXKICoa27F2e9e LFYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721685508; x=1722290308; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UhITSSlteAMwmsPUv9TpJ8KEJQbK1ok0BXYvmwnIXKY=; b=esgWOhaNFJ/soYlwy5u7R4HdE1xZarw4tsCvkqVQskrKDZUmbkmLMgdyVckb93zcOM 2UIO53U6xX0RFV20BKPKJvTmIMA/+D70LUr2N9fecB36BzBu2AuyVVtlI/AJBTYb2Jtr PcrFydk1jaVe0XV2O/DqR/46Gzf4ysuK2sIaweB0FbQ9klP5jTgwU3hPTY2U0L1RcBpd W5VXRolb8CTBrZ+XNZdbMrewg6ET3eB3yUT6N9kBNKXD6qWO0sSMThvN0F8C88mqFHbI W/lwvPIQ8WbKtXRVHdA/NCr3UPc5s50m2xCpKLnG4DtHT0zusYMOiCUvIlRaI8SI3Jqz JXAQ== X-Forwarded-Encrypted: i=1; AJvYcCUm0hCZ3GJgY3oe14nN/P0oNu9CkGVIC1Vh/+L3wDAmUO+pIFlzFVJIrSgVkJU+K2A1CZHZsZgmZ4mwVlYqcxCNIqv42lVBYnGVBMgq X-Gm-Message-State: AOJu0YxjJaz2VS52/MgsAxrMij1U9DobkIo4rp1hrKhzjSmu508Sr13F eerxJl4mhIwZ+4ukRH3Iyy8ZMvLEO3m81DkKPlCOJnNzNIVSiEKmpk2A2OR/BFw= X-Google-Smtp-Source: AGHT+IF2VUxYR/aRNToCR+5ZrcyCmNKV+sSs8BINBXokqocI6vx0Q1B7xy0Kb+PiYoFTmuhV9YSoTA== X-Received: by 2002:a17:902:d510:b0:1fd:8eaf:eaa9 with SMTP id d9443c01a7336-1fd8eafeec5mr38070905ad.37.1721685508075; Mon, 22 Jul 2024 14:58:28 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fd6f44f0d4sm59997775ad.219.2024.07.22.14.58.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jul 2024 14:58:27 -0700 (PDT) From: Charlie Jenkins Date: Mon, 22 Jul 2024 14:58:12 -0700 Subject: [PATCH v6 08/13] riscv: Add xtheadvector instruction definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240722-xtheadvector-v6-8-c9af0130fa00@rivosinc.com> References: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com> In-Reply-To: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins , Heiko Stuebner X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721685488; l=1957; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=L3aaRS2j1B7ly0GhgM86XDS3MRCOslmFg/ArzwGxzO0=; b=hqIK70baIF2TRsMNhma0nqEfic3E1nBlRr8r5IBs5B1G/V09ObAWM/kiUDmJLqlbsJt62gSOm TBKkN9dv4EhDg1McKFXFHMYxPuqxf1K2g39tmBh7oLjWZiqSN3Lw1vA X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= xtheadvector uses different encodings than standard vector for vsetvli and vector loads/stores. Write the instruction formats to be used in assembly code. Co-developed-by: Heiko Stuebner Signed-off-by: Heiko Stuebner Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/vendor_extensions/thead.h | 26 ++++++++++++++++++++= ++++ 1 file changed, 26 insertions(+) diff --git a/arch/riscv/include/asm/vendor_extensions/thead.h b/arch/riscv/= include/asm/vendor_extensions/thead.h index 48421d1553ad..27a253a20ab8 100644 --- a/arch/riscv/include/asm/vendor_extensions/thead.h +++ b/arch/riscv/include/asm/vendor_extensions/thead.h @@ -13,4 +13,30 @@ =20 extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_the= ad; =20 +/* Extension specific helpers */ + +/* + * Vector 0.7.1 as used for example on T-Head Xuantie cores, uses an older + * encoding for vsetvli (ta, ma vs. d1), so provide an instruction for + * vsetvli t4, x0, e8, m8, d1 + */ +#define THEAD_VSETVLI_T4X0E8M8D1 ".long 0x00307ed7\n\t" +#define THEAD_VSETVLI_X0X0E8M8D1 ".long 0x00307057\n\t" + +/* + * While in theory, the vector-0.7.1 vsb.v and vlb.v result in the same + * encoding as the standard vse8.v and vle8.v, compilers seem to optimize + * the call resulting in a different encoding and then using a value for + * the "mop" field that is not part of vector-0.7.1 + * So encode specific variants for vstate_save and _restore. + */ +#define THEAD_VSB_V_V0T0 ".long 0x02028027\n\t" +#define THEAD_VSB_V_V8T0 ".long 0x02028427\n\t" +#define THEAD_VSB_V_V16T0 ".long 0x02028827\n\t" +#define THEAD_VSB_V_V24T0 ".long 0x02028c27\n\t" +#define THEAD_VLB_V_V0T0 ".long 0x012028007\n\t" +#define THEAD_VLB_V_V8T0 ".long 0x012028407\n\t" +#define THEAD_VLB_V_V16T0 ".long 0x012028807\n\t" +#define THEAD_VLB_V_V24T0 ".long 0x012028c07\n\t" + #endif --=20 2.44.0 From nobody Tue Dec 16 19:40:49 2025 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2078E12D752 for ; Mon, 22 Jul 2024 21:58:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721685513; cv=none; b=JEinFGvChqf9ICrvDqbQdkU3TLoZUkEhWEAiuv+w0H4MPGll1bzPDsqI9G/i1NOEq8BAUQdRE4es/wGVXK55UGe5aye8Z1axZt2ZJqx0uICTrv5qiWE6y0qmebghB0O70kReVHRtSceByCosNoiXugt1pws1v+IO6iL6fcS3AVs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721685513; c=relaxed/simple; bh=TwA0gwFg2vgNEL89uxalGbRfzdlmmPfjJ4oKZqlRd+A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=X5j75txESPNDAvvd6MjRrpmZl/N8b/LjEla2F/KgOZ7L34nCBsH6RdlDZggfdIeHJijgHS1j+oPAB8nKMlZDDVM9LGxmXdPxLWFKRRndSqBkt6bxzlalgHINV4Y20kO+0OTx5HV1j36NobXw12TFoFnMAimqbCbEIspI01M4eZ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=fJ5IpWiX; arc=none smtp.client-ip=209.85.214.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="fJ5IpWiX" Received: by mail-pl1-f176.google.com with SMTP id d9443c01a7336-1fc52394c92so1002745ad.1 for ; Mon, 22 Jul 2024 14:58:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1721685510; x=1722290310; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=0LHskn70d2ksv6LHdkX1mJP86NW8JKXeHVtQxtRD63o=; b=fJ5IpWiXRnVXDY3Xg++9LJLG7yBPXM1L4muTzE18GNQbkwAHjENh3m5OP5xtN2UVlm nyIYjUnc1j14jUeu0j8EBZqukZdplribDPbxj9uTp3IIct/R/c580+DiRpb6tmmlzK1o wJGqT8ORnHekp5Dh7GMYiUiFZyU3oAj5zo+pGvgMllV912vfS+Z91jcE7hMlJcC0r0N4 qhGJNyPvVHEaP00+YadjpucSfJ0jptNIuGrppRYQlDUn/h6NpCgMl/v05S16ZiE5Q0VX m2hkgCr0erd+8qWsF3bxT9XM5YVDE9g7YLK5eFSMob76vjvqx7w2vqvA+MzAyyXRqDUh wyaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721685510; x=1722290310; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0LHskn70d2ksv6LHdkX1mJP86NW8JKXeHVtQxtRD63o=; b=DeP91gF+30PWj61U/9fCpqe1nZ/3JkdKJqpWwH306vIrTOru1FfYZytqt74n8N2RK1 EleC+vQsmbHc7gFsGEZcRf5ayzn23upY7cI24mSqTiPvLMGpp/lrrece38rA+eBr7HKc vdw/jM2NjsTnu452J4/pE7OmjtUqKa6vDiOXk1so3aTyLVTIOdeJhEeVDwkMj6Hgc5Dj dEbFBfoL5DZH/BS+UW+kEZlz0Vh6GCC2ChT5KavhUaAX/ymfNjBLvaDArxbSRewlmYf/ 22VSMh0kfFiC99/djYIo+z/248OrnR/qHsFKL5WQFx6XqLLj0Q+yKcn/OFA8/rISFpLk baxw== X-Forwarded-Encrypted: i=1; AJvYcCWsZ+/WKrO70ThJX9JtZ0jL+pllRmObtuEmYGv7jbpewU+289WyawLB6CdvUogfgkBUWiQw8iVaiC1s0sqgeKuOZdmp7h+H9Skk2Y1+ X-Gm-Message-State: AOJu0Yy5N+tYPI6AQ4MWXRSIaXHf9576sxwWIGfKssh/wndsKgwmFU7c LrkIU5unvi0sbI/cXhg01A4HinKf1COcErHvDUN+R9pTrW/96bl/thKL/uS5oME= X-Google-Smtp-Source: AGHT+IHd+2bB4yQUH4+GuARmHkySKcbsdc55uuRZE454T1+R3ecnFnM5LkLIXssH0xJnbAHEgzvaBg== X-Received: by 2002:a17:902:dacb:b0:1fd:8f66:b06c with SMTP id d9443c01a7336-1fdb5feee06mr5863175ad.46.1721685510328; Mon, 22 Jul 2024 14:58:30 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fd6f44f0d4sm59997775ad.219.2024.07.22.14.58.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jul 2024 14:58:29 -0700 (PDT) From: Charlie Jenkins Date: Mon, 22 Jul 2024 14:58:13 -0700 Subject: [PATCH v6 09/13] riscv: vector: Support xtheadvector save/restore Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240722-xtheadvector-v6-9-c9af0130fa00@rivosinc.com> References: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com> In-Reply-To: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins , Conor Dooley X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721685488; l=18546; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=TwA0gwFg2vgNEL89uxalGbRfzdlmmPfjJ4oKZqlRd+A=; b=eWG4feYK4MKca9vV40X/v/NdTyYSO3Dwp9RwFkQxCN32gff7IU56MOKvckm3xnbzJItbeBHck EqieXM26NpBDek5CmycDHbxXvVZGw445oyGxzBnB4TIWhBdAaFaW6xr X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Use alternatives to add support for xtheadvector vector save/restore routines. Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley --- arch/riscv/include/asm/csr.h | 6 + arch/riscv/include/asm/switch_to.h | 2 +- arch/riscv/include/asm/vector.h | 223 +++++++++++++++++++++++++----= ---- arch/riscv/kernel/cpufeature.c | 5 +- arch/riscv/kernel/kernel_mode_vector.c | 8 +- arch/riscv/kernel/process.c | 4 +- arch/riscv/kernel/signal.c | 6 +- arch/riscv/kernel/vector.c | 12 +- 8 files changed, 196 insertions(+), 70 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index c0a60c4ed911..b4b3fcb1d142 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -30,6 +30,12 @@ #define SR_VS_CLEAN _AC(0x00000400, UL) #define SR_VS_DIRTY _AC(0x00000600, UL) =20 +#define SR_VS_THEAD _AC(0x01800000, UL) /* xtheadvector Status */ +#define SR_VS_OFF_THEAD _AC(0x00000000, UL) +#define SR_VS_INITIAL_THEAD _AC(0x00800000, UL) +#define SR_VS_CLEAN_THEAD _AC(0x01000000, UL) +#define SR_VS_DIRTY_THEAD _AC(0x01800000, UL) + #define SR_XS _AC(0x00018000, UL) /* Extension Status */ #define SR_XS_OFF _AC(0x00000000, UL) #define SR_XS_INITIAL _AC(0x00008000, UL) diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/sw= itch_to.h index 7594df37cc9f..f9cbebe372b8 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -99,7 +99,7 @@ do { \ __set_prev_cpu(__prev->thread); \ if (has_fpu()) \ __switch_to_fpu(__prev, __next); \ - if (has_vector()) \ + if (has_vector() || has_xtheadvector()) \ __switch_to_vector(__prev, __next); \ if (switch_to_should_flush_icache(__next)) \ local_flush_icache_all(); \ diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vecto= r.h index be7d309cca8a..5f70c403f14f 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -18,6 +18,27 @@ #include #include #include +#include +#include +#include + +#define __riscv_v_vstate_or(_val, TYPE) ({ \ + typeof(_val) _res =3D _val; \ + if (has_xtheadvector()) \ + _res =3D (_res & ~SR_VS_THEAD) | SR_VS_##TYPE##_THEAD; \ + else \ + _res =3D (_res & ~SR_VS) | SR_VS_##TYPE; \ + _res; \ +}) + +#define __riscv_v_vstate_check(_val, TYPE) ({ \ + bool _res; \ + if (has_xtheadvector()) \ + _res =3D ((_val) & SR_VS_THEAD) =3D=3D SR_VS_##TYPE##_THEAD; \ + else \ + _res =3D ((_val) & SR_VS) =3D=3D SR_VS_##TYPE; \ + _res; \ +}) =20 extern unsigned long riscv_v_vsize; int riscv_v_setup_vsize(void); @@ -40,39 +61,62 @@ static __always_inline bool has_vector(void) return riscv_has_extension_unlikely(RISCV_ISA_EXT_ZVE32X); } =20 +static __always_inline bool has_xtheadvector_no_alternatives(void) +{ + if (IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR)) + return riscv_isa_vendor_extension_available(THEAD_VENDOR_ID, XTHEADVECTO= R); + else + return false; +} + +static __always_inline bool has_xtheadvector(void) +{ + if (IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR)) + return riscv_has_vendor_extension_unlikely(THEAD_VENDOR_ID, + RISCV_ISA_VENDOR_EXT_XTHEADVECTOR); + else + return false; +} + static inline void __riscv_v_vstate_clean(struct pt_regs *regs) { - regs->status =3D (regs->status & ~SR_VS) | SR_VS_CLEAN; + regs->status =3D __riscv_v_vstate_or(regs->status, CLEAN); } =20 static inline void __riscv_v_vstate_dirty(struct pt_regs *regs) { - regs->status =3D (regs->status & ~SR_VS) | SR_VS_DIRTY; + regs->status =3D __riscv_v_vstate_or(regs->status, DIRTY); } =20 static inline void riscv_v_vstate_off(struct pt_regs *regs) { - regs->status =3D (regs->status & ~SR_VS) | SR_VS_OFF; + regs->status =3D __riscv_v_vstate_or(regs->status, OFF); } =20 static inline void riscv_v_vstate_on(struct pt_regs *regs) { - regs->status =3D (regs->status & ~SR_VS) | SR_VS_INITIAL; + regs->status =3D __riscv_v_vstate_or(regs->status, INITIAL); } =20 static inline bool riscv_v_vstate_query(struct pt_regs *regs) { - return (regs->status & SR_VS) !=3D 0; + return !__riscv_v_vstate_check(regs->status, OFF); } =20 static __always_inline void riscv_v_enable(void) { - csr_set(CSR_SSTATUS, SR_VS); + if (has_xtheadvector()) + csr_set(CSR_SSTATUS, SR_VS_THEAD); + else + csr_set(CSR_SSTATUS, SR_VS); } =20 static __always_inline void riscv_v_disable(void) { - csr_clear(CSR_SSTATUS, SR_VS); + if (has_xtheadvector()) + csr_clear(CSR_SSTATUS, SR_VS_THEAD); + else + csr_clear(CSR_SSTATUS, SR_VS); } =20 static __always_inline void __vstate_csr_save(struct __riscv_v_ext_state *= dest) @@ -81,10 +125,36 @@ static __always_inline void __vstate_csr_save(struct _= _riscv_v_ext_state *dest) "csrr %0, " __stringify(CSR_VSTART) "\n\t" "csrr %1, " __stringify(CSR_VTYPE) "\n\t" "csrr %2, " __stringify(CSR_VL) "\n\t" - "csrr %3, " __stringify(CSR_VCSR) "\n\t" - "csrr %4, " __stringify(CSR_VLENB) "\n\t" : "=3Dr" (dest->vstart), "=3Dr" (dest->vtype), "=3Dr" (dest->vl), - "=3Dr" (dest->vcsr), "=3Dr" (dest->vlenb) : :); + "=3Dr" (dest->vcsr) : :); + + if (has_xtheadvector()) { + unsigned long status; + + /* + * CSR_VCSR is defined as + * [2:1] - vxrm[1:0] + * [0] - vxsat + * The earlier vector spec implemented by T-Head uses separate + * registers for the same bit-elements, so just combine those + * into the existing output field. + * + * Additionally T-Head cores need FS to be enabled when accessing + * the VXRM and VXSAT CSRs, otherwise ending in illegal instructions. + * Though the cores do not implement the VXRM and VXSAT fields in the + * FCSR CSR that vector-0.7.1 specifies. + */ + status =3D csr_read_set(CSR_STATUS, SR_FS_DIRTY); + dest->vcsr =3D csr_read(CSR_VXSAT) | csr_read(CSR_VXRM) << CSR_VXRM_SHIF= T; + + dest->vlenb =3D riscv_v_vsize / 32; + + if ((status & SR_FS) !=3D SR_FS_DIRTY) + csr_write(CSR_STATUS, status); + } else { + dest->vcsr =3D csr_read(CSR_VCSR); + dest->vlenb =3D csr_read(CSR_VLENB); + } } =20 static __always_inline void __vstate_csr_restore(struct __riscv_v_ext_stat= e *src) @@ -95,9 +165,25 @@ static __always_inline void __vstate_csr_restore(struct= __riscv_v_ext_state *src "vsetvl x0, %2, %1\n\t" ".option pop\n\t" "csrw " __stringify(CSR_VSTART) ", %0\n\t" - "csrw " __stringify(CSR_VCSR) ", %3\n\t" - : : "r" (src->vstart), "r" (src->vtype), "r" (src->vl), - "r" (src->vcsr) :); + : : "r" (src->vstart), "r" (src->vtype), "r" (src->vl)); + + if (has_xtheadvector()) { + unsigned long status =3D csr_read(CSR_SSTATUS); + + /* + * Similar to __vstate_csr_save above, restore values for the + * separate VXRM and VXSAT CSRs from the vcsr variable. + */ + status =3D csr_read_set(CSR_STATUS, SR_FS_DIRTY); + + csr_write(CSR_VXRM, (src->vcsr >> CSR_VXRM_SHIFT) & CSR_VXRM_MASK); + csr_write(CSR_VXSAT, src->vcsr & CSR_VXSAT_MASK); + + if ((status & SR_FS) !=3D SR_FS_DIRTY) + csr_write(CSR_STATUS, status); + } else { + csr_write(CSR_VCSR, src->vcsr); + } } =20 static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_= to, @@ -107,19 +193,33 @@ static inline void __riscv_v_vstate_save(struct __ris= cv_v_ext_state *save_to, =20 riscv_v_enable(); __vstate_csr_save(save_to); - asm volatile ( - ".option push\n\t" - ".option arch, +zve32x\n\t" - "vsetvli %0, x0, e8, m8, ta, ma\n\t" - "vse8.v v0, (%1)\n\t" - "add %1, %1, %0\n\t" - "vse8.v v8, (%1)\n\t" - "add %1, %1, %0\n\t" - "vse8.v v16, (%1)\n\t" - "add %1, %1, %0\n\t" - "vse8.v v24, (%1)\n\t" - ".option pop\n\t" - : "=3D&r" (vl) : "r" (datap) : "memory"); + if (has_xtheadvector()) { + asm volatile ( + "mv t0, %0\n\t" + THEAD_VSETVLI_T4X0E8M8D1 + THEAD_VSB_V_V0T0 + "add t0, t0, t4\n\t" + THEAD_VSB_V_V0T0 + "add t0, t0, t4\n\t" + THEAD_VSB_V_V0T0 + "add t0, t0, t4\n\t" + THEAD_VSB_V_V0T0 + : : "r" (datap) : "memory", "t0", "t4"); + } else { + asm volatile ( + ".option push\n\t" + ".option arch, +zve32x\n\t" + "vsetvli %0, x0, e8, m8, ta, ma\n\t" + "vse8.v v0, (%1)\n\t" + "add %1, %1, %0\n\t" + "vse8.v v8, (%1)\n\t" + "add %1, %1, %0\n\t" + "vse8.v v16, (%1)\n\t" + "add %1, %1, %0\n\t" + "vse8.v v24, (%1)\n\t" + ".option pop\n\t" + : "=3D&r" (vl) : "r" (datap) : "memory"); + } riscv_v_disable(); } =20 @@ -129,28 +229,51 @@ static inline void __riscv_v_vstate_restore(struct __= riscv_v_ext_state *restore_ unsigned long vl; =20 riscv_v_enable(); - asm volatile ( - ".option push\n\t" - ".option arch, +zve32x\n\t" - "vsetvli %0, x0, e8, m8, ta, ma\n\t" - "vle8.v v0, (%1)\n\t" - "add %1, %1, %0\n\t" - "vle8.v v8, (%1)\n\t" - "add %1, %1, %0\n\t" - "vle8.v v16, (%1)\n\t" - "add %1, %1, %0\n\t" - "vle8.v v24, (%1)\n\t" - ".option pop\n\t" - : "=3D&r" (vl) : "r" (datap) : "memory"); + if (has_xtheadvector()) { + asm volatile ( + "mv t0, %0\n\t" + THEAD_VSETVLI_T4X0E8M8D1 + THEAD_VLB_V_V0T0 + "add t0, t0, t4\n\t" + THEAD_VLB_V_V0T0 + "add t0, t0, t4\n\t" + THEAD_VLB_V_V0T0 + "add t0, t0, t4\n\t" + THEAD_VLB_V_V0T0 + : : "r" (datap) : "memory", "t0", "t4"); + } else { + asm volatile ( + ".option push\n\t" + ".option arch, +zve32x\n\t" + "vsetvli %0, x0, e8, m8, ta, ma\n\t" + "vle8.v v0, (%1)\n\t" + "add %1, %1, %0\n\t" + "vle8.v v8, (%1)\n\t" + "add %1, %1, %0\n\t" + "vle8.v v16, (%1)\n\t" + "add %1, %1, %0\n\t" + "vle8.v v24, (%1)\n\t" + ".option pop\n\t" + : "=3D&r" (vl) : "r" (datap) : "memory"); + } __vstate_csr_restore(restore_from); riscv_v_disable(); } =20 static inline void __riscv_v_vstate_discard(void) { - unsigned long vl, vtype_inval =3D 1UL << (BITS_PER_LONG - 1); + unsigned long vtype_inval =3D 1UL << (BITS_PER_LONG - 1); =20 riscv_v_enable(); + if (has_xtheadvector()) + asm volatile (THEAD_VSETVLI_X0X0E8M8D1); + else + asm volatile ( + ".option push\n\t" + ".option arch, +v\n\t" + "vsetvli x0, x0, e8, m8, ta, ma\n\t" + ".option pop\n\t"); + asm volatile ( ".option push\n\t" ".option arch, +zve32x\n\t" @@ -159,25 +282,25 @@ static inline void __riscv_v_vstate_discard(void) "vmv.v.i v8, -1\n\t" "vmv.v.i v16, -1\n\t" "vmv.v.i v24, -1\n\t" - "vsetvl %0, x0, %1\n\t" + "vsetvl x0, x0, %0\n\t" ".option pop\n\t" - : "=3D&r" (vl) : "r" (vtype_inval) : "memory"); + : : "r" (vtype_inval)); + riscv_v_disable(); } =20 static inline void riscv_v_vstate_discard(struct pt_regs *regs) { - if ((regs->status & SR_VS) =3D=3D SR_VS_OFF) - return; - - __riscv_v_vstate_discard(); - __riscv_v_vstate_dirty(regs); + if (riscv_v_vstate_query(regs)) { + __riscv_v_vstate_discard(); + __riscv_v_vstate_dirty(regs); + } } =20 static inline void riscv_v_vstate_save(struct __riscv_v_ext_state *vstate, struct pt_regs *regs) { - if ((regs->status & SR_VS) =3D=3D SR_VS_DIRTY) { + if (__riscv_v_vstate_check(regs->status, DIRTY)) { __riscv_v_vstate_save(vstate, vstate->datap); __riscv_v_vstate_clean(regs); } @@ -186,7 +309,7 @@ static inline void riscv_v_vstate_save(struct __riscv_v= _ext_state *vstate, static inline void riscv_v_vstate_restore(struct __riscv_v_ext_state *vsta= te, struct pt_regs *regs) { - if ((regs->status & SR_VS) !=3D SR_VS_OFF) { + if (riscv_v_vstate_query(regs)) { __riscv_v_vstate_restore(vstate, vstate->datap); __riscv_v_vstate_clean(regs); } @@ -195,7 +318,7 @@ static inline void riscv_v_vstate_restore(struct __risc= v_v_ext_state *vstate, static inline void riscv_v_vstate_set_restore(struct task_struct *task, struct pt_regs *regs) { - if ((regs->status & SR_VS) !=3D SR_VS_OFF) { + if (riscv_v_vstate_query(regs)) { set_tsk_thread_flag(task, TIF_RISCV_V_DEFER_RESTORE); riscv_v_vstate_on(regs); } diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index bf25215bad24..cb48092fdc5d 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -845,10 +845,7 @@ static int __init riscv_fill_hwcap_from_ext_list(unsig= ned long *isa2hwcap) riscv_isa_set_ext(ext, source_isa); } =20 -<<<<<<< HEAD riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap); -=3D=3D=3D=3D=3D=3D=3D ->>>>>>> 0f260ac829ca (riscv: Extend cpufeature.c to detect vendor extensio= ns) riscv_fill_cpu_vendor_ext(cpu_node, cpu); =20 of_node_put(cpu_node); @@ -928,7 +925,7 @@ void __init riscv_fill_hwcap(void) elf_hwcap &=3D ~COMPAT_HWCAP_ISA_F; } =20 - if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ZVE32X)) { + if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ZVE32X) || has_xt= headvector_no_alternatives()) { /* * This cannot fail when called on the boot hart */ diff --git a/arch/riscv/kernel/kernel_mode_vector.c b/arch/riscv/kernel/ker= nel_mode_vector.c index 6afe80c7f03a..99972a48e86b 100644 --- a/arch/riscv/kernel/kernel_mode_vector.c +++ b/arch/riscv/kernel/kernel_mode_vector.c @@ -143,7 +143,7 @@ static int riscv_v_start_kernel_context(bool *is_nested) =20 /* Transfer the ownership of V from user to kernel, then save */ riscv_v_start(RISCV_PREEMPT_V | RISCV_PREEMPT_V_DIRTY); - if ((task_pt_regs(current)->status & SR_VS) =3D=3D SR_VS_DIRTY) { + if (__riscv_v_vstate_check(task_pt_regs(current)->status, DIRTY)) { uvstate =3D ¤t->thread.vstate; __riscv_v_vstate_save(uvstate, uvstate->datap); } @@ -160,7 +160,7 @@ asmlinkage void riscv_v_context_nesting_start(struct pt= _regs *regs) return; =20 depth =3D riscv_v_ctx_get_depth(); - if (depth =3D=3D 0 && (regs->status & SR_VS) =3D=3D SR_VS_DIRTY) + if (depth =3D=3D 0 && __riscv_v_vstate_check(regs->status, DIRTY)) riscv_preempt_v_set_dirty(); =20 riscv_v_ctx_depth_inc(); @@ -208,7 +208,7 @@ void kernel_vector_begin(void) { bool nested =3D false; =20 - if (WARN_ON(!has_vector())) + if (WARN_ON(!(has_vector() || has_xtheadvector()))) return; =20 BUG_ON(!may_use_simd()); @@ -236,7 +236,7 @@ EXPORT_SYMBOL_GPL(kernel_vector_begin); */ void kernel_vector_end(void) { - if (WARN_ON(!has_vector())) + if (WARN_ON(!(has_vector() || has_xtheadvector()))) return; =20 riscv_v_disable(); diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index e4bc61c4e58a..191023decd16 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -176,7 +176,7 @@ void flush_thread(void) void arch_release_task_struct(struct task_struct *tsk) { /* Free the vector context of datap. */ - if (has_vector()) + if (has_vector() || has_xtheadvector()) riscv_v_thread_free(tsk); } =20 @@ -222,7 +222,7 @@ int copy_thread(struct task_struct *p, const struct ker= nel_clone_args *args) p->thread.s[0] =3D 0; } p->thread.riscv_v_flags =3D 0; - if (has_vector()) + if (has_vector() || has_xtheadvector()) riscv_v_thread_alloc(p); p->thread.ra =3D (unsigned long)ret_from_fork; p->thread.sp =3D (unsigned long)childregs; /* kernel sp */ diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index 5a2edd7f027e..1d5e4b3ca9e1 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -189,7 +189,7 @@ static long restore_sigcontext(struct pt_regs *regs, =20 return 0; case RISCV_V_MAGIC: - if (!has_vector() || !riscv_v_vstate_query(regs) || + if (!(has_vector() || has_xtheadvector()) || !riscv_v_vstate_query(regs= ) || size !=3D riscv_v_sc_size) return -EINVAL; =20 @@ -211,7 +211,7 @@ static size_t get_rt_frame_size(bool cal_all) =20 frame_size =3D sizeof(*frame); =20 - if (has_vector()) { + if (has_vector() || has_xtheadvector()) { if (cal_all || riscv_v_vstate_query(task_pt_regs(current))) total_context_size +=3D riscv_v_sc_size; } @@ -284,7 +284,7 @@ static long setup_sigcontext(struct rt_sigframe __user = *frame, if (has_fpu()) err |=3D save_fp_state(regs, &sc->sc_fpregs); /* Save the vector state. */ - if (has_vector() && riscv_v_vstate_query(regs)) + if ((has_vector() || has_xtheadvector()) && riscv_v_vstate_query(regs)) err |=3D save_v_state(regs, (void __user **)&sc_ext_ptr); /* Write zero to fp-reserved space and check it on restore_sigcontext */ err |=3D __put_user(0, &sc->sc_extdesc.reserved); diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c index 9775d6a9c8ee..f3e1de574050 100644 --- a/arch/riscv/kernel/vector.c +++ b/arch/riscv/kernel/vector.c @@ -63,7 +63,7 @@ int riscv_v_setup_vsize(void) =20 void __init riscv_v_setup_ctx_cache(void) { - if (!has_vector()) + if (!(has_vector() || has_xtheadvector())) return; =20 riscv_v_user_cachep =3D kmem_cache_create_usercopy("riscv_vector_ctx", @@ -183,7 +183,7 @@ bool riscv_v_first_use_handler(struct pt_regs *regs) u32 __user *epc =3D (u32 __user *)regs->epc; u32 insn =3D (u32)regs->badaddr; =20 - if (!has_vector()) + if (!(has_vector() || has_xtheadvector())) return false; =20 /* Do not handle if V is not supported, or disabled */ @@ -226,7 +226,7 @@ void riscv_v_vstate_ctrl_init(struct task_struct *tsk) bool inherit; int cur, next; =20 - if (!has_vector()) + if (!(has_vector() || has_xtheadvector())) return; =20 next =3D riscv_v_ctrl_get_next(tsk); @@ -248,7 +248,7 @@ void riscv_v_vstate_ctrl_init(struct task_struct *tsk) =20 long riscv_v_vstate_ctrl_get_current(void) { - if (!has_vector()) + if (!(has_vector() || has_xtheadvector())) return -EINVAL; =20 return current->thread.vstate_ctrl & PR_RISCV_V_VSTATE_CTRL_MASK; @@ -259,7 +259,7 @@ long riscv_v_vstate_ctrl_set_current(unsigned long arg) bool inherit; int cur, next; =20 - if (!has_vector()) + if (!(has_vector() || has_xtheadvector())) return -EINVAL; =20 if (arg & ~PR_RISCV_V_VSTATE_CTRL_MASK) @@ -309,7 +309,7 @@ static struct ctl_table riscv_v_default_vstate_table[] = =3D { =20 static int __init riscv_v_sysctl_init(void) { - if (has_vector()) + if (has_vector() || has_xtheadvector()) if (!register_sysctl("abi", riscv_v_default_vstate_table)) return -EINVAL; return 0; --=20 2.44.0 From nobody Tue Dec 16 19:40:49 2025 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1759E12E1DE for ; Mon, 22 Jul 2024 21:58:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721685515; cv=none; b=fVGZi7fMb003bOnhZ0p3ohgG8JYz7/2aZXt2+B86gPbKo3xukCzVyQMWn4JLiS/EuU6EaOrV2Hgq+Gp1VKKWT0XD12BLJnS7ufr0xJNwNtM/arWDGoC6RlajDk8gxM/DgqsCW55vDdVTaQtcaapgWmRo4OhU1357mn6WaBjEd+8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721685515; c=relaxed/simple; bh=Q43N1SzZuoUs9V4odMuGerUQldvvnFwkFkU8sDA49Kg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QlT5tu9sr5sVzevLT1NaFBrjPieLwqCOBiAjHdyZ1k6Xnd6v3IjRCpYB1brD+MRzBvLdwSYMcIApShNygGtyzqobwQA9Est1q4Lh1YSYOuBFhpiTUJNrFeC1JjVBdZ24d5zkSg++jvmn/bH+I09CRi442RC6RaFV5+KOLzFvMXo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=gWPrDRKE; arc=none smtp.client-ip=209.85.214.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="gWPrDRKE" Received: by mail-pl1-f178.google.com with SMTP id d9443c01a7336-1fc5296e214so37088495ad.0 for ; Mon, 22 Jul 2024 14:58:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1721685512; x=1722290312; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=JiHGX7WHPh3w54Ho6DWi1K3xQlJp39Igxk9RjCMoL4E=; b=gWPrDRKEZvvL07PvLlFVC32ONnLCcGsO2B5Zj1txjGvA0ZMiUymHc2Hsm8/uryffOc 1gbZaQnO9+a/PDqnjAz2WHoFZ6S7ARHIHeUMwr9aUnp5J347CkJtBUgrmV2XFH3kHJ2V aJRyt6DZP1lcoboDjZ7KN1jAyD0fHdkjta9DqXmhAZPMJjqygQD4li2+Bni2vpCGjYIu IOVglYbJGKXBNEr0rWpUIH/xINCyGvvzXOxiedWYqeByyurQbRTtVE3FlNvkLtFwcQ9z BtJuoGwilhGK918olTfZWCqs/SDfVCGMdZwqbW/6xVwNcO6tT8tYCRc+7WxKckaoZWFT 1cfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721685512; x=1722290312; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JiHGX7WHPh3w54Ho6DWi1K3xQlJp39Igxk9RjCMoL4E=; b=WSl5FrRvRekDKA3Zb+WAVNEyGZhh/4HHuBtrjh5xNvpiCWOTYc+q8G+gHofmRVzovf 7ZcAf0JtHU/+U55zrv7JotwvoaaWcqYiFT/WI94ja22JC3ZQ59X6rTWGEu9OlZaO/ThV 14sKsW6QwK5vOutP5HQXBYOBoIWqN5fA2qxiLXucIa8c49OcEyTmfCuJ1ZgM5hAjnj1u J5lBJwsUIMjncAW3Q+l8JRcdK/Lp3wYi5aFrlEqduHqQyN606pUUi5D2N33R/UpiImYN OSNlre788z3msYWUab3O//gfZFLAXEZZZhVb4C9i7lbAazSdyfN82TgJa7HY4+9D8GOK HEew== X-Forwarded-Encrypted: i=1; AJvYcCXsGmEfGrLfJZ06UWjpG6l0BM8zCTwTH+5+e/ge7b9JwjaZoKxm4KLvs+IA3vdFzeSje+yEgkgyvLNvstxz49SGS0UEuAIg9Luv5D/h X-Gm-Message-State: AOJu0YyYMg91V6ICKKRhP1xOBC5ghhLEuMlaTEjDJH3hSIwadtl5mdL+ F7N5T9DyjdwKzecxsKEhDW09X+pkjGK8+6mERUZZLkA5784baFi163evEo+ixZ4= X-Google-Smtp-Source: AGHT+IEdsdhJWEQPBzdYx9IL+EfvpGKXZrni+QDvCGGbFZ3XsYrJhCOmvtJGjQ4CJxajBqfPKGvCgw== X-Received: by 2002:a17:903:228d:b0:1fb:4a68:b7bf with SMTP id d9443c01a7336-1fd745f8208mr89218265ad.45.1721685512419; Mon, 22 Jul 2024 14:58:32 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fd6f44f0d4sm59997775ad.219.2024.07.22.14.58.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jul 2024 14:58:31 -0700 (PDT) From: Charlie Jenkins Date: Mon, 22 Jul 2024 14:58:14 -0700 Subject: [PATCH v6 10/13] riscv: hwprobe: Add thead vendor extension probing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240722-xtheadvector-v6-10-c9af0130fa00@rivosinc.com> References: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com> In-Reply-To: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721685488; l=7556; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=Q43N1SzZuoUs9V4odMuGerUQldvvnFwkFkU8sDA49Kg=; b=yzrDPPB9EC21rOZcxR3ZD6AwSKUv6A6pfJ9JQFHZwdvHz0FrBtAEQXJR1iDKWCkgCTntwYjkV IVRKB8lbdBYAkipZ/cC+v1pnpz0DDqDt4NvWh058sutbPPXBe6DDJmx X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0" which allows userspace to probe for the new RISCV_ISA_VENDOR_EXT_XTHEADVECTOR vendor extension. This new key will allow userspace code to probe for which thead vendor extensions are supported. This API is modeled to be consistent with RISCV_HWPROBE_KEY_IMA_EXT_0. The bitmask returned will have each bit corresponding to a supported thead vendor extension of the cpumask set. Just like RISCV_HWPROBE_KEY_IMA_EXT_0, this allows a userspace program to determine all of the supported thead vendor extensions in one call. Signed-off-by: Charlie Jenkins Reviewed-by: Evan Green --- arch/riscv/include/asm/hwprobe.h | 5 +-- .../include/asm/vendor_extensions/thead_hwprobe.h | 18 +++++++++++ .../include/asm/vendor_extensions/vendor_hwprobe.h | 37 ++++++++++++++++++= ++++ arch/riscv/include/uapi/asm/hwprobe.h | 3 +- arch/riscv/include/uapi/asm/vendor/thead.h | 3 ++ arch/riscv/kernel/sys_hwprobe.c | 5 +++ arch/riscv/kernel/vendor_extensions/Makefile | 1 + .../riscv/kernel/vendor_extensions/thead_hwprobe.c | 19 +++++++++++ 8 files changed, 88 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwpr= obe.h index 150a9877b0af..6148e1eab64c 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* - * Copyright 2023 Rivos, Inc + * Copyright 2023-2024 Rivos, Inc */ =20 #ifndef _ASM_HWPROBE_H @@ -8,7 +8,7 @@ =20 #include =20 -#define RISCV_HWPROBE_MAX_KEY 7 +#define RISCV_HWPROBE_MAX_KEY 8 =20 static inline bool riscv_hwprobe_key_is_valid(__s64 key) { @@ -21,6 +21,7 @@ static inline bool hwprobe_key_is_bitmask(__s64 key) case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: case RISCV_HWPROBE_KEY_IMA_EXT_0: case RISCV_HWPROBE_KEY_CPUPERF_0: + case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0: return true; } =20 diff --git a/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h b/arc= h/riscv/include/asm/vendor_extensions/thead_hwprobe.h new file mode 100644 index 000000000000..925fef39a2c0 --- /dev/null +++ b/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_HWPROBE_H +#define _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_HWPROBE_H + +#include + +#include + +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD +void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const stru= ct cpumask *cpus); +#else +static inline void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pa= ir, const struct cpumask *cpus) +{ + pair->value =3D 0; +} +#endif + +#endif diff --git a/arch/riscv/include/asm/vendor_extensions/vendor_hwprobe.h b/ar= ch/riscv/include/asm/vendor_extensions/vendor_hwprobe.h new file mode 100644 index 000000000000..f28f31e19cda --- /dev/null +++ b/arch/riscv/include/asm/vendor_extensions/vendor_hwprobe.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2024 Rivos, Inc + */ + +#ifndef _ASM_RISCV_SYS_HWPROBE_H +#define _ASM_RISCV_SYS_HWPROBE_H + +#include + +#define VENDOR_EXT_KEY(ext) \ + do { \ + if (__riscv_isa_extension_available(isainfo->isa, RISCV_ISA_VENDOR_EXT_#= #ext)) \ + pair->value |=3D RISCV_HWPROBE_VENDOR_EXT_##ext; \ + else \ + missing |=3D RISCV_HWPROBE_VENDOR_EXT_##ext; \ + } while (false) + +/* + * Loop through and record extensions that 1) anyone has, and 2) anyone + * doesn't have. + * + * _extension_checks is an arbitrary C block to set the values of pair->va= lue + * and missing. It should be filled with VENDOR_EXT_KEY expressions. + */ +#define VENDOR_EXTENSION_SUPPORTED(pair, cpus, per_hart_vendor_bitmap, _ex= tension_checks) \ + do { \ + int cpu; \ + u64 missing; \ + for_each_cpu(cpu, (cpus)) { \ + struct riscv_isavendorinfo *isainfo =3D &(per_hart_vendor_bitmap)[cpu];= \ + _extension_checks \ + } \ + (pair)->value &=3D ~missing; \ + } while (false) \ + +#endif /* _ASM_RISCV_SYS_HWPROBE_H */ diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 8b8f6ac0eae2..73ab65ac8c55 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* - * Copyright 2023 Rivos, Inc + * Copyright 2023-2024 Rivos, Inc */ =20 #ifndef _UAPI_ASM_HWPROBE_H @@ -81,6 +81,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6 #define RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS 7 +#define RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 8 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ =20 /* Flags */ diff --git a/arch/riscv/include/uapi/asm/vendor/thead.h b/arch/riscv/includ= e/uapi/asm/vendor/thead.h new file mode 100644 index 000000000000..43790ebe5faf --- /dev/null +++ b/arch/riscv/include/uapi/asm/vendor/thead.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ + +#define RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR (1 << 0) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprob= e.c index 685594769535..4cecdb0249a2 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -14,6 +14,7 @@ #include #include #include +#include #include =20 =20 @@ -237,6 +238,10 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pai= r, pair->value =3D user_max_virt_addr(); break; =20 + case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0: + hwprobe_isa_vendor_ext_thead_0(pair, cpus); + break; + /* * For forward compatibility, unknown keys don't fail the whole * call, but get their element key set to -1 and value set to 0 diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kern= el/vendor_extensions/Makefile index 353522cb3bf0..866414c81a9f 100644 --- a/arch/riscv/kernel/vendor_extensions/Makefile +++ b/arch/riscv/kernel/vendor_extensions/Makefile @@ -2,3 +2,4 @@ =20 obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) +=3D andes.o obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) +=3D thead.o +obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) +=3D thead_hwprobe.o diff --git a/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c b/arch/ris= cv/kernel/vendor_extensions/thead_hwprobe.c new file mode 100644 index 000000000000..2eba34011786 --- /dev/null +++ b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include + +#include +#include + +#include +#include + +void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const stru= ct cpumask *cpus) +{ + VENDOR_EXTENSION_SUPPORTED(pair, cpus, + riscv_isa_vendor_ext_list_thead.per_hart_isa_bitmap, { + VENDOR_EXT_KEY(XTHEADVECTOR); + }); +} --=20 2.44.0 From nobody Tue Dec 16 19:40:49 2025 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2768C12F59F for ; Mon, 22 Jul 2024 21:58:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721685517; cv=none; b=o63zs/uk/ZbdyqfA5AaVsKHB3OUNzVFkqKvoTP49Y52Ydk4tL0uAP3QEgEUTtDV/dF7ysnRVBhQ+sG3spnCOjrY+unurI6XhepGLVakjnZd4dTH0AAUttqW6qwgevrF1WcSXN9ayT5K74P30F2oubeJGkFsovH90uc35sv6duck= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721685517; c=relaxed/simple; bh=2W48pS8YjVGGuKgFcdTY4JQ+czvhIHjQutLR0sMQn0M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hySo9ZrDFAIo9muWxVzQEaXR5LKKSu9a32xf/qMJzLFcid6+gAjM/5u4h5u2XxpPX1+qFee9CaS4rPxRDEUPsaEyXVZ6kIg8vY/AlJoY9zlRBEcldGoWqHp/7QhuMFeBS4AKzA5kaHhBTPJmjg5cmWR01uPAtAJkqpRejLT/pY8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=IVj5AfRZ; arc=none smtp.client-ip=209.85.214.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="IVj5AfRZ" Received: by mail-pl1-f171.google.com with SMTP id d9443c01a7336-1fd90c2fc68so1053155ad.1 for ; Mon, 22 Jul 2024 14:58:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1721685514; x=1722290314; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=RFlUlKNClOcGHl95zNXTKC1SKxBdILei2erBqjtymyU=; b=IVj5AfRZu/xl7bgcSOgxCbzP1gLxKk5b1Stz6U14Ov9GJkA2eKb8ORYQzrQlsenJsc xXmrtGKbwrpo51Iz7RctzKJki//rYI4XbDnOkwq0/EU2AXcKko1yl4A0e6oP24NPXgow Ec6wU1OM7RHABUGBrOE0wp56nBAKHr4P7SsFHyOGG0EOd64N9S9FhFOPD6rZ3DPZLujB KrbuzqfTeXN3hT5vqUk63iarSs4n+7QADow70cdXjGdTmvhMkxUYpsS0RfmgZyw2+xsK 247eH9wtfJFtnOQshzx0cjxxqhVP1jOopnwIgYcDVVqUAykFIVwG7hhtwjHDHlfuIA7n lG5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721685514; x=1722290314; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RFlUlKNClOcGHl95zNXTKC1SKxBdILei2erBqjtymyU=; b=rm/sECHtYMSNqEGq/vbyMXoTjhkl6besbLVXAe7+imjyl8SEjuMmT+sTM623ytgOR1 L6DU4k2jBYdG4m7K20IM0nfXp6v4s9oNQXkKH3YcAm5Ua45myk0x1d6Kg8tRY339Te7p 7P/q6vPAFnC9nk5kGyd19oPuz8oDv/VCqr8hPIjBBC67MJ1uPjwtC7eqYwHVWPupJzYs ip7k5i+yFdOwmnxjWKFJiT/dIpIzTNLMs7TNJcy6XoDWHQQGJ3N+K+Vfg/1aUrjYAPBM yODKe/XfJuGCXEmbWkbsM8F9GEt8N+qhkb7daY0KIq0C4PtXuQvTbezyk9ZDcFqbYVYp xBSA== X-Forwarded-Encrypted: i=1; AJvYcCUOtUjlRg1BU6kAOAfHDaup797SLVAG/RHg7sdRdhFTprS3Z3Ew+j8iDuM+duXI7JQwLNhhfmD1KmRzxCNdwTVIG+VRyc3ovpHT8qWk X-Gm-Message-State: AOJu0YzC6gl7Y3yTRuZdCz0vcYpWLA6A4B19SjcFQtStgc6xStt3vVo+ NunK44KzTRCJ5UTWamRbP0KWizTUWBKCKVfo7lFGcQ/Q6tirwrNR/qWLsxrD7bw= X-Google-Smtp-Source: AGHT+IFmou8rSkO/pXeWqn5Y08peXHpQQZJpzoyKzV+g8WtXw8VSsTRAbxkcuTo+xUK5I20cnMuzOQ== X-Received: by 2002:a17:902:ec83:b0:1fc:2e38:d3de with SMTP id d9443c01a7336-1fdb5eb14a7mr13001095ad.7.1721685514562; Mon, 22 Jul 2024 14:58:34 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fd6f44f0d4sm59997775ad.219.2024.07.22.14.58.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jul 2024 14:58:33 -0700 (PDT) From: Charlie Jenkins Date: Mon, 22 Jul 2024 14:58:15 -0700 Subject: [PATCH v6 11/13] riscv: hwprobe: Document thead vendor extensions and xtheadvector extension Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240722-xtheadvector-v6-11-c9af0130fa00@rivosinc.com> References: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com> In-Reply-To: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721685488; l=1260; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=2W48pS8YjVGGuKgFcdTY4JQ+czvhIHjQutLR0sMQn0M=; b=RiMnA1+g5SPgw4LGch5qdpL5lwgJZjDhU+TTicDgiDFxBQRLn7rxsOmNZM3sDkGgoWCnfcU5S OXvLmirQIGQCTiByNpwWBWeN+HWIBf63huJ7QRj0Q5MhE6xaF+q7Esq X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Document support for thead vendor extensions using the key RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 and xtheadvector extension using the key RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR. Signed-off-by: Charlie Jenkins Reviewed-by: Evan Green --- Documentation/arch/riscv/hwprobe.rst | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index 02eb4d98b7de..b48a06ef80e0 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -264,3 +264,13 @@ The following keys are defined: =20 * :c:macro:`RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS`: An unsigned long which represent the highest userspace virtual address usable. + +* :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0`: A bitmask containing the + thead vendor extensions that are compatible with the + :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior. + + * T-HEAD + + * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR`: The xtheadvector v= endor + extension is supported in the T-Head ISA extensions spec starting = from + commit a18c801634 ("Add T-Head VECTOR vendor extension. "). --=20 2.44.0 From nobody Tue Dec 16 19:40:49 2025 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6568B12FB0B for ; Mon, 22 Jul 2024 21:58:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721685520; cv=none; b=jQ0nZOmoDmMFxFCqp91LCGSRsD84GruLqyB+/fLKgBZQuyOZpmF18vqD9owqon3MzvGBhZ+IurBhy26hAMOAIiYhwf4BLfDoNE6p4O4wQVeOJ0D4E0bqKXMKGcRnrkpaXUu4GZJOgIHXonJ/EmvzjWvS0hc9jeQ6bBXgmxwqO2s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721685520; c=relaxed/simple; bh=EXw1RBuJ59Tg4rj85+XXNcoIvGx1Jn6m8cyQI0zqsoM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Vh2SUkNnxmWFlS4FV3XQjc2zP47WRuPs9ZMQYiIgKE58zJcmyF7zQnCSV0Gf1VfZaM3M12a0CeIbPj1rLGvpCptmucKvz0gwwqmcZdBScryfObAOA7+G1HxLJ8ICSPF7Fx5LrhTt2pTwJ2vWi2Pei39I2VmaKr+QAth/xkHc814= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=St8BjSrA; arc=none smtp.client-ip=209.85.214.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="St8BjSrA" Received: by mail-pl1-f175.google.com with SMTP id d9443c01a7336-1fd69e44596so1392565ad.1 for ; Mon, 22 Jul 2024 14:58:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1721685517; x=1722290317; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=/L7Xs95ZIB/cJfs55CP6x6VOhLtGqbuGQanL+c2GDEI=; b=St8BjSrAbhttTNW3GyNnd7sCkRc4eG+vWG1LecTWa0e0YNHGTDi23iGlBfwpOhMTi8 9WY0Mm5+5u36e/TVSOX9KwX1fECrStgCzdLDxNA9ttWn6LYmtQGEeey1/Zl6jI/mVVbC jMw6eZozoOZ+Ibfv7PShhAGg7dG1EdeQ3cRNP57eKI9J9U7I9qeXAE29a+7yh6Jq94SM YhyiMXQyymEOlQuAlrn2Ymr2Z6hZsU90qTj0oB7ijP2xxBmFf55aTK4CIEqYWkQm6yRg b8efkPoqsTl3FvUVfEM4xVLlsA7em3yTZs8ogrU3BKRPx2JfqE0Dq1/nuRs4fQarqf75 d4lA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721685517; x=1722290317; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/L7Xs95ZIB/cJfs55CP6x6VOhLtGqbuGQanL+c2GDEI=; b=oymGAF8WvzFGI//2p61T6p3yRCaE3mM57Jb7PTMZ+VtJb1StJwW52oR0M7tnFpwsl4 41UalXZw7B/oEzXmRiXnQMcNDBvBB+ZddX7QA+lAPHNs4c3J8TrnSObcjeJzaqpfYGwV KzRJJkfp9IcG5XD2N+A4UfEtiNa/IlcqSGYLf3G0MoQPGVM61KFY1qRR7vdPyiOujBj0 Ry7SruT6iAHVcb5vIiEvo05K0RLksl5E87CyoB4I/JTW1vlynY3s9QfMyFrpbUwFy+uM h+VdOkp3SUvY0Vwqn/GrR0dfMbrx7A5nX2LYAF1w52eyrpK0B92W4Bl40l80I4nBMpuO j+gA== X-Forwarded-Encrypted: i=1; AJvYcCVNKAGFn/paCzWX0feBV/9VmXbgKINIcmm7z8Ek8q+1ejGNEHIz6hzjOSQTIkDFaGBFfCPJMI+98YYadW/M28zmI2UOY1nM48tOWZ/k X-Gm-Message-State: AOJu0Yy/e+/UsPZHOVAmELLsjuaPmF7D+dTipxDWE02AvXR6V+tUeLfu +7dgYIMAUtx+oRg7vQkPRcJ1c9GJIZFWT4MjnFx0QzdmW5WvNtp9HtWG0l/T/2M= X-Google-Smtp-Source: AGHT+IG750GiKdS/h6ska19fW6qthgYcXL84MPVtxz3YdbkhfvB0peQKLX2OoOIQzAdrHS3aHFoBtQ== X-Received: by 2002:a17:903:2bcc:b0:1fc:60c3:7b3 with SMTP id d9443c01a7336-1fdb95816d7mr3219945ad.25.1721685516769; Mon, 22 Jul 2024 14:58:36 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fd6f44f0d4sm59997775ad.219.2024.07.22.14.58.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jul 2024 14:58:35 -0700 (PDT) From: Charlie Jenkins Date: Mon, 22 Jul 2024 14:58:16 -0700 Subject: [PATCH v6 12/13] selftests: riscv: Fix vector tests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240722-xtheadvector-v6-12-c9af0130fa00@rivosinc.com> References: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com> In-Reply-To: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721685488; l=19714; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=EXw1RBuJ59Tg4rj85+XXNcoIvGx1Jn6m8cyQI0zqsoM=; b=sxUR71YXab9xgYxOYSf9A2DWy12MjTgAXNQ+LNZxs3iSnnkSZyhEO7h+Y3ixcRHA9dsrZf+C7 IZeTx5LkE+CBC1U13Grfns7E4qiWG7lregK68T3VF96BBZoq9mbohfZ X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Overhaul the riscv vector tests to use kselftest_harness to help the test cases correctly report the results and decouple the individual test cases from each other. With this refactoring, only run the test cases is vector is reported and properly report the test case as skipped otherwise. The v_initval_nolibc test was previously not checking if vector was supported and used a function (malloc) which invalidates the state of the vector registers. Signed-off-by: Charlie Jenkins --- tools/testing/selftests/riscv/vector/.gitignore | 3 +- tools/testing/selftests/riscv/vector/Makefile | 17 +- .../selftests/riscv/vector/v_exec_initval_nolibc.c | 84 +++++++ tools/testing/selftests/riscv/vector/v_helpers.c | 57 +++++ tools/testing/selftests/riscv/vector/v_helpers.h | 6 + tools/testing/selftests/riscv/vector/v_initval.c | 16 ++ .../selftests/riscv/vector/v_initval_nolibc.c | 68 ------ .../testing/selftests/riscv/vector/vstate_prctl.c | 266 ++++++++++++-----= ---- 8 files changed, 326 insertions(+), 191 deletions(-) diff --git a/tools/testing/selftests/riscv/vector/.gitignore b/tools/testin= g/selftests/riscv/vector/.gitignore index 9ae7964491d5..7d9c87cd0649 100644 --- a/tools/testing/selftests/riscv/vector/.gitignore +++ b/tools/testing/selftests/riscv/vector/.gitignore @@ -1,3 +1,4 @@ vstate_exec_nolibc vstate_prctl -v_initval_nolibc +v_initval +v_exec_initval_nolibc diff --git a/tools/testing/selftests/riscv/vector/Makefile b/tools/testing/= selftests/riscv/vector/Makefile index bfff0ff4f3be..995746359477 100644 --- a/tools/testing/selftests/riscv/vector/Makefile +++ b/tools/testing/selftests/riscv/vector/Makefile @@ -2,18 +2,27 @@ # Copyright (C) 2021 ARM Limited # Originally tools/testing/arm64/abi/Makefile =20 -TEST_GEN_PROGS :=3D vstate_prctl v_initval_nolibc -TEST_GEN_PROGS_EXTENDED :=3D vstate_exec_nolibc +TEST_GEN_PROGS :=3D v_initval vstate_prctl +TEST_GEN_PROGS_EXTENDED :=3D vstate_exec_nolibc v_exec_initval_nolibc sys_= hwprobe.o v_helpers.o =20 include ../../lib.mk =20 -$(OUTPUT)/vstate_prctl: vstate_prctl.c ../hwprobe/sys_hwprobe.S +$(OUTPUT)/sys_hwprobe.o: ../hwprobe/sys_hwprobe.S + $(CC) -static -c -o$@ $(CFLAGS) $^ + +$(OUTPUT)/v_helpers.o: v_helpers.c + $(CC) -static -c -o$@ $(CFLAGS) $^ + +$(OUTPUT)/vstate_prctl: vstate_prctl.c $(OUTPUT)/sys_hwprobe.o $(OUTPUT)/v= _helpers.o $(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^ =20 $(OUTPUT)/vstate_exec_nolibc: vstate_exec_nolibc.c $(CC) -nostdlib -static -include ../../../../include/nolibc/nolibc.h \ -Wall $(CFLAGS) $(LDFLAGS) $^ -o $@ -lgcc =20 -$(OUTPUT)/v_initval_nolibc: v_initval_nolibc.c +$(OUTPUT)/v_initval: v_initval.c $(OUTPUT)/sys_hwprobe.o $(OUTPUT)/v_helpe= rs.o + $(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^ + +$(OUTPUT)/v_exec_initval_nolibc: v_exec_initval_nolibc.c $(CC) -nostdlib -static -include ../../../../include/nolibc/nolibc.h \ -Wall $(CFLAGS) $(LDFLAGS) $^ -o $@ -lgcc diff --git a/tools/testing/selftests/riscv/vector/v_exec_initval_nolibc.c b= /tools/testing/selftests/riscv/vector/v_exec_initval_nolibc.c new file mode 100644 index 000000000000..74b13806baf0 --- /dev/null +++ b/tools/testing/selftests/riscv/vector/v_exec_initval_nolibc.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Get values of vector registers as soon as the program starts to test if + * is properly cleaning the values before starting a new program. Vector + * registers are caller saved, so no function calls may happen before read= ing + * the values. To further ensure consistency, this file is compiled without + * libc and without auto-vectorization. + * + * To be "clean" all values must be either all ones or all zeroes. + */ + +#define __stringify_1(x...) #x +#define __stringify(x...) __stringify_1(x) + +int main(int argc, char **argv) +{ + char prev_value =3D 0, value; + unsigned long vl; + int first =3D 1; + + asm volatile ( + ".option push\n\t" + ".option arch, +v\n\t" + "vsetvli %[vl], x0, e8, m1, ta, ma\n\t" + ".option pop\n\t" + : [vl] "=3Dr" (vl) + ); + +#define CHECK_VECTOR_REGISTER(register) ({ \ + for (int i =3D 0; i < vl; i++) { \ + asm volatile ( \ + ".option push\n\t" \ + ".option arch, +v\n\t" \ + "vmv.x.s %0, " __stringify(register) "\n\t" \ + "vsrl.vi " __stringify(register) ", " __stringify(register) ", 8\n\t" \ + ".option pop\n\t" \ + : "=3Dr" (value)); \ + if (first) { \ + first =3D 0; \ + } else if (value !=3D prev_value || !(value =3D=3D 0x00 || value =3D=3D = 0xff)) { \ + printf("Register " __stringify(register) " values not clean! value: %u\= n", value); \ + exit(-1); \ + } \ + prev_value =3D value; \ + } \ +}) + + CHECK_VECTOR_REGISTER(v0); + CHECK_VECTOR_REGISTER(v1); + CHECK_VECTOR_REGISTER(v2); + CHECK_VECTOR_REGISTER(v3); + CHECK_VECTOR_REGISTER(v4); + CHECK_VECTOR_REGISTER(v5); + CHECK_VECTOR_REGISTER(v6); + CHECK_VECTOR_REGISTER(v7); + CHECK_VECTOR_REGISTER(v8); + CHECK_VECTOR_REGISTER(v9); + CHECK_VECTOR_REGISTER(v10); + CHECK_VECTOR_REGISTER(v11); + CHECK_VECTOR_REGISTER(v12); + CHECK_VECTOR_REGISTER(v13); + CHECK_VECTOR_REGISTER(v14); + CHECK_VECTOR_REGISTER(v15); + CHECK_VECTOR_REGISTER(v16); + CHECK_VECTOR_REGISTER(v17); + CHECK_VECTOR_REGISTER(v18); + CHECK_VECTOR_REGISTER(v19); + CHECK_VECTOR_REGISTER(v20); + CHECK_VECTOR_REGISTER(v21); + CHECK_VECTOR_REGISTER(v22); + CHECK_VECTOR_REGISTER(v23); + CHECK_VECTOR_REGISTER(v24); + CHECK_VECTOR_REGISTER(v25); + CHECK_VECTOR_REGISTER(v26); + CHECK_VECTOR_REGISTER(v27); + CHECK_VECTOR_REGISTER(v28); + CHECK_VECTOR_REGISTER(v29); + CHECK_VECTOR_REGISTER(v30); + CHECK_VECTOR_REGISTER(v31); + +#undef CHECK_VECTOR_REGISTER + + return 0; +} diff --git a/tools/testing/selftests/riscv/vector/v_helpers.c b/tools/testi= ng/selftests/riscv/vector/v_helpers.c new file mode 100644 index 000000000000..d50f4dfbf9e5 --- /dev/null +++ b/tools/testing/selftests/riscv/vector/v_helpers.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "../hwprobe/hwprobe.h" +#include +#include +#include +#include +#include + +bool is_vector_supported(void) +{ + struct riscv_hwprobe pair; + + pair.key =3D RISCV_HWPROBE_KEY_IMA_EXT_0; + riscv_hwprobe(&pair, 1, 0, NULL, 0); + return pair.value & RISCV_HWPROBE_EXT_ZVE32X; +} + +int launch_test(char *next_program, int test_inherit) +{ + char *exec_argv[3], *exec_envp[1]; + int rc, pid, status; + + pid =3D fork(); + if (pid < 0) { + printf("fork failed %d", pid); + return -1; + } + + if (!pid) { + exec_argv[0] =3D next_program; + exec_argv[1] =3D test_inherit !=3D 0 ? "x" : NULL; + exec_argv[2] =3D NULL; + exec_envp[0] =3D NULL; + /* launch the program again to check inherit */ + rc =3D execve(next_program, exec_argv, exec_envp); + if (rc) { + perror("execve"); + printf("child execve failed %d\n", rc); + exit(-1); + } + } + + rc =3D waitpid(-1, &status, 0); + if (rc < 0) { + printf("waitpid failed\n"); + return -3; + } + + if ((WIFEXITED(status) && WEXITSTATUS(status) =3D=3D -1) || + WIFSIGNALED(status)) { + printf("child exited abnormally\n"); + return -4; + } + + return WEXITSTATUS(status); +} diff --git a/tools/testing/selftests/riscv/vector/v_helpers.h b/tools/testi= ng/selftests/riscv/vector/v_helpers.h new file mode 100644 index 000000000000..faeeeb625b6e --- /dev/null +++ b/tools/testing/selftests/riscv/vector/v_helpers.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include + +bool is_vector_supported(void); + +int launch_test(char *next_program, int test_inherit); diff --git a/tools/testing/selftests/riscv/vector/v_initval.c b/tools/testi= ng/selftests/riscv/vector/v_initval.c new file mode 100644 index 000000000000..f38b5797fa31 --- /dev/null +++ b/tools/testing/selftests/riscv/vector/v_initval.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "../../kselftest_harness.h" +#include "v_helpers.h" + +#define NEXT_PROGRAM "./v_exec_initval_nolibc" + +TEST(v_initval) +{ + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); + + ASSERT_EQ(0, launch_test(NEXT_PROGRAM, 0)); +} + +TEST_HARNESS_MAIN diff --git a/tools/testing/selftests/riscv/vector/v_initval_nolibc.c b/tool= s/testing/selftests/riscv/vector/v_initval_nolibc.c deleted file mode 100644 index 1dd94197da30..000000000000 --- a/tools/testing/selftests/riscv/vector/v_initval_nolibc.c +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include "../../kselftest.h" -#define MAX_VSIZE (8192 * 32) - -void dump(char *ptr, int size) -{ - int i =3D 0; - - for (i =3D 0; i < size; i++) { - if (i !=3D 0) { - if (i % 16 =3D=3D 0) - printf("\n"); - else if (i % 8 =3D=3D 0) - printf(" "); - } - printf("%02x ", ptr[i]); - } - printf("\n"); -} - -int main(void) -{ - int i; - unsigned long vl; - char *datap, *tmp; - - datap =3D malloc(MAX_VSIZE); - if (!datap) { - ksft_test_result_fail("fail to allocate memory for size =3D %d\n", MAX_V= SIZE); - exit(-1); - } - - tmp =3D datap; - asm volatile ( - ".option push\n\t" - ".option arch, +v\n\t" - "vsetvli %0, x0, e8, m8, ta, ma\n\t" - "vse8.v v0, (%2)\n\t" - "add %1, %2, %0\n\t" - "vse8.v v8, (%1)\n\t" - "add %1, %1, %0\n\t" - "vse8.v v16, (%1)\n\t" - "add %1, %1, %0\n\t" - "vse8.v v24, (%1)\n\t" - ".option pop\n\t" - : "=3D&r" (vl), "=3Dr" (tmp) : "r" (datap) : "memory"); - - ksft_print_msg("vl =3D %lu\n", vl); - - if (datap[0] !=3D 0x00 && datap[0] !=3D 0xff) { - ksft_test_result_fail("v-regesters are not properly initialized\n"); - dump(datap, vl * 4); - exit(-1); - } - - for (i =3D 1; i < vl * 4; i++) { - if (datap[i] !=3D datap[0]) { - ksft_test_result_fail("detect stale values on v-regesters\n"); - dump(datap, vl * 4); - exit(-2); - } - } - - free(datap); - ksft_exit_pass(); - return 0; -} diff --git a/tools/testing/selftests/riscv/vector/vstate_prctl.c b/tools/te= sting/selftests/riscv/vector/vstate_prctl.c index 895177f6bf4c..850a0caa226e 100644 --- a/tools/testing/selftests/riscv/vector/vstate_prctl.c +++ b/tools/testing/selftests/riscv/vector/vstate_prctl.c @@ -3,50 +3,13 @@ #include #include #include +#include +#include =20 -#include "../hwprobe/hwprobe.h" -#include "../../kselftest.h" +#include "../../kselftest_harness.h" +#include "v_helpers.h" =20 #define NEXT_PROGRAM "./vstate_exec_nolibc" -static int launch_test(int test_inherit) -{ - char *exec_argv[3], *exec_envp[1]; - int rc, pid, status; - - pid =3D fork(); - if (pid < 0) { - ksft_test_result_fail("fork failed %d", pid); - return -1; - } - - if (!pid) { - exec_argv[0] =3D NEXT_PROGRAM; - exec_argv[1] =3D test_inherit !=3D 0 ? "x" : NULL; - exec_argv[2] =3D NULL; - exec_envp[0] =3D NULL; - /* launch the program again to check inherit */ - rc =3D execve(NEXT_PROGRAM, exec_argv, exec_envp); - if (rc) { - perror("execve"); - ksft_test_result_fail("child execve failed %d\n", rc); - exit(-1); - } - } - - rc =3D waitpid(-1, &status, 0); - if (rc < 0) { - ksft_test_result_fail("waitpid failed\n"); - return -3; - } - - if ((WIFEXITED(status) && WEXITSTATUS(status) =3D=3D -1) || - WIFSIGNALED(status)) { - ksft_test_result_fail("child exited abnormally\n"); - return -4; - } - - return WEXITSTATUS(status); -} =20 int test_and_compare_child(long provided, long expected, int inherit) { @@ -54,14 +17,13 @@ int test_and_compare_child(long provided, long expected= , int inherit) =20 rc =3D prctl(PR_RISCV_V_SET_CONTROL, provided); if (rc !=3D 0) { - ksft_test_result_fail("prctl with provided arg %lx failed with code %d\n= ", - provided, rc); + printf("prctl with provided arg %lx failed with code %d\n", + provided, rc); return -1; } - rc =3D launch_test(inherit); + rc =3D launch_test(NEXT_PROGRAM, inherit); if (rc !=3D expected) { - ksft_test_result_fail("Test failed, check %d !=3D %ld\n", rc, - expected); + printf("Test failed, check %d !=3D %ld\n", rc, expected); return -2; } return 0; @@ -70,112 +32,180 @@ int test_and_compare_child(long provided, long expect= ed, int inherit) #define PR_RISCV_V_VSTATE_CTRL_CUR_SHIFT 0 #define PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT 2 =20 -int main(void) +TEST(get_control_no_v) { - struct riscv_hwprobe pair; - long flag, expected; long rc; =20 - pair.key =3D RISCV_HWPROBE_KEY_IMA_EXT_0; - rc =3D riscv_hwprobe(&pair, 1, 0, NULL, 0); - if (rc < 0) { - ksft_test_result_fail("hwprobe() failed with %ld\n", rc); - return -1; - } + if (is_vector_supported()) + SKIP(return, "Test expects vector to be not supported"); =20 - if (pair.key !=3D RISCV_HWPROBE_KEY_IMA_EXT_0) { - ksft_test_result_fail("hwprobe cannot probe RISCV_HWPROBE_KEY_IMA_EXT_0\= n"); - return -2; - } + rc =3D prctl(PR_RISCV_V_GET_CONTROL); + EXPECT_EQ(-1, rc) TH_LOG("GET_CONTROL should fail on kernel/hw without ZV= E32X"); + EXPECT_EQ(EINVAL, errno) TH_LOG("GET_CONTROL should fail on kernel/hw wit= hout ZVE32X"); +} =20 - if (!(pair.value & RISCV_HWPROBE_EXT_ZVE32X)) { - rc =3D prctl(PR_RISCV_V_GET_CONTROL); - if (rc !=3D -1 || errno !=3D EINVAL) { - ksft_test_result_fail("GET_CONTROL should fail on kernel/hw without ZVE= 32X\n"); - return -3; - } - - rc =3D prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); - if (rc !=3D -1 || errno !=3D EINVAL) { - ksft_test_result_fail("SET_CONTROL should fail on kernel/hw without ZVE= 32X\n"); - return -4; - } - - ksft_test_result_skip("Vector not supported\n"); - return 0; - } +TEST(set_control_no_v) +{ + long rc; + + if (is_vector_supported()) + SKIP(return, "Test expects vector to be not supported"); + + rc =3D prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); + EXPECT_EQ(-1, rc) TH_LOG("SET_CONTROL should fail on kernel/hw without ZV= E32X"); + EXPECT_EQ(EINVAL, errno) TH_LOG("SET_CONTROL should fail on kernel/hw wit= hout ZVE32X"); +} + +TEST(vstate_on_current) +{ + long flag; + long rc; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 flag =3D PR_RISCV_V_VSTATE_CTRL_ON; rc =3D prctl(PR_RISCV_V_SET_CONTROL, flag); - if (rc !=3D 0) { - ksft_test_result_fail("Enabling V for current should always success\n"); - return -5; - } + EXPECT_EQ(0, rc) TH_LOG("Enabling V for current should always success"); +} + +TEST(vstate_off_eperm) +{ + long flag; + long rc; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 flag =3D PR_RISCV_V_VSTATE_CTRL_OFF; rc =3D prctl(PR_RISCV_V_SET_CONTROL, flag); - if (rc !=3D -1 || errno !=3D EPERM) { - ksft_test_result_fail("Disabling current's V alive must fail with EPERM(= %d)\n", - errno); - return -5; - } + EXPECT_EQ(EPERM, errno) TH_LOG("Disabling current's V alive must fail wit= h EPERM(%d)", errno); + EXPECT_EQ(-1, rc) TH_LOG("Disabling current's V alive must fail with EPER= M(%d)", errno); +} + +TEST(vstate_on_no_nesting) +{ + long flag; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 /* Turn on next's vector explicitly and test */ flag =3D PR_RISCV_V_VSTATE_CTRL_ON << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; - if (test_and_compare_child(flag, PR_RISCV_V_VSTATE_CTRL_ON, 0)) - return -6; + + EXPECT_EQ(0, test_and_compare_child(flag, PR_RISCV_V_VSTATE_CTRL_ON, 0)); +} + +TEST(vstate_off_nesting) +{ + long flag; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 /* Turn off next's vector explicitly and test */ flag =3D PR_RISCV_V_VSTATE_CTRL_OFF << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; - if (test_and_compare_child(flag, PR_RISCV_V_VSTATE_CTRL_OFF, 0)) - return -7; + + EXPECT_EQ(0, test_and_compare_child(flag, PR_RISCV_V_VSTATE_CTRL_OFF, 1)); +} + +TEST(vstate_on_inherit_no_nesting) +{ + long flag, expected; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); + + /* Turn on next's vector explicitly and test no inherit */ + flag =3D PR_RISCV_V_VSTATE_CTRL_ON << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; + flag |=3D PR_RISCV_V_VSTATE_CTRL_INHERIT; + expected =3D flag | PR_RISCV_V_VSTATE_CTRL_ON; + + EXPECT_EQ(0, test_and_compare_child(flag, expected, 0)); +} + +TEST(vstate_on_inherit) +{ + long flag, expected; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 /* Turn on next's vector explicitly and test inherit */ flag =3D PR_RISCV_V_VSTATE_CTRL_ON << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; flag |=3D PR_RISCV_V_VSTATE_CTRL_INHERIT; expected =3D flag | PR_RISCV_V_VSTATE_CTRL_ON; - if (test_and_compare_child(flag, expected, 0)) - return -8; =20 - if (test_and_compare_child(flag, expected, 1)) - return -9; + EXPECT_EQ(0, test_and_compare_child(flag, expected, 1)); +} + +TEST(vstate_off_inherit_no_nesting) +{ + long flag, expected; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); + + /* Turn off next's vector explicitly and test no inherit */ + flag =3D PR_RISCV_V_VSTATE_CTRL_OFF << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; + flag |=3D PR_RISCV_V_VSTATE_CTRL_INHERIT; + expected =3D flag | PR_RISCV_V_VSTATE_CTRL_OFF; + + EXPECT_EQ(0, test_and_compare_child(flag, expected, 0)); +} + +TEST(vstate_off_inherit) +{ + long flag, expected; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 /* Turn off next's vector explicitly and test inherit */ flag =3D PR_RISCV_V_VSTATE_CTRL_OFF << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; flag |=3D PR_RISCV_V_VSTATE_CTRL_INHERIT; expected =3D flag | PR_RISCV_V_VSTATE_CTRL_OFF; - if (test_and_compare_child(flag, expected, 0)) - return -10; =20 - if (test_and_compare_child(flag, expected, 1)) - return -11; + EXPECT_EQ(0, test_and_compare_child(flag, expected, 1)); +} + +/* arguments should fail with EINVAL */ +TEST(inval_set_control_1) +{ + int rc; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 - /* arguments should fail with EINVAL */ rc =3D prctl(PR_RISCV_V_SET_CONTROL, 0xff0); - if (rc !=3D -1 || errno !=3D EINVAL) { - ksft_test_result_fail("Undefined control argument should return EINVAL\n= "); - return -12; - } + EXPECT_EQ(-1, rc); + EXPECT_EQ(EINVAL, errno); +} + +/* arguments should fail with EINVAL */ +TEST(inval_set_control_2) +{ + int rc; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 rc =3D prctl(PR_RISCV_V_SET_CONTROL, 0x3); - if (rc !=3D -1 || errno !=3D EINVAL) { - ksft_test_result_fail("Undefined control argument should return EINVAL\n= "); - return -12; - } + EXPECT_EQ(-1, rc); + EXPECT_EQ(EINVAL, errno); +} =20 - rc =3D prctl(PR_RISCV_V_SET_CONTROL, 0xc); - if (rc !=3D -1 || errno !=3D EINVAL) { - ksft_test_result_fail("Undefined control argument should return EINVAL\n= "); - return -12; - } +/* arguments should fail with EINVAL */ +TEST(inval_set_control_3) +{ + int rc; =20 - rc =3D prctl(PR_RISCV_V_SET_CONTROL, 0xc); - if (rc !=3D -1 || errno !=3D EINVAL) { - ksft_test_result_fail("Undefined control argument should return EINVAL\n= "); - return -12; - } + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 - ksft_test_result_pass("tests for riscv_v_vstate_ctrl pass\n"); - ksft_exit_pass(); - return 0; + rc =3D prctl(PR_RISCV_V_SET_CONTROL, 0xc); + EXPECT_EQ(-1, rc); + EXPECT_EQ(EINVAL, errno); } + +TEST_HARNESS_MAIN --=20 2.44.0 From nobody Tue Dec 16 19:40:49 2025 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CCB313698F for ; Mon, 22 Jul 2024 21:58:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721685522; cv=none; b=cgva6E3eCYT6dkmOvoEKjl5gD1bgS6AoKCxkCtRtohYhzNhzjn66s58y2yYpWsZ+Q3Vajhs3VgMsS6AaqLqR59cf6KtiUluSrfAIXrZ53+kq5DgBpUT9sM2ARBzPcFqC8qh/TgM8d/B6QH8OJdxfNrfGAhqcSKp/iLqxmlk2Io0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721685522; c=relaxed/simple; bh=9w7dBpv+20Zqh2hfnY2iaYlSIT6IIR7L7F4Z0i1nJ5w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=txwZHgKpKNhmFBcHmYfch8Gl+f2z87eym4qoOOmcFx8a8Y8xDcXOU1A0ZAfZfNA465U7Tr5FFNS7OEtaYo5z4e9hylfAzkB8RjJ8gaZoxOUKhqYpcmHekkAK26wQ/09FJfc8YC5+CacNkis2Vk57NmuokupKYhQGGUGW/nB6i8s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=Cb4Fq9l1; arc=none smtp.client-ip=209.85.214.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="Cb4Fq9l1" Received: by mail-pl1-f175.google.com with SMTP id d9443c01a7336-1fd69e44596so1392885ad.1 for ; Mon, 22 Jul 2024 14:58:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1721685520; x=1722290320; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=9n2f4kq3fPmLVWerTpucYYwN/E7TPJTN4fKyHj2upcE=; b=Cb4Fq9l1vkJpr2XjiiXyHR38kC7KgCYOhXdbtyAJkR/RV2hiVuRNMkIL3Ua1a2SRPM McXIo9EVG7qqvBfeGBFmIN9ANFgzUypZPA1cYYVADpMGQTBqN8sUkQG34K8+Hl/CkhDN kE4dC5IuExYRQYL7MTiyeXcjRVbCeE3jOR83kJ/6GVgurWnkk1sDYvezShLJxGh5AysX 7st0hv63jW0FAPvaUoC6BtkmYSGbmqgWAQKjkiWKQVdFZ542Yz9xN/52gBINvn1GX1s2 GD1CTugYl54wuStvSwg2HGfuBw4929rsb0BmlfI7ymYZA7A64Q5/UEiCvzH2JyYscJKG Kadw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721685520; x=1722290320; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9n2f4kq3fPmLVWerTpucYYwN/E7TPJTN4fKyHj2upcE=; b=TmfxDFFj4fq0sqIoNeo6yoW0WZLZZUFVs8ne7L+uLXfmOT6hTjj0F1tpbNjxtT71kY 2ZIdhh5jaBglXTH3QDtfHe3IeBC1PAzOK9Rmr2YKp0yYNzeMPnfACkOe8AIwZVby1dhN VL0hnqp2DQSnWnIPvQ6qvQynNspjctEqkET2R6IfMdwmIOyXBfmm0gVF+6WoBxHvp7Yz DxkCWxWcDndyahJuPRhXMlbCi/blAM5TiPXyKLnCDiAg+zLaAFBGpR/CLERFgLE24EFY UMzRPb4K+wjWycxozazT6M3Ndu7SzopyFmW1+O7PtgUceh4jmujO424SZdBZzuNHS6dJ j1pQ== X-Forwarded-Encrypted: i=1; AJvYcCUrLagzceBi3zPdkY+xj9Lk9O7Iu4rkSrdmbjxyQBtzEXkQDQoOIjIJrMvKsvsfRshFCJSU93KqT60ZDF2RwM8PqgxFhzQgKHiT7mH5 X-Gm-Message-State: AOJu0Yzcn1pxzn5VRsEOH7LPdwOTJqEOdtQdQecMUh9VhgjQe4RqJNe9 lK06iA3UaPbl1BbQRz4qMN4JXozGLPHUFQeI6XgucMv+xGjB1lZudPAF1CcXjwc= X-Google-Smtp-Source: AGHT+IEipqL0Jie3CAThhg3jGrU5PbyaQcRxDMLegrJgL59LFBLDyj5WwZp8YAKwMZOHl6ED3DzrlA== X-Received: by 2002:a17:902:c411:b0:1fd:65ad:d8a1 with SMTP id d9443c01a7336-1fdb9581671mr2739985ad.21.1721685518835; Mon, 22 Jul 2024 14:58:38 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fd6f44f0d4sm59997775ad.219.2024.07.22.14.58.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jul 2024 14:58:38 -0700 (PDT) From: Charlie Jenkins Date: Mon, 22 Jul 2024 14:58:17 -0700 Subject: [PATCH v6 13/13] selftests: riscv: Support xtheadvector in vector tests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240722-xtheadvector-v6-13-c9af0130fa00@rivosinc.com> References: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com> In-Reply-To: <20240722-xtheadvector-v6-0-c9af0130fa00@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721685488; l=13279; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=9w7dBpv+20Zqh2hfnY2iaYlSIT6IIR7L7F4Z0i1nJ5w=; b=0YMmpOGaS7oZHo/sNXHwzUGlBKOrsCApVVvHth9llhrg5Op2Xq33tE9qMXr8lWPmoauJahaNI ExK5NhUCkzqCMGeXKyaxd15fGW3z+LZcuFtCuvEEKQQC722azM7eLsE X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Extend existing vector tests to be compatible with the xtheadvector instructions. Signed-off-by: Charlie Jenkins --- .../selftests/riscv/vector/v_exec_initval_nolibc.c | 23 ++++-- tools/testing/selftests/riscv/vector/v_helpers.c | 17 +++- tools/testing/selftests/riscv/vector/v_helpers.h | 4 +- tools/testing/selftests/riscv/vector/v_initval.c | 12 ++- .../selftests/riscv/vector/vstate_exec_nolibc.c | 20 +++-- .../testing/selftests/riscv/vector/vstate_prctl.c | 91 ++++++++++++++----= ---- 6 files changed, 115 insertions(+), 52 deletions(-) diff --git a/tools/testing/selftests/riscv/vector/v_exec_initval_nolibc.c b= /tools/testing/selftests/riscv/vector/v_exec_initval_nolibc.c index 74b13806baf0..6f40c2acc0c2 100644 --- a/tools/testing/selftests/riscv/vector/v_exec_initval_nolibc.c +++ b/tools/testing/selftests/riscv/vector/v_exec_initval_nolibc.c @@ -18,13 +18,22 @@ int main(int argc, char **argv) unsigned long vl; int first =3D 1; =20 - asm volatile ( - ".option push\n\t" - ".option arch, +v\n\t" - "vsetvli %[vl], x0, e8, m1, ta, ma\n\t" - ".option pop\n\t" - : [vl] "=3Dr" (vl) - ); + if (argc > 2 && strcmp(argv[2], "x")) + asm volatile ( + // 0 | zimm[10:0] | rs1 | 1 1 1 | rd |1010111| vsetvli + // vsetvli t4, x0, e8, m1, d1 + ".4byte 0b00000000000000000111111011010111\n\t" + "mv %[vl], t4\n\t" + : [vl] "=3Dr" (vl) : : "t4" + ); + else + asm volatile ( + ".option push\n\t" + ".option arch, +v\n\t" + "vsetvli %[vl], x0, e8, m1, ta, ma\n\t" + ".option pop\n\t" + : [vl] "=3Dr" (vl) + ); =20 #define CHECK_VECTOR_REGISTER(register) ({ \ for (int i =3D 0; i < vl; i++) { \ diff --git a/tools/testing/selftests/riscv/vector/v_helpers.c b/tools/testi= ng/selftests/riscv/vector/v_helpers.c index d50f4dfbf9e5..01a8799dcb78 100644 --- a/tools/testing/selftests/riscv/vector/v_helpers.c +++ b/tools/testing/selftests/riscv/vector/v_helpers.c @@ -1,12 +1,22 @@ // SPDX-License-Identifier: GPL-2.0-only =20 #include "../hwprobe/hwprobe.h" +#include #include #include #include #include #include =20 +bool is_xtheadvector_supported(void) +{ + struct riscv_hwprobe pair; + + pair.key =3D RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0; + riscv_hwprobe(&pair, 1, 0, NULL, 0); + return pair.value & RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR; +} + bool is_vector_supported(void) { struct riscv_hwprobe pair; @@ -16,9 +26,9 @@ bool is_vector_supported(void) return pair.value & RISCV_HWPROBE_EXT_ZVE32X; } =20 -int launch_test(char *next_program, int test_inherit) +int launch_test(char *next_program, int test_inherit, int xtheadvector) { - char *exec_argv[3], *exec_envp[1]; + char *exec_argv[4], *exec_envp[1]; int rc, pid, status; =20 pid =3D fork(); @@ -30,7 +40,8 @@ int launch_test(char *next_program, int test_inherit) if (!pid) { exec_argv[0] =3D next_program; exec_argv[1] =3D test_inherit !=3D 0 ? "x" : NULL; - exec_argv[2] =3D NULL; + exec_argv[2] =3D xtheadvector !=3D 0 ? "x" : NULL; + exec_argv[3] =3D NULL; exec_envp[0] =3D NULL; /* launch the program again to check inherit */ rc =3D execve(next_program, exec_argv, exec_envp); diff --git a/tools/testing/selftests/riscv/vector/v_helpers.h b/tools/testi= ng/selftests/riscv/vector/v_helpers.h index faeeeb625b6e..763cddfe26da 100644 --- a/tools/testing/selftests/riscv/vector/v_helpers.h +++ b/tools/testing/selftests/riscv/vector/v_helpers.h @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include =20 +bool is_xtheadvector_supported(void); + bool is_vector_supported(void); =20 -int launch_test(char *next_program, int test_inherit); +int launch_test(char *next_program, int test_inherit, int xtheadvector); diff --git a/tools/testing/selftests/riscv/vector/v_initval.c b/tools/testi= ng/selftests/riscv/vector/v_initval.c index f38b5797fa31..be9e1d18ad29 100644 --- a/tools/testing/selftests/riscv/vector/v_initval.c +++ b/tools/testing/selftests/riscv/vector/v_initval.c @@ -7,10 +7,16 @@ =20 TEST(v_initval) { - if (!is_vector_supported()) - SKIP(return, "Vector not supported"); + int xtheadvector =3D 0; =20 - ASSERT_EQ(0, launch_test(NEXT_PROGRAM, 0)); + if (!is_vector_supported()) { + if (is_xtheadvector_supported()) + xtheadvector =3D 1; + else + SKIP(return, "Vector not supported"); + } + + ASSERT_EQ(0, launch_test(NEXT_PROGRAM, 0, xtheadvector)); } =20 TEST_HARNESS_MAIN diff --git a/tools/testing/selftests/riscv/vector/vstate_exec_nolibc.c b/to= ols/testing/selftests/riscv/vector/vstate_exec_nolibc.c index 1f9969bed235..7b7d6f21acb4 100644 --- a/tools/testing/selftests/riscv/vector/vstate_exec_nolibc.c +++ b/tools/testing/selftests/riscv/vector/vstate_exec_nolibc.c @@ -6,13 +6,16 @@ =20 int main(int argc, char **argv) { - int rc, pid, status, test_inherit =3D 0; + int rc, pid, status, test_inherit =3D 0, xtheadvector =3D 0; long ctrl, ctrl_c; char *exec_argv[2], *exec_envp[2]; =20 - if (argc > 1) + if (argc > 1 && strcmp(argv[1], "x")) test_inherit =3D 1; =20 + if (argc > 2 && strcmp(argv[2], "x")) + xtheadvector =3D 1; + ctrl =3D my_syscall1(__NR_prctl, PR_RISCV_V_GET_CONTROL); if (ctrl < 0) { puts("PR_RISCV_V_GET_CONTROL is not supported\n"); @@ -53,11 +56,14 @@ int main(int argc, char **argv) puts("child's vstate_ctrl not equal to parent's\n"); exit(-1); } - asm volatile (".option push\n\t" - ".option arch, +v\n\t" - "vsetvli x0, x0, e32, m8, ta, ma\n\t" - ".option pop\n\t" - ); + if (xtheadvector) + asm volatile (".4byte 0x00007ed7"); + else + asm volatile (".option push\n\t" + ".option arch, +v\n\t" + "vsetvli x0, x0, e32, m8, ta, ma\n\t" + ".option pop\n\t" + ); exit(ctrl); } } diff --git a/tools/testing/selftests/riscv/vector/vstate_prctl.c b/tools/te= sting/selftests/riscv/vector/vstate_prctl.c index 850a0caa226e..3d79f266cc65 100644 --- a/tools/testing/selftests/riscv/vector/vstate_prctl.c +++ b/tools/testing/selftests/riscv/vector/vstate_prctl.c @@ -11,7 +11,7 @@ =20 #define NEXT_PROGRAM "./vstate_exec_nolibc" =20 -int test_and_compare_child(long provided, long expected, int inherit) +int test_and_compare_child(long provided, long expected, int inherit, int = xtheadvector) { int rc; =20 @@ -21,7 +21,7 @@ int test_and_compare_child(long provided, long expected, = int inherit) provided, rc); return -1; } - rc =3D launch_test(NEXT_PROGRAM, inherit); + rc =3D launch_test(NEXT_PROGRAM, inherit, xtheadvector); if (rc !=3D expected) { printf("Test failed, check %d !=3D %ld\n", rc, expected); return -2; @@ -36,7 +36,7 @@ TEST(get_control_no_v) { long rc; =20 - if (is_vector_supported()) + if (is_vector_supported() || is_xtheadvector_supported()) SKIP(return, "Test expects vector to be not supported"); =20 rc =3D prctl(PR_RISCV_V_GET_CONTROL); @@ -48,7 +48,7 @@ TEST(set_control_no_v) { long rc; =20 - if (is_vector_supported()) + if (is_vector_supported() || is_xtheadvector_supported()) SKIP(return, "Test expects vector to be not supported"); =20 rc =3D prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); @@ -61,12 +61,12 @@ TEST(vstate_on_current) long flag; long rc; =20 - if (!is_vector_supported()) + if (!is_vector_supported() && !is_xtheadvector_supported()) SKIP(return, "Vector not supported"); =20 flag =3D PR_RISCV_V_VSTATE_CTRL_ON; rc =3D prctl(PR_RISCV_V_SET_CONTROL, flag); - EXPECT_EQ(0, rc) TH_LOG("Enabling V for current should always success"); + EXPECT_EQ(0, rc) TH_LOG("Enabling V for current should always succeed"); } =20 TEST(vstate_off_eperm) @@ -74,99 +74,128 @@ TEST(vstate_off_eperm) long flag; long rc; =20 - if (!is_vector_supported()) + if (!is_vector_supported() && !is_xtheadvector_supported()) SKIP(return, "Vector not supported"); =20 flag =3D PR_RISCV_V_VSTATE_CTRL_OFF; rc =3D prctl(PR_RISCV_V_SET_CONTROL, flag); - EXPECT_EQ(EPERM, errno) TH_LOG("Disabling current's V alive must fail wit= h EPERM(%d)", errno); - EXPECT_EQ(-1, rc) TH_LOG("Disabling current's V alive must fail with EPER= M(%d)", errno); + EXPECT_EQ(EPERM, errno) TH_LOG("Disabling V in current thread with V enab= led must fail with EPERM(%d)", errno); + EXPECT_EQ(-1, rc) TH_LOG("Disabling V in current thread with V enabled mu= st fail with EPERM(%d)", errno); } =20 TEST(vstate_on_no_nesting) { long flag; + int xtheadvector =3D 0; =20 - if (!is_vector_supported()) - SKIP(return, "Vector not supported"); + if (!is_vector_supported()) { + if (is_xtheadvector_supported()) + xtheadvector =3D 1; + else + SKIP(return, "Vector not supported"); + } =20 /* Turn on next's vector explicitly and test */ flag =3D PR_RISCV_V_VSTATE_CTRL_ON << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; =20 - EXPECT_EQ(0, test_and_compare_child(flag, PR_RISCV_V_VSTATE_CTRL_ON, 0)); + EXPECT_EQ(0, test_and_compare_child(flag, PR_RISCV_V_VSTATE_CTRL_ON, 0, x= theadvector)); } =20 TEST(vstate_off_nesting) { long flag; + int xtheadvector =3D 0; =20 - if (!is_vector_supported()) - SKIP(return, "Vector not supported"); + if (!is_vector_supported()) { + if (is_xtheadvector_supported()) + xtheadvector =3D 1; + else + SKIP(return, "Vector not supported"); + } =20 /* Turn off next's vector explicitly and test */ flag =3D PR_RISCV_V_VSTATE_CTRL_OFF << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; =20 - EXPECT_EQ(0, test_and_compare_child(flag, PR_RISCV_V_VSTATE_CTRL_OFF, 1)); + EXPECT_EQ(0, test_and_compare_child(flag, PR_RISCV_V_VSTATE_CTRL_OFF, 1, = xtheadvector)); } =20 TEST(vstate_on_inherit_no_nesting) { long flag, expected; + int xtheadvector =3D 0; =20 - if (!is_vector_supported()) - SKIP(return, "Vector not supported"); + if (!is_vector_supported()) { + if (is_xtheadvector_supported()) + xtheadvector =3D 1; + else + SKIP(return, "Vector not supported"); + } =20 /* Turn on next's vector explicitly and test no inherit */ flag =3D PR_RISCV_V_VSTATE_CTRL_ON << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; flag |=3D PR_RISCV_V_VSTATE_CTRL_INHERIT; expected =3D flag | PR_RISCV_V_VSTATE_CTRL_ON; =20 - EXPECT_EQ(0, test_and_compare_child(flag, expected, 0)); + EXPECT_EQ(0, test_and_compare_child(flag, expected, 0, xtheadvector)); } =20 TEST(vstate_on_inherit) { long flag, expected; + int xtheadvector =3D 0; =20 - if (!is_vector_supported()) - SKIP(return, "Vector not supported"); + if (!is_vector_supported()) { + if (is_xtheadvector_supported()) + xtheadvector =3D 1; + else + SKIP(return, "Vector not supported"); + } =20 /* Turn on next's vector explicitly and test inherit */ flag =3D PR_RISCV_V_VSTATE_CTRL_ON << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; flag |=3D PR_RISCV_V_VSTATE_CTRL_INHERIT; expected =3D flag | PR_RISCV_V_VSTATE_CTRL_ON; =20 - EXPECT_EQ(0, test_and_compare_child(flag, expected, 1)); + EXPECT_EQ(0, test_and_compare_child(flag, expected, 1, xtheadvector)); } =20 TEST(vstate_off_inherit_no_nesting) { long flag, expected; + int xtheadvector =3D 0; =20 - if (!is_vector_supported()) - SKIP(return, "Vector not supported"); - + if (!is_vector_supported()) { + if (is_xtheadvector_supported()) + xtheadvector =3D 1; + else + SKIP(return, "Vector not supported"); + } /* Turn off next's vector explicitly and test no inherit */ flag =3D PR_RISCV_V_VSTATE_CTRL_OFF << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; flag |=3D PR_RISCV_V_VSTATE_CTRL_INHERIT; expected =3D flag | PR_RISCV_V_VSTATE_CTRL_OFF; =20 - EXPECT_EQ(0, test_and_compare_child(flag, expected, 0)); + EXPECT_EQ(0, test_and_compare_child(flag, expected, 0, xtheadvector)); } =20 TEST(vstate_off_inherit) { long flag, expected; + int xtheadvector =3D 0; =20 - if (!is_vector_supported()) - SKIP(return, "Vector not supported"); + if (!is_vector_supported()) { + if (is_xtheadvector_supported()) + xtheadvector =3D 1; + else + SKIP(return, "Vector not supported"); + } =20 /* Turn off next's vector explicitly and test inherit */ flag =3D PR_RISCV_V_VSTATE_CTRL_OFF << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; flag |=3D PR_RISCV_V_VSTATE_CTRL_INHERIT; expected =3D flag | PR_RISCV_V_VSTATE_CTRL_OFF; =20 - EXPECT_EQ(0, test_and_compare_child(flag, expected, 1)); + EXPECT_EQ(0, test_and_compare_child(flag, expected, 1, xtheadvector)); } =20 /* arguments should fail with EINVAL */ @@ -174,7 +203,7 @@ TEST(inval_set_control_1) { int rc; =20 - if (!is_vector_supported()) + if (!is_vector_supported() && !is_xtheadvector_supported()) SKIP(return, "Vector not supported"); =20 rc =3D prctl(PR_RISCV_V_SET_CONTROL, 0xff0); @@ -187,7 +216,7 @@ TEST(inval_set_control_2) { int rc; =20 - if (!is_vector_supported()) + if (!is_vector_supported() && !is_xtheadvector_supported()) SKIP(return, "Vector not supported"); =20 rc =3D prctl(PR_RISCV_V_SET_CONTROL, 0x3); @@ -200,7 +229,7 @@ TEST(inval_set_control_3) { int rc; =20 - if (!is_vector_supported()) + if (!is_vector_supported() && !is_xtheadvector_supported()) SKIP(return, "Vector not supported"); =20 rc =3D prctl(PR_RISCV_V_SET_CONTROL, 0xc); --=20 2.44.0