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[98.183.112.25]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-708f60a55e1sm1719911a34.11.2024.07.22.15.01.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jul 2024 15:01:30 -0700 (PDT) From: David Lechner To: Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Nuno_S=C3=A1?= Cc: David Lechner , Michael Hennerich , Lars-Peter Clausen , David Jander , Martin Sperl , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org Subject: [PATCH RFC v3 5/9] spi: dt-bindings: axi-spi-engine: document spi-offloads Date: Mon, 22 Jul 2024 16:57:12 -0500 Message-ID: <20240722-dlech-mainline-spi-engine-offload-2-v3-5-7420e45df69b@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240722-dlech-mainline-spi-engine-offload-2-v3-0-7420e45df69b@baylibre.com> References: <20240722-dlech-mainline-spi-engine-offload-2-v3-0-7420e45df69b@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.14.0 Content-Transfer-Encoding: quoted-printable The AXI SPI Engine has support for hardware offloading capabilities. There can be up to 32 offload instances per SPI controller, so the bindings limit the value accordingly. Signed-off-by: David Lechner --- RFC: I have a few questions about this one... 1. The trigger-source properties are borrowed from the leds bindings. Do we want to promote this to a generic binding that can be used by any type of device? 2. Some folks are working on adding DMA to TX stream support to the AXI SPI Engine hardware. I assume that the `dmas` property is like others where the order/index in the phandle array matters. So this would mean that for device that only uses 1 out of the 32 offloads and only uses 1 TX DMA channel, we would have to have 32 <0>s for each of the possible RX dmas in the array. Any way to do some kind of mapping to avoid this? 3. In v2, we discussed about having some sort of data processing unit between the AXI SPI Engine RX stream interface and the DMA channel interface on the DMA controller. I haven't included this in the bindings yet because we don't have a user yet. But it was suggested that we could use the graph bindings for this. So here is what that might look like: Additional property for the AXI SPI Engine controller bindings: out-ports: $ref: /schemas/graph.yaml#/properties/ports unevaluatedProperties: false patternProperties: "^port@1?[0-9a-f]$": $ref: /schemas/graph.yaml#/properties/port unevaluatedProperties: false And this would be connected to a device node similar to this: ip-block@3000 { // Something similar to, but not exactly like // http://analogdevicesinc.github.io/hdl/library/util_extract/i= ndex.html compatible =3D "adi,crc-check"; // clock that runs this IP block clocks =3D <&sysclk 15>; // interrupt raised on bad CRC interrupts =3D <&intc 99>; interrupt-names =3D "crc"; // output stream with CRC byte removed piped to DMA dmas =3D <&adc_dma 0>; dma-names =3D "rx"; port { adc_crc_check: endpoint { remote-endpoint: <&offload0_rx>; }; }; }; Does this sound reasonable? v3 changes: * Added #spi-offload-cells property. * Added properties for triggers and RX data stream connected to DMA. v2 changes: This is basically a new patch. It partially replaces "dt-bindings: iio: offload: add binding for PWM/DMA triggered buffer". The controller no longer has an offloads object node and the spi-offloads property is now a standard SPI peripheral property. --- .../bindings/spi/adi,axi-spi-engine.yaml | 41 ++++++++++++++++++= ++++ 1 file changed, 41 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml = b/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml index d48faa42d025..ec18eabb993a 100644 --- a/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml +++ b/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml @@ -41,6 +41,42 @@ properties: - const: s_axi_aclk - const: spi_clk =20 + '#spi-offload-cells': + description: The cell value is the offload instance number. + const: 1 + + trigger-sources: + description: + An array of trigger source phandles for offload instances. The index= in + the array corresponds to the offload instance number. + $ref: /schemas/types.yaml#/definitions/phandle-array + + dmas: + description: + DMA channels connected to the output stream interface of an offload = instance. + minItems: 1 + maxItems: 32 + + dma-names: + minItems: 1 + maxItems: 32 + items: + pattern: "^offload(?:[12]?[0-9]|3[01])-rx$" + +patternProperties: + "^.*@[0-9a-f]+$": + type: object + $ref: spi-peripheral-props.yaml + additionalProperties: true + properties: + spi-offloads: + description: + An array of 1 or more offload instance numbers assigned to this + peripheral. + items: + minimum: 0 + maximum: 31 + required: - compatible - reg @@ -59,6 +95,11 @@ examples: clocks =3D <&clkc 15>, <&clkc 15>; clock-names =3D "s_axi_aclk", "spi_clk"; =20 + #spi-offload-cells =3D <1>; + trigger-sources =3D <&trigger_clock>; + dmas =3D <&dma 0>; + dma-names =3D "offload0-rx"; + #address-cells =3D <1>; #size-cells =3D <0>; =20 --=20 2.43.0