From nobody Tue Dec 16 02:57:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E62781487C5 for ; Sat, 20 Jul 2024 17:26:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721496412; cv=none; b=sxRKX3T23zD4/REN8bgCSKbyrWTT4+KyIvdv4GywaKHTj/Yq6pOw30u7WY694s2ki6dJ2MCywRDM7l46RDEc8yybwlKhv0ExGovhU/Mnn9cBHQoAhQb97xdqVdnng58MHXLqKTjYHsbXMmseOSBsCf/NYMhx7GcKuEOqPYCztpI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721496412; c=relaxed/simple; bh=NCFdc/pkut4LwN+MrcPmxA5eUoeddsannScPQZtdY/A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=r6Xu9AY0j3YF8Q0qVuqMQrz5swEbgyX/KBFjTUJKf0QJ4KfIzZ9XVakpuq7kGussmWtekQHmoPrneE1MzILLN2mPPhgnLXGvSLUD9i5lSmFZoc0/mFYQ0ngyyY3RPAmV0nPBhus6nCdoxkGLhgjSRYmbmH/yQ+RwbZl3ClzQIaE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hvlTkTWX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hvlTkTWX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 06E95C4AF09; Sat, 20 Jul 2024 17:26:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721496411; bh=NCFdc/pkut4LwN+MrcPmxA5eUoeddsannScPQZtdY/A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hvlTkTWXkGaIxigUYa1gwQar5xanhbF93SHCip2ilWq5sLv5uxDeIy8BPjMTDtNRO 80D+AfczK9MoaU8hayhUVOcKkecYo114IlB7xBsFuQj1f1uc2UJwjZeYGFu5Rt6ycV 1yzyTb8oUNS8Tr1PYk8LjNALSCij22dli9rSGZGa6E/0qS0DjYzKTLdf7iUm4TPqBZ lhxdComq3ce51D2+v9CZUsbaLcLLkXWqlUu11XOlhN5siC3kcPRVhCk8FoA0SJluuJ Us5Hc+/eSm3qupIEKSBT3LkHnvKe3u+eamNdnwE7Lwjd7oSdMV5OxSOqMYUPos5aY1 toGQ3Pzc5Ca1A== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Charlie Jenkins , Deepak Gupta , Clement Leger Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/7] riscv: traps: staticalize handle_break() Date: Sun, 21 Jul 2024 01:12:26 +0800 Message-ID: <20240720171232.1753-2-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240720171232.1753-1-jszhang@kernel.org> References: <20240720171232.1753-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" handle_break() is only called in traps.c, make it static. Signed-off-by: Jisheng Zhang --- arch/riscv/include/asm/entry-common.h | 1 - arch/riscv/kernel/traps.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/entry-common.h b/arch/riscv/include/asm= /entry-common.h index 2293e535f865..1458a41c6536 100644 --- a/arch/riscv/include/asm/entry-common.h +++ b/arch/riscv/include/asm/entry-common.h @@ -23,7 +23,6 @@ static inline void arch_exit_to_user_mode_prepare(struct = pt_regs *regs, #define arch_exit_to_user_mode_prepare arch_exit_to_user_mode_prepare =20 void handle_page_fault(struct pt_regs *regs); -void handle_break(struct pt_regs *regs); =20 #ifdef CONFIG_RISCV_MISALIGNED int handle_misaligned_load(struct pt_regs *regs); diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 05a16b1f0aee..84dff89f435d 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -270,7 +270,7 @@ static bool probe_breakpoint_handler(struct pt_regs *re= gs) return user ? uprobe_breakpoint_handler(regs) : kprobe_breakpoint_handler= (regs); } =20 -void handle_break(struct pt_regs *regs) +static void handle_break(struct pt_regs *regs) { if (probe_single_step_handler(regs)) return; --=20 2.43.0 From nobody Tue Dec 16 02:57:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBCEB148848 for ; Sat, 20 Jul 2024 17:26:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721496413; cv=none; b=n5s36FRgWS0cwqnUZ9F3XCh6ngXqCxG6K9Kg5mnBTPCTR1jwf1kQKuy3qiAhjBeI160lG/ldmXFuuU86GEKZ59XhSA/wLs+kcisez94asQwVb7DYaJJGjSPD5ltFl/N+rh3LW4PigK7EpuSzIpo/Um5BAXjyvTSlSU/NUiKzofg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721496413; c=relaxed/simple; bh=98NBtrS/SMiq12hZfID75Yi7wQQ0UoZjx4bDe8JfM7E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cYmMkCXl1O5UEOVkr5HjnPbbHfi8qsWm7rWqoDe97/jolnPAiwqFpkJvHUbudBoV8OKUNnjYU5QeHZK5MogSGpgxqsOizpAkBgn//NDyu9VReQi0sBhbqyVGXNd+wVdi/ONI+TFWaOxfoSxKSO3YOI06wjYypqlZlwEwMMTvpVw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=N4ztOcRF; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="N4ztOcRF" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DCCC0C4AF0E; Sat, 20 Jul 2024 17:26:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721496413; bh=98NBtrS/SMiq12hZfID75Yi7wQQ0UoZjx4bDe8JfM7E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=N4ztOcRFtt/L8y27kj71vaMp/hVPX2rJ4XGAvHs2lK82jNMi7tHf63+X4gZ6ikrOL 5NCdG91/FjCSWTnPZu0DN4v81Pr99PSPEt+JF4DRdNQlGLiu3drOFFWs/9qycQOl09 9S9DDIlttmYex+ufURu9cwx76Gvu24azkKA5HYf1gCU4spDsZIOu9s9gPYIR9j2uC0 xdJEajhAV4WWiKPviJXA/F4ibDbR3WgZbCf/uHvyP34sUPLkD+DPo6wvU01GaZUIlr mDcqR/ITjGxO1s+H2Ms9xAScH0925ep10jddLPR8UESmKdZSnh2QJbMouFH8zx5gfH p0Ijsu6L28aJg== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Charlie Jenkins , Deepak Gupta , Clement Leger Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/7] riscv: traps: remove __visible annotation Date: Sun, 21 Jul 2024 01:12:27 +0800 Message-ID: <20240720171232.1753-3-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240720171232.1753-1-jszhang@kernel.org> References: <20240720171232.1753-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit f307307992bf ("riscv: for C functions called only from assembly, mark with __visible") resolve sparse warnings for C functions called only by assembly code by adding __visible annotations instead of adding prototypes. But after commit 030f1dfa8550 ("riscv: traps: Fix no prototype warnings"), prototypes were added. So the __visible annotations are not needed any more, remove them. Signed-off-by: Jisheng Zhang --- arch/riscv/kernel/traps.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 84dff89f435d..3d1f84cb6eac 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -147,7 +147,7 @@ static void do_trap_error(struct pt_regs *regs, int sig= no, int code, #define __trap_section noinstr #endif #define DO_ERROR_INFO(name, signo, code, str) \ -asmlinkage __visible __trap_section void name(struct pt_regs *regs) \ +asmlinkage __trap_section void name(struct pt_regs *regs) \ { \ if (user_mode(regs)) { \ irqentry_enter_from_user_mode(regs); \ @@ -167,7 +167,7 @@ DO_ERROR_INFO(do_trap_insn_misaligned, DO_ERROR_INFO(do_trap_insn_fault, SIGSEGV, SEGV_ACCERR, "instruction access fault"); =20 -asmlinkage __visible __trap_section void do_trap_insn_illegal(struct pt_re= gs *regs) +asmlinkage __trap_section void do_trap_insn_illegal(struct pt_regs *regs) { bool handled; =20 @@ -198,7 +198,7 @@ asmlinkage __visible __trap_section void do_trap_insn_i= llegal(struct pt_regs *re DO_ERROR_INFO(do_trap_load_fault, SIGSEGV, SEGV_ACCERR, "load access fault"); =20 -asmlinkage __visible __trap_section void do_trap_load_misaligned(struct pt= _regs *regs) +asmlinkage __trap_section void do_trap_load_misaligned(struct pt_regs *reg= s) { if (user_mode(regs)) { irqentry_enter_from_user_mode(regs); @@ -219,7 +219,7 @@ asmlinkage __visible __trap_section void do_trap_load_m= isaligned(struct pt_regs } } =20 -asmlinkage __visible __trap_section void do_trap_store_misaligned(struct p= t_regs *regs) +asmlinkage __trap_section void do_trap_store_misaligned(struct pt_regs *re= gs) { if (user_mode(regs)) { irqentry_enter_from_user_mode(regs); @@ -294,7 +294,7 @@ static void handle_break(struct pt_regs *regs) die(regs, "Kernel BUG"); } =20 -asmlinkage __visible __trap_section void do_trap_break(struct pt_regs *reg= s) +asmlinkage __trap_section void do_trap_break(struct pt_regs *regs) { if (user_mode(regs)) { irqentry_enter_from_user_mode(regs); @@ -311,7 +311,7 @@ asmlinkage __visible __trap_section void do_trap_break(= struct pt_regs *regs) } } =20 -asmlinkage __visible __trap_section __no_stack_protector +asmlinkage __trap_section __no_stack_protector void do_trap_ecall_u(struct pt_regs *regs) { if (user_mode(regs)) { @@ -355,7 +355,7 @@ void do_trap_ecall_u(struct pt_regs *regs) } =20 #ifdef CONFIG_MMU -asmlinkage __visible noinstr void do_page_fault(struct pt_regs *regs) +asmlinkage noinstr void do_page_fault(struct pt_regs *regs) { irqentry_state_t state =3D irqentry_enter(regs); =20 --=20 2.43.0 From nobody Tue Dec 16 02:57:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6704148FF5 for ; Sat, 20 Jul 2024 17:26:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721496415; cv=none; b=E/AlmyFifxQ00B1lUVBWjt5RVrsmaS2nvsOQOvd9hgezLA1f26GDRQEpd3pL71AD1MzuctxEHU6jPwWtkhRIGoAYnWp9KzzgvEGZ02N1mfuTat9UV3sK0sfLIH2qEFL6Ilkfegyy6azJ32LKbZL/KROwYMdWXFPbYPwAon4BX/Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721496415; c=relaxed/simple; bh=4mfzfBuI5w4GYD/fit9dlYuOHBy27wsKPXlA84/NLtY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=E+WEp7y6Uw0/paKvyfWvjAFz7k3q6fGi+vbaBtKngoqXs36GLQV9GmAG4asGFNMfHgICVn1tXBCqCWIRGYJlBONVLsZkerTwSf9zwZCIujAZbSs+aLToFHel0iQq4JJnr23RZi2ObNX5DQ5oCc70EfXEpEM+/1obuuURnsJ13rk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZZRNKnrr; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZZRNKnrr" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BFB94C2BD10; Sat, 20 Jul 2024 17:26:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721496415; bh=4mfzfBuI5w4GYD/fit9dlYuOHBy27wsKPXlA84/NLtY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZZRNKnrrt4f/JLNrILzEZrulIdE1aK+z6WCFBcwfHrbArWJN0twEMJCpU2bLeGbAI NtpPhOx7V1C0D9fA69dZVbLiLHFmCxJ5XrRFZMsmLaxQGrA/WxoMrFqj8BKRTUGYD+ BRk/DejhE0/KW2u1qtzZ2BIAbH70++8IIqJkge0xK7HFDllRajPwGv6CEEHMi9tvjF S4oadAj6SUTqlcoF7aj0zCQk1g6xQ6mZ2SFJYhul9K4/0De+LJFXDR6TIYG8ggc/sm W8n7CfwJBgEp0qrbvT80b1o9fj1o6y1mU7tlpnJMFuU1END+IPmxoIO5u85qNsuaU+ HNaox/Kg5Uwpg== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Charlie Jenkins , Deepak Gupta , Clement Leger Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/7] riscv: convert bottom half of exception handling to C Date: Sun, 21 Jul 2024 01:12:28 +0800 Message-ID: <20240720171232.1753-4-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240720171232.1753-1-jszhang@kernel.org> References: <20240720171232.1753-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For readability, maintainability and future scalability, convert the bottom half of the exception handling to C. Mostly the assembly code is converted to C in a relatively straightforward manner. However, there are two modifications I need to mention: 1. the cause I.E the CSR_CAUSE value is passed to do_traps() via. 2nd param, do_traps() doesn't get it from pt_regs because this way an extra memory load is needed, the exception handling sits in hot code path, every instruction matters. 2.To cope with SIFIVE_CIP_453 errata, it looks like we don't need alternative mechanism any more after the asm->c conversion. Just replace the excp_vect_table two entries. Signed-off-by: Jisheng Zhang Reviewed-by: Deepak Gupta --- arch/riscv/errata/sifive/errata.c | 25 ++++++++--- arch/riscv/include/asm/asm-prototypes.h | 1 + arch/riscv/include/asm/errata_list.h | 5 +-- arch/riscv/kernel/entry.S | 57 +------------------------ arch/riscv/kernel/traps.c | 37 ++++++++++++++++ 5 files changed, 61 insertions(+), 64 deletions(-) diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/e= rrata.c index 716cfedad3a2..bbba99f207ca 100644 --- a/arch/riscv/errata/sifive/errata.c +++ b/arch/riscv/errata/sifive/errata.c @@ -10,9 +10,14 @@ #include #include #include +#include #include #include =20 +extern void (*excp_vect_table[])(struct pt_regs *regs); +extern void sifive_cip_453_insn_fault_trp(struct pt_regs *regs); +extern void sifive_cip_453_page_fault_trp(struct pt_regs *regs); + struct errata_info_t { char name[32]; bool (*check_func)(unsigned long arch_id, unsigned long impid); @@ -20,6 +25,9 @@ struct errata_info_t { =20 static bool errata_cip_453_check_func(unsigned long arch_id, unsigned lon= g impid) { + if (!IS_ENABLED(CONFIG_ERRATA_SIFIVE_CIP_453)) + return false; + /* * Affected cores: * Architecture ID: 0x8000000000000007 @@ -51,10 +59,6 @@ static bool errata_cip_1200_check_func(unsigned long ar= ch_id, unsigned long imp } =20 static struct errata_info_t errata_list[ERRATA_SIFIVE_NUMBER] =3D { - { - .name =3D "cip-453", - .check_func =3D errata_cip_453_check_func - }, { .name =3D "cip-1200", .check_func =3D errata_cip_1200_check_func @@ -62,11 +66,20 @@ static struct errata_info_t errata_list[ERRATA_SIFIVE_N= UMBER] =3D { }; =20 static u32 __init_or_module sifive_errata_probe(unsigned long archid, - unsigned long impid) + unsigned long impid, + unsigned int stage) { int idx; u32 cpu_req_errata =3D 0; =20 + if (stage =3D=3D RISCV_ALTERNATIVES_BOOT) { + if (IS_ENABLED(CONFIG_MMU) && + errata_cip_453_check_func(archid, impid)) { + excp_vect_table[EXC_INST_ACCESS] =3D sifive_cip_453_insn_fault_trp; + excp_vect_table[EXC_INST_PAGE_FAULT] =3D sifive_cip_453_page_fault_trp; + } + } + for (idx =3D 0; idx < ERRATA_SIFIVE_NUMBER; idx++) if (errata_list[idx].check_func(archid, impid)) cpu_req_errata |=3D (1U << idx); @@ -99,7 +112,7 @@ void sifive_errata_patch_func(struct alt_entry *begin, s= truct alt_entry *end, if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT) return; =20 - cpu_req_errata =3D sifive_errata_probe(archid, impid); + cpu_req_errata =3D sifive_errata_probe(archid, impid, stage); =20 for (alt =3D begin; alt < end; alt++) { if (alt->vendor_id !=3D SIFIVE_VENDOR_ID) diff --git a/arch/riscv/include/asm/asm-prototypes.h b/arch/riscv/include/a= sm/asm-prototypes.h index cd627ec289f1..c6691e9032dd 100644 --- a/arch/riscv/include/asm/asm-prototypes.h +++ b/arch/riscv/include/asm/asm-prototypes.h @@ -55,5 +55,6 @@ DECLARE_DO_ERROR_INFO(do_trap_break); asmlinkage void handle_bad_stack(struct pt_regs *regs); asmlinkage void do_page_fault(struct pt_regs *regs); asmlinkage void do_irq(struct pt_regs *regs); +asmlinkage void do_traps(struct pt_regs *regs, unsigned long cause); =20 #endif /* _ASM_RISCV_PROTOTYPES_H */ diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/= errata_list.h index 7c8a71a526a3..95b79afc4061 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -17,9 +17,8 @@ #endif =20 #ifdef CONFIG_ERRATA_SIFIVE -#define ERRATA_SIFIVE_CIP_453 0 -#define ERRATA_SIFIVE_CIP_1200 1 -#define ERRATA_SIFIVE_NUMBER 2 +#define ERRATA_SIFIVE_CIP_1200 0 +#define ERRATA_SIFIVE_NUMBER 1 #endif =20 #ifdef CONFIG_ERRATA_THEAD diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 81dec627a8d4..37c3c2068fef 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -83,36 +83,10 @@ SYM_CODE_START(handle_exception) /* Load the kernel shadow call stack pointer if coming from userspace */ scs_load_current_if_task_changed s5 =20 -#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE - move a0, sp - call riscv_v_context_nesting_start -#endif move a0, sp /* pt_regs */ - - /* - * MSB of cause differentiates between - * interrupts and exceptions - */ - bge s4, zero, 1f - - /* Handle interrupts */ - call do_irq + move a1, s4 /* cause */ + call do_traps j ret_from_exception -1: - /* Handle other exceptions */ - slli t0, s4, RISCV_LGPTR - la t1, excp_vect_table - la t2, excp_vect_table_end - add t0, t1, t0 - /* Check if exception code lies within bounds */ - bgeu t0, t2, 3f - REG_L t1, 0(t0) -2: jalr t1 - j ret_from_exception -3: - - la t1, do_trap_unknown - j 2b SYM_CODE_END(handle_exception) ASM_NOKPROBE(handle_exception) =20 @@ -329,33 +303,6 @@ SYM_FUNC_START(__switch_to) ret SYM_FUNC_END(__switch_to) =20 -#ifndef CONFIG_MMU -#define do_page_fault do_trap_unknown -#endif - - .section ".rodata" - .align LGREG - /* Exception vector table */ -SYM_DATA_START_LOCAL(excp_vect_table) - RISCV_PTR do_trap_insn_misaligned - ALT_INSN_FAULT(RISCV_PTR do_trap_insn_fault) - RISCV_PTR do_trap_insn_illegal - RISCV_PTR do_trap_break - RISCV_PTR do_trap_load_misaligned - RISCV_PTR do_trap_load_fault - RISCV_PTR do_trap_store_misaligned - RISCV_PTR do_trap_store_fault - RISCV_PTR do_trap_ecall_u /* system call */ - RISCV_PTR do_trap_ecall_s - RISCV_PTR do_trap_unknown - RISCV_PTR do_trap_ecall_m - /* instruciton page fault */ - ALT_PAGE_FAULT(RISCV_PTR do_page_fault) - RISCV_PTR do_page_fault /* load page fault */ - RISCV_PTR do_trap_unknown - RISCV_PTR do_page_fault /* store page fault */ -SYM_DATA_END_LABEL(excp_vect_table, SYM_L_LOCAL, excp_vect_table_end) - #ifndef CONFIG_MMU SYM_DATA_START(__user_rt_sigreturn) li a7, __NR_rt_sigreturn diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 3d1f84cb6eac..3eaa7c72f2be 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -390,6 +390,43 @@ asmlinkage void noinstr do_irq(struct pt_regs *regs) irqentry_exit(regs, state); } =20 +void (*excp_vect_table[])(struct pt_regs *regs) __ro_after_init =3D { + do_trap_insn_misaligned, /* 0 Instruction address misaligned */ + do_trap_insn_fault, /* 1 Instruction access fault */ + do_trap_insn_illegal, /* 2 Illegal instruction */ + do_trap_break, /* 3 Breakpoint */ + do_trap_load_misaligned, /* 4 Load address misaligned */ + do_trap_load_fault, /* 5 Load access fault */ + do_trap_store_misaligned, /* 6 Store/AMO address misaligned */ + do_trap_store_fault, /* 7 Store/AMO access fault */ + do_trap_ecall_u, /* 8 Environment call from U-mode */ + do_trap_ecall_s, /* 9 Environment call from S-mode */ + do_trap_unknown, /* 10 Reserved */ + do_trap_ecall_m, /* 11 Environment call from M-mode */ +#ifdef CONFIG_MMU + do_page_fault, /* 12 Instruciton page fault */ + do_page_fault, /* 13 Load page fault */ + do_trap_unknown, /* 14 Reserved */ + do_page_fault, /* 15 Store/AMO page fault */ +#endif +}; + +asmlinkage void noinstr do_traps(struct pt_regs *regs, unsigned long cause) +{ +#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE + riscv_v_context_nesting_start(regs); +#endif + if (cause & CAUSE_IRQ_FLAG) { + do_irq(regs); + } else { + if (cause >=3D ARRAY_SIZE(excp_vect_table)) { + do_trap_unknown(regs); + return; + } + excp_vect_table[cause](regs); + } +} + #ifdef CONFIG_GENERIC_BUG int is_valid_bugaddr(unsigned long pc) { --=20 2.43.0 From nobody Tue Dec 16 02:57:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C2EF149016 for ; Sat, 20 Jul 2024 17:26:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721496417; cv=none; b=mTAQo7NVrPvmgIAdk6S2yHOSFgus68qLOP9CoTPFdgO5OpmVgUMiQOStbKjJjwoY7jyB0dHB1jm9NfVReU8TmA/0/WLZ8u9iwxdl2JS747TslBfKJOgxckdC/z2e9RgogHGsYmiwAiX6q5HbBo23GXmSfFAx5FBnr9AzIkBSPxw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721496417; c=relaxed/simple; bh=PS9GETIFotMXHbuFrtVxV4bYZ42Bdzp9+Zn0gjyOdnE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lYnJTqT8WsT3F+1HwjOX4/Wq83LpgxocaTcu9ZRv6dXZAFLsjOm4EZfvTqJ1/l+wYLDMbX2GXpm4NB5zUPvwvBKDpCbCRwyC1ZgVmdey7p19FM1rpVwNenYDT5XVsCv3aMG1115hHbclkXqsgMFR+u5b89piPPzJVoufPthtJG4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=s/rP/PyG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="s/rP/PyG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9EA31C4AF0F; Sat, 20 Jul 2024 17:26:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721496417; bh=PS9GETIFotMXHbuFrtVxV4bYZ42Bdzp9+Zn0gjyOdnE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=s/rP/PyGYs4PM91YBMl0YbrBayzt4Kt/jSe62G6momR9f39KhwggHvETfJRuFWbjb lrmjhNUkFw6spRPMkBRpQpY1mSdm04chjCkZcA4Ug5ONjd1NJn+uQUdHQ5TpVNALeL Ajogh2zDCPgwIxQ0zebSHVrDSUSX7EiFqgsWuNViCda7BwUn+bJOSKOo1ZhEx0Q9Hl bhMTwUjyww2Y3zktoq7+ABmGksGl/86pifrZvxVYHIDQmxIbHj910AlLeCxyTrlvZc F/kFUngUxFt+iAZZsOTOuaybDumo7n1kDhed5stC1a5zPZtbKjSSxkYnGB2cEcCK8t AYdeziyZy0pxA== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Charlie Jenkins , Deepak Gupta , Clement Leger Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/7] riscv: errata: remove ALT_INSN_FAULT and ALT_PAGE_FAULT Date: Sun, 21 Jul 2024 01:12:29 +0800 Message-ID: <20240720171232.1753-5-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240720171232.1753-1-jszhang@kernel.org> References: <20240720171232.1753-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" They are used for SIFIVE_CIP_453 errata, which has been solved by replacing the excp_vect_table[] two entries in last commit. So these two macros are useless now, remove them. Signed-off-by: Jisheng Zhang --- arch/riscv/include/asm/errata_list.h | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/= errata_list.h index 95b79afc4061..46bf00c4a57a 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -27,21 +27,7 @@ #define ERRATA_THEAD_NUMBER 2 #endif =20 -#ifdef __ASSEMBLY__ - -#define ALT_INSN_FAULT(x) \ -ALTERNATIVE(__stringify(RISCV_PTR do_trap_insn_fault), \ - __stringify(RISCV_PTR sifive_cip_453_insn_fault_trp), \ - SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \ - CONFIG_ERRATA_SIFIVE_CIP_453) - -#define ALT_PAGE_FAULT(x) \ -ALTERNATIVE(__stringify(RISCV_PTR do_page_fault), \ - __stringify(RISCV_PTR sifive_cip_453_page_fault_trp), \ - SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \ - CONFIG_ERRATA_SIFIVE_CIP_453) -#else /* !__ASSEMBLY__ */ - +#ifndef __ASSEMBLY__ #define ALT_SFENCE_VMA_ASID(asid) \ asm(ALTERNATIVE("sfence.vma x0, %0", "sfence.vma", SIFIVE_VENDOR_ID, \ ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200) \ --=20 2.43.0 From nobody Tue Dec 16 02:57:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2ECAE1494C1 for ; Sat, 20 Jul 2024 17:26:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721496419; cv=none; b=Rj3enFeR8Wwc9Uhmub40fzvV+vdTmPPMlfhh0kCqxgAS7LDBqpX7ALOllM1Cl2rR8169AbkqXugD1wBd6lR1MLOvApSclE8tuzPWFqHUi2o96ZQevqK3+FphLY8b97uI6GfnsrDb59e6DCiI3B69jlOmHowFiY6WDh0JKYt7AAc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721496419; c=relaxed/simple; bh=Xt3rus8MTwutIvQ5H763TfjQNRRFpnqcC5IzkxuWKNs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=egA7JcufuMqEICg2X9Z/qDCtxD6n7E8VnWdL9Vo6H+4SMs4sR+O1ImNHHrKE0ICvrvqK/pIrV2UIskuyqjobNWlb578TZzZsPOXjlGWIg/NDkdSz0XMwJweI3SIfBu5/nqe7hBmIzMbxDO/bWIMSzRrnBehjdiAbjcmWfSHGhAE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QihgeSnv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QihgeSnv" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 84504C4AF0A; Sat, 20 Jul 2024 17:26:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721496419; bh=Xt3rus8MTwutIvQ5H763TfjQNRRFpnqcC5IzkxuWKNs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QihgeSnvf2PG6PDvXw42EUn9W2Oi9atxy4Nf7WqIlvZyRTC4qpgDd43bxadaHLI8o G7TVwBqzG9gC9FOAqBErLA9cR1tph4INUWAYs/GaWoQuthn76MwevRLw+oBVXpxsYw QI8kpRYJGwRWvkACHfZtzQ5N7F9OMML+EPWNft5t3UUI9MSAaWT9SLH6EcfTXgX2jn eTqRuMFQtySTtIJP/MeDVsb6yVHCFN6iTkA5CWHMn01XwPx6IA1DAjrZFPRwvVd+ct gfkP4W7c3SC+BZ+aASXMRVuewUoo2jvRede2Xbp+Q3R2VxVuw8qaED7MjWaDz1pip3 YBG1UIfA5btfQ== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Charlie Jenkins , Deepak Gupta , Clement Leger Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/7] riscv: errata: sifive: remove NOMMU handling Date: Sun, 21 Jul 2024 01:12:30 +0800 Message-ID: <20240720171232.1753-6-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240720171232.1753-1-jszhang@kernel.org> References: <20240720171232.1753-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since NOMMU is now properly handling in generic do_traps() which will call do_trap_unknown() for instruciton page fault for NOMMU. Signed-off-by: Jisheng Zhang --- arch/riscv/errata/sifive/errata_cip_453.S | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/riscv/errata/sifive/errata_cip_453.S b/arch/riscv/errata/= sifive/errata_cip_453.S index b1f7b636fe9a..6f004a1610f6 100644 --- a/arch/riscv/errata/sifive/errata_cip_453.S +++ b/arch/riscv/errata/sifive/errata_cip_453.S @@ -23,11 +23,7 @@ =20 SYM_FUNC_START(sifive_cip_453_page_fault_trp) ADD_SIGN_EXT a0, t0, t1 -#ifdef CONFIG_MMU la t0, do_page_fault -#else - la t0, do_trap_unknown -#endif jr t0 SYM_FUNC_END(sifive_cip_453_page_fault_trp) =20 --=20 2.43.0 From nobody Tue Dec 16 02:57:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27160149C59 for ; Sat, 20 Jul 2024 17:27:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721496421; cv=none; b=Ou2mu+zUyOidKoKcaxNmElGW4p6aM8FoF0snZ+3h7XDVoqxvIBGTuqxQufAxpm6SY6MTh5lKU7Z8Y3htBESuhp8UugYCPG2Xa1DDSXq44IJv6/nANvOiqjcwXJvQbKN5cIY7mlj133xmoe23WVsYuTary6J9TdjxcmMkdnaddjg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721496421; c=relaxed/simple; bh=Y6v1+nAyzX6PLWXUQO4fYkr+VRI6pL0daNUbphTp9Ls=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RCh0+j4b4qenlPET4HywE/7Qh8+yR9YUDKQ3CHX5dxQmSyHXONRpJbwPl/+kKFCXMDIvRacWrAS+ebr7ENaBwaM47ecYpsSZcTa9/0/RYhSYgouAZnhS1KoIg+tmmpeV6EZJke8pUK8MpEisxDcNSu+NH5maOZvOHcuFoDKX5ZQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mo1NidTg; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mo1NidTg" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6AE32C4AF0A; Sat, 20 Jul 2024 17:26:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721496421; bh=Y6v1+nAyzX6PLWXUQO4fYkr+VRI6pL0daNUbphTp9Ls=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mo1NidTgWe4gaqa1uhLGqnaHg5Lw0GfB7cXA2DLf78lDSt9LMzySiZAzXFuGsfTu9 FDnJOOoFjIyPazatV3Ug8h0PqPHAkHPAcbvSGjrokipmTMPAQPnsJNRxgmP9G3jtKp MIKNSf0+s9SB+anrQYQRRYASrqCfnBEjAQRZiEeXxxfhsWctjs48eSrv2aVoiQNa/z 5dWVUwW5P89QqGsHHrOtoPHWxsR2Hhz7Hfzc2PYU4YNM+wPvG7RrCNXi5myMqD4Q1T DoGnsRlzagv7bVnSzB5Yv4w0Mbd7pmz1IgPTotQOcVwqR/3+BHuCm5OYoOX91TtLSn Hdvj0BPDY6Ofg== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Charlie Jenkins , Deepak Gupta , Clement Leger Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/7] riscv: staticalize and remove asmlinkage from updated functions Date: Sun, 21 Jul 2024 01:12:31 +0800 Message-ID: <20240720171232.1753-7-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240720171232.1753-1-jszhang@kernel.org> References: <20240720171232.1753-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that the callers of these functions have moved into C, they are only called in trap.c and no longer need the asmlinkage annotation. So make them static and remove asmlinkage from them. Signed-off-by: Jisheng Zhang --- arch/riscv/include/asm/asm-prototypes.h | 19 +------------------ arch/riscv/kernel/kernel_mode_vector.c | 2 +- arch/riscv/kernel/traps.c | 16 ++++++++-------- 3 files changed, 10 insertions(+), 27 deletions(-) diff --git a/arch/riscv/include/asm/asm-prototypes.h b/arch/riscv/include/a= sm/asm-prototypes.h index c6691e9032dd..067e93e3b400 100644 --- a/arch/riscv/include/asm/asm-prototypes.h +++ b/arch/riscv/include/asm/asm-prototypes.h @@ -31,30 +31,13 @@ void xor_regs_5_(unsigned long bytes, unsigned long *__= restrict p1, const unsigned long *__restrict p5); =20 #ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE -asmlinkage void riscv_v_context_nesting_start(struct pt_regs *regs); +void riscv_v_context_nesting_start(struct pt_regs *regs); asmlinkage void riscv_v_context_nesting_end(struct pt_regs *regs); #endif /* CONFIG_RISCV_ISA_V_PREEMPTIVE */ =20 #endif /* CONFIG_RISCV_ISA_V */ =20 -#define DECLARE_DO_ERROR_INFO(name) asmlinkage void name(struct pt_regs *r= egs) - -DECLARE_DO_ERROR_INFO(do_trap_unknown); -DECLARE_DO_ERROR_INFO(do_trap_insn_misaligned); -DECLARE_DO_ERROR_INFO(do_trap_insn_fault); -DECLARE_DO_ERROR_INFO(do_trap_insn_illegal); -DECLARE_DO_ERROR_INFO(do_trap_load_fault); -DECLARE_DO_ERROR_INFO(do_trap_load_misaligned); -DECLARE_DO_ERROR_INFO(do_trap_store_misaligned); -DECLARE_DO_ERROR_INFO(do_trap_store_fault); -DECLARE_DO_ERROR_INFO(do_trap_ecall_u); -DECLARE_DO_ERROR_INFO(do_trap_ecall_s); -DECLARE_DO_ERROR_INFO(do_trap_ecall_m); -DECLARE_DO_ERROR_INFO(do_trap_break); - asmlinkage void handle_bad_stack(struct pt_regs *regs); -asmlinkage void do_page_fault(struct pt_regs *regs); -asmlinkage void do_irq(struct pt_regs *regs); asmlinkage void do_traps(struct pt_regs *regs, unsigned long cause); =20 #endif /* _ASM_RISCV_PROTOTYPES_H */ diff --git a/arch/riscv/kernel/kernel_mode_vector.c b/arch/riscv/kernel/ker= nel_mode_vector.c index 6afe80c7f03a..a6995429ddf5 100644 --- a/arch/riscv/kernel/kernel_mode_vector.c +++ b/arch/riscv/kernel/kernel_mode_vector.c @@ -152,7 +152,7 @@ static int riscv_v_start_kernel_context(bool *is_nested) } =20 /* low-level V context handling code, called with irq disabled */ -asmlinkage void riscv_v_context_nesting_start(struct pt_regs *regs) +void riscv_v_context_nesting_start(struct pt_regs *regs) { int depth; =20 diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 3eaa7c72f2be..dc1bc84cfe15 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -147,7 +147,7 @@ static void do_trap_error(struct pt_regs *regs, int sig= no, int code, #define __trap_section noinstr #endif #define DO_ERROR_INFO(name, signo, code, str) \ -asmlinkage __trap_section void name(struct pt_regs *regs) \ +static __trap_section void name(struct pt_regs *regs) \ { \ if (user_mode(regs)) { \ irqentry_enter_from_user_mode(regs); \ @@ -167,7 +167,7 @@ DO_ERROR_INFO(do_trap_insn_misaligned, DO_ERROR_INFO(do_trap_insn_fault, SIGSEGV, SEGV_ACCERR, "instruction access fault"); =20 -asmlinkage __trap_section void do_trap_insn_illegal(struct pt_regs *regs) +static __trap_section void do_trap_insn_illegal(struct pt_regs *regs) { bool handled; =20 @@ -198,7 +198,7 @@ asmlinkage __trap_section void do_trap_insn_illegal(str= uct pt_regs *regs) DO_ERROR_INFO(do_trap_load_fault, SIGSEGV, SEGV_ACCERR, "load access fault"); =20 -asmlinkage __trap_section void do_trap_load_misaligned(struct pt_regs *reg= s) +static __trap_section void do_trap_load_misaligned(struct pt_regs *regs) { if (user_mode(regs)) { irqentry_enter_from_user_mode(regs); @@ -219,7 +219,7 @@ asmlinkage __trap_section void do_trap_load_misaligned(= struct pt_regs *regs) } } =20 -asmlinkage __trap_section void do_trap_store_misaligned(struct pt_regs *re= gs) +static __trap_section void do_trap_store_misaligned(struct pt_regs *regs) { if (user_mode(regs)) { irqentry_enter_from_user_mode(regs); @@ -294,7 +294,7 @@ static void handle_break(struct pt_regs *regs) die(regs, "Kernel BUG"); } =20 -asmlinkage __trap_section void do_trap_break(struct pt_regs *regs) +static __trap_section void do_trap_break(struct pt_regs *regs) { if (user_mode(regs)) { irqentry_enter_from_user_mode(regs); @@ -311,7 +311,7 @@ asmlinkage __trap_section void do_trap_break(struct pt_= regs *regs) } } =20 -asmlinkage __trap_section __no_stack_protector +static __trap_section __no_stack_protector void do_trap_ecall_u(struct pt_regs *regs) { if (user_mode(regs)) { @@ -355,7 +355,7 @@ void do_trap_ecall_u(struct pt_regs *regs) } =20 #ifdef CONFIG_MMU -asmlinkage noinstr void do_page_fault(struct pt_regs *regs) +static noinstr void do_page_fault(struct pt_regs *regs) { irqentry_state_t state =3D irqentry_enter(regs); =20 @@ -378,7 +378,7 @@ static void noinstr handle_riscv_irq(struct pt_regs *re= gs) irq_exit_rcu(); } =20 -asmlinkage void noinstr do_irq(struct pt_regs *regs) +static void noinstr do_irq(struct pt_regs *regs) { irqentry_state_t state =3D irqentry_enter(regs); =20 --=20 2.43.0 From nobody Tue Dec 16 02:57:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37A63149DE3 for ; Sat, 20 Jul 2024 17:27:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721496423; cv=none; b=bOqTEKh3ginlksFMMRqqXIoHzNN9g5+bI4BJ7+XQIOIFnPctV61AZa5Sp5YXZSmNQB6U3DTKmkXtXkMcdz0ZLztShh9tN9x8lR979CFrznG0woN4qFiHBYPsgkkulCdSvxjhak3YX30TxhSlMZyXgF2oDa3FPDMW93k2PzUzcZs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721496423; c=relaxed/simple; bh=8YWEf7rK4+5tGsSPanUmb4XQE9I8vrOKfPCp7u9NCeA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Lb2066Le2Kne+Fdu1RivPyfRMTc4/TBU7lOBk/4wjURmrd3OyLwXOxjOMj7dXiQpG9t6xcLy19teyGpT8dHI8EB44AEF6hnV7Lg6QPn/vLVejJSY3DinZOYxKMHTbHAd74SCtdGK5lpDgE+aY20pKXWDcSBPdelOafVB9YI1gSI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Re7GD1nJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Re7GD1nJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5DCEFC2BD10; Sat, 20 Jul 2024 17:27:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721496422; bh=8YWEf7rK4+5tGsSPanUmb4XQE9I8vrOKfPCp7u9NCeA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Re7GD1nJZkP6/TKDh5zaK6UJbwlRjD13WrXU+U/uWsoCTIPCz+KkS+FWe8qzlMP59 wlaMSl5RD1er1zJPgMqSYWPvsRLTM2wGkplZ1jJf3w9Yv4HlMpoV9jdkNRSlb1bdiS W0Z/iKOvCHmdepNmvdU10tVh0iDJuzMb4asXBIb36F+00MK6omqL5EqD3KHJ3eG9M6 Ib8eUV8z3NHnirkWteJ6P3BCBfD2UasMSk6lEjEzNX/qKJYolpbyxvDk1QsCPgq1jX WZx2mswB0I3ykRY//D+kMEiNz+QxYkm6s7EEKaloqxysN9SlVnZ8impwwvBZnQAzL2 yz5VoNN3s1ktw== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Charlie Jenkins , Deepak Gupta , Clement Leger Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 7/7] riscv: traps: mark do_irq() as __always_inline Date: Sun, 21 Jul 2024 01:12:32 +0800 Message-ID: <20240720171232.1753-8-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240720171232.1753-1-jszhang@kernel.org> References: <20240720171232.1753-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since do_irq() is only called in traps.c, so mark it as __always_inline this will allow the compiler to get rid of the stack setup/tear down code and eliminate a handful of instructions. Signed-off-by: Jisheng Zhang --- arch/riscv/kernel/traps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index dc1bc84cfe15..030c50cb4e78 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -378,7 +378,7 @@ static void noinstr handle_riscv_irq(struct pt_regs *re= gs) irq_exit_rcu(); } =20 -static void noinstr do_irq(struct pt_regs *regs) +static __always_inline void do_irq(struct pt_regs *regs) { irqentry_state_t state =3D irqentry_enter(regs); =20 --=20 2.43.0