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AJvYcCVw3Iwt9R4/5uJ1JLSihsHKohPLhjPfmCY3o3PSG2ItmuyE/Dw9DRSRjvra38KW6hr69YBN5NIx7iJqti72Br7+ssH8QNx1F0uGAat4 X-Gm-Message-State: AOJu0YzKwqZa7N1h4aIwtik4DmJQ6HrkKoRDynSc4OWgtTVh+ufJpw7/ BfxVS+wX0TH0CiifLoExXaKVaKCGvUhKRpcTPUzwcw1Qv/XsjchGIuJH42pIkHc= X-Google-Smtp-Source: AGHT+IE+xJaOF5e+dz9ph4mEQcMOaOJS+xXUFim+WrfebsgXUwhG7R+IIRODL08tQgBfyTXBjU6Aqg== X-Received: by 2002:a17:903:32c5:b0:1fb:80a3:5826 with SMTP id d9443c01a7336-1fd74cff03bmr2252485ad.4.1721405406717; Fri, 19 Jul 2024 09:10:06 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([223.185.135.236]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fd6f28f518sm6632615ad.69.2024.07.19.09.10.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Jul 2024 09:10:06 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley Cc: Atish Patra , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH 12/13] RISC-V: KVM: Save trap CSRs in kvm_riscv_vcpu_enter_exit() Date: Fri, 19 Jul 2024 21:39:12 +0530 Message-Id: <20240719160913.342027-13-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240719160913.342027-1-apatel@ventanamicro.com> References: <20240719160913.342027-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Save trap CSRs in the kvm_riscv_vcpu_enter_exit() function instead of the kvm_arch_vcpu_ioctl_run() function so that HTVAL and HTINST CSRs are accessed in more optimized manner while running under some other hypervisor. Signed-off-by: Anup Patel Reviewed-by: Atish Patra --- arch/riscv/kvm/vcpu.c | 34 +++++++++++++++++++++------------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index fe849fb1aaab..854d98aa165e 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -757,12 +757,21 @@ static __always_inline void kvm_riscv_vcpu_swap_in_ho= st_state(struct kvm_vcpu *v * This must be noinstr as instrumentation may make use of RCU, and this i= s not * safe during the EQS. */ -static void noinstr kvm_riscv_vcpu_enter_exit(struct kvm_vcpu *vcpu) +static void noinstr kvm_riscv_vcpu_enter_exit(struct kvm_vcpu *vcpu, + struct kvm_cpu_trap *trap) { void *nsh; struct kvm_cpu_context *gcntx =3D &vcpu->arch.guest_context; struct kvm_cpu_context *hcntx =3D &vcpu->arch.host_context; =20 + /* + * We save trap CSRs (such as SEPC, SCAUSE, STVAL, HTVAL, and + * HTINST) here because we do local_irq_enable() after this + * function in kvm_arch_vcpu_ioctl_run() which can result in + * an interrupt immediately after local_irq_enable() and can + * potentially change trap CSRs. + */ + kvm_riscv_vcpu_swap_in_guest_state(vcpu); guest_state_enter_irqoff(); =20 @@ -805,14 +814,24 @@ static void noinstr kvm_riscv_vcpu_enter_exit(struct = kvm_vcpu *vcpu) } else { gcntx->hstatus =3D csr_swap(CSR_HSTATUS, hcntx->hstatus); } + + trap->htval =3D nacl_csr_read(nsh, CSR_HTVAL); + trap->htinst =3D nacl_csr_read(nsh, CSR_HTINST); } else { hcntx->hstatus =3D csr_swap(CSR_HSTATUS, gcntx->hstatus); =20 __kvm_riscv_switch_to(&vcpu->arch); =20 gcntx->hstatus =3D csr_swap(CSR_HSTATUS, hcntx->hstatus); + + trap->htval =3D csr_read(CSR_HTVAL); + trap->htinst =3D csr_read(CSR_HTINST); } =20 + trap->sepc =3D gcntx->sepc; + trap->scause =3D csr_read(CSR_SCAUSE); + trap->stval =3D csr_read(CSR_STVAL); + vcpu->arch.last_exit_cpu =3D vcpu->cpu; guest_state_exit_irqoff(); kvm_riscv_vcpu_swap_in_host_state(vcpu); @@ -929,22 +948,11 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) =20 guest_timing_enter_irqoff(); =20 - kvm_riscv_vcpu_enter_exit(vcpu); + kvm_riscv_vcpu_enter_exit(vcpu, &trap); =20 vcpu->mode =3D OUTSIDE_GUEST_MODE; vcpu->stat.exits++; =20 - /* - * Save SCAUSE, STVAL, HTVAL, and HTINST because we might - * get an interrupt between __kvm_riscv_switch_to() and - * local_irq_enable() which can potentially change CSRs. - */ - trap.sepc =3D vcpu->arch.guest_context.sepc; - trap.scause =3D csr_read(CSR_SCAUSE); - trap.stval =3D csr_read(CSR_STVAL); - trap.htval =3D ncsr_read(CSR_HTVAL); - trap.htinst =3D ncsr_read(CSR_HTINST); - /* Syncup interrupts state with HW */ kvm_riscv_vcpu_sync_interrupts(vcpu); =20 --=20 2.34.1