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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240719-support_vendor_extensions-v3-3-0af7587bbec0@rivosinc.com> References: <20240719-support_vendor_extensions-v3-0-0af7587bbec0@rivosinc.com> In-Reply-To: <20240719-support_vendor_extensions-v3-0-0af7587bbec0@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Evan Green , Andy Chiu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721405735; l=4598; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=CjE8/rzubqx5R8Iz4IqjgB80B9gjcI9d7XpRrk2z8Qs=; b=cgJc9U8CKeGbQmMhF8nkxrxoy872cNjd9xtHNOdycdagYpu0adcmK3V/345qAoSy1eexq5Mbd EKmq84TacEsAj+nLjgQyW06Q3rDCun28yf2myFXx3Rta5jBdj3j6Hqo X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Vendor extensions are maintained in per-vendor structs (separate from standard extensions which live in riscv_isa). Create vendor variants for the existing extension helpers to interface with the riscv_isa_vendor bitmaps. Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley Reviewed-by: Andy Chiu --- arch/riscv/include/asm/vendor_extensions.h | 83 ++++++++++++++++++++++++++= ++++ drivers/perf/riscv_pmu_sbi.c | 3 +- 2 files changed, 85 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/vendor_extensions.h b/arch/riscv/includ= e/asm/vendor_extensions.h index 5fca550fc1f6..04d72b02ae6b 100644 --- a/arch/riscv/include/asm/vendor_extensions.h +++ b/arch/riscv/include/asm/vendor_extensions.h @@ -42,8 +42,91 @@ extern const size_t riscv_isa_vendor_ext_list_size; #define VENDOR_EXT_ALL_CPUS -1 =20 bool __riscv_isa_vendor_extension_available(int cpu, unsigned long vendor,= unsigned int bit); +#define riscv_cpu_isa_vendor_extension_available(cpu, vendor, ext) \ + __riscv_isa_vendor_extension_available(cpu, vendor, RISCV_ISA_VENDOR_EXT_= ##ext) #define riscv_isa_vendor_extension_available(vendor, ext) \ __riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor, \ RISCV_ISA_VENDOR_EXT_##ext) =20 +static __always_inline bool __riscv_has_extension_likely(const unsigned lo= ng vendor, + const unsigned long ext) +{ + asm goto(ALTERNATIVE("j %l[l_no]", "nop", %[vendor], %[ext], 1) + : + : [vendor] "i" (vendor), [ext] "i" (ext) + : + : l_no); + + return true; +l_no: + return false; +} + +static __always_inline bool __riscv_has_extension_unlikely(const unsigned = long vendor, + const unsigned long ext) +{ + asm goto(ALTERNATIVE("nop", "j %l[l_yes]", %[vendor], %[ext], 1) + : + : [vendor] "i" (vendor), [ext] "i" (ext) + : + : l_yes); + + return false; +l_yes: + return true; +} + +static __always_inline bool riscv_has_vendor_extension_likely(const unsign= ed long vendor, + const unsigned long ext) +{ + if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) + return false; + + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) + return __riscv_has_extension_likely(vendor, + ext + RISCV_VENDOR_EXT_ALTERNATIVES_BASE); + + return __riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor= , ext); +} + +static __always_inline bool riscv_has_vendor_extension_unlikely(const unsi= gned long vendor, + const unsigned long ext) +{ + if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) + return false; + + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) + return __riscv_has_extension_unlikely(vendor, + ext + RISCV_VENDOR_EXT_ALTERNATIVES_BASE); + + return __riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor= , ext); +} + +static __always_inline bool riscv_cpu_has_vendor_extension_likely(const un= signed long vendor, + int cpu, const unsigned long ext) +{ + if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) + return false; + + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && + __riscv_has_extension_likely(vendor, ext + RISCV_VENDOR_EXT_ALTERNATI= VES_BASE)) + return true; + + return __riscv_isa_vendor_extension_available(cpu, vendor, ext); +} + +static __always_inline bool riscv_cpu_has_vendor_extension_unlikely(const = unsigned long vendor, + int cpu, + const unsigned long ext) +{ + if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) + return false; + + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && + __riscv_has_extension_unlikely(vendor, ext + RISCV_VENDOR_EXT_ALTERNA= TIVES_BASE)) + return true; + + return __riscv_isa_vendor_extension_available(cpu, vendor, ext); +} + #endif /* _ASM_VENDOR_EXTENSIONS_H */ diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 16daebd0af1e..36d128ff166f 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -1099,7 +1099,8 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, = struct platform_device *pde riscv_cached_mimpid(0) =3D=3D 0) { riscv_pmu_irq_num =3D THEAD_C9XX_RV_IRQ_PMU; riscv_pmu_use_irq =3D true; - } else if (riscv_isa_vendor_extension_available(ANDES_VENDOR_ID, XANDESPM= U) && + } else if (riscv_has_vendor_extension_unlikely(ANDES_VENDOR_ID, + RISCV_ISA_VENDOR_EXT_XANDESPMU) && IS_ENABLED(CONFIG_ANDES_CUSTOM_PMU)) { riscv_pmu_irq_num =3D ANDES_SLI_CAUSE_BASE + ANDES_RV_IRQ_PMOVI; riscv_pmu_use_irq =3D true; --=20 2.44.0