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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240719-support_vendor_extensions-v3-2-0af7587bbec0@rivosinc.com> References: <20240719-support_vendor_extensions-v3-0-0af7587bbec0@rivosinc.com> In-Reply-To: <20240719-support_vendor_extensions-v3-0-0af7587bbec0@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Evan Green , Andy Chiu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721405734; l=2560; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=jX1rj/5Eo6K4VCkcWXFPVGV22tyIjfGbooFelFlP1yQ=; b=lhgzvNChjg8kplCDzaODRjelwprExmqYizaI7GahQwX36jwYoLg90IMReAZacNf3LCHSV3OJi 4i7f2uis6h6DZOqSKfRpKT76WiHAFmjVrX/9dVn+wV7FBGGLky57PIx X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= All of the supported vendor extensions that have been listed in riscv_isa_vendor_ext_list can be exported through /proc/cpuinfo. Signed-off-by: Charlie Jenkins Reviewed-by: Evan Green Reviewed-by: Conor Dooley --- arch/riscv/kernel/cpu.c | 35 ++++++++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index c1f3655238fd..f6b13e9f5e6c 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -16,6 +16,7 @@ #include #include #include +#include =20 bool arch_match_cpu_phys_id(int cpu, u64 phys_id) { @@ -235,7 +236,33 @@ arch_initcall(riscv_cpuinfo_init); =20 #ifdef CONFIG_PROC_FS =20 -static void print_isa(struct seq_file *f, const unsigned long *isa_bitmap) +#define ALL_CPUS -1 + +static void print_vendor_isa(struct seq_file *f, int cpu) +{ + struct riscv_isavendorinfo *vendor_bitmap; + struct riscv_isa_vendor_ext_data_list *ext_list; + const struct riscv_isa_ext_data *ext_data; + + for (int i =3D 0; i < riscv_isa_vendor_ext_list_size; i++) { + ext_list =3D riscv_isa_vendor_ext_list[i]; + ext_data =3D riscv_isa_vendor_ext_list[i]->ext_data; + + if (cpu =3D=3D ALL_CPUS) + vendor_bitmap =3D &ext_list->all_harts_isa_bitmap; + else + vendor_bitmap =3D &ext_list->per_hart_isa_bitmap[cpu]; + + for (int j =3D 0; j < ext_list->ext_data_count; j++) { + if (!__riscv_isa_extension_available(vendor_bitmap->isa, ext_data[j].id= )) + continue; + + seq_printf(f, "_%s", ext_data[j].name); + } + } +} + +static void print_isa(struct seq_file *f, const unsigned long *isa_bitmap,= int cpu) { =20 if (IS_ENABLED(CONFIG_32BIT)) @@ -254,6 +281,8 @@ static void print_isa(struct seq_file *f, const unsigne= d long *isa_bitmap) seq_printf(f, "%s", riscv_isa_ext[i].name); } =20 + print_vendor_isa(f, cpu); + seq_puts(f, "\n"); } =20 @@ -316,7 +345,7 @@ static int c_show(struct seq_file *m, void *v) * line. */ seq_puts(m, "isa\t\t: "); - print_isa(m, NULL); + print_isa(m, NULL, ALL_CPUS); print_mmu(m); =20 if (acpi_disabled) { @@ -338,7 +367,7 @@ static int c_show(struct seq_file *m, void *v) * additional extensions not present across all harts. */ seq_puts(m, "hart isa\t: "); - print_isa(m, hart_isa[cpu_id].isa); + print_isa(m, hart_isa[cpu_id].isa, cpu_id); seq_puts(m, "\n"); =20 return 0; --=20 2.44.0