From nobody Wed Dec 17 01:11:21 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20BEB13E41D for ; Thu, 18 Jul 2024 13:48:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721310492; cv=none; b=shTN9lolma0SSEmo67X+GkO4VzvbxzCdq4K6hqfBq6XHoFFjKaqQJrAGNwFWHdRD4mf+LrY1htYGYvz2Cmen5uLRXStKDYhrHppmgJa7NdnUofIFsfavBH3ns5hGZwx8fg8JrCYTjgJmRsIOhhjr2J/o12QAXHhN40LBOP9q+eQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721310492; c=relaxed/simple; bh=rDL/H4swq5vWFG8nI1kb1FbbSTKnnKfTWZQMQdVPLuo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aAOi7whxthPvRJQsvQWfqnBmo+kF+fUjnaeTSbSNYtko+pAdDRS4wIAus9mSs7N9rtT2VDuMPNSmvHmLbGwwiooA//SyPBHDLI1cqeE9p+J9JkNrhNnnGFdvRyCFC+vfCtkybO98CsYUThxYz4Hm5MA6PDJwu00evc8hXItDNmI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=MU2toyyk; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=k7umEflX; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="MU2toyyk"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="k7umEflX" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1721310489; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RTXkR8T3kLHV3No5jIU3m0/aEpNcwQkpCfNEeOLSNS4=; b=MU2toyykCBl9x7ohgzejkx5R0cfcJS97sJd3UJxrSMDdU/pk8KhkkyXy0BGFOoj7OvEEdW YHf27rkSXETcznuzt2uaIXCVyX4pZuUSW+ywPJzhH2IHr5jj0o8r9Y9r0fdSaxSKhlOvFt 2jfNdrpoCd7ZLvX4UjrXJ5IbKkjBQXOx4UewgDA2Cq9SVODOWMNjaJktmlDExSTkO3unNW kaCT8MZMQKXtrbox7jDwb7WjfaoZOWf239Zjf9Q6G4o1Fs2KvObiY0wtv/ErzRUjDSKZO7 Giq+AE/I3wK2Nil/YfVMZafVYeA+BFyuUla0pHV/RiWOkZguT7qC6bhc32Fvag== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1721310489; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RTXkR8T3kLHV3No5jIU3m0/aEpNcwQkpCfNEeOLSNS4=; b=k7umEflXbJReBenA8FAmSzm0EIiIwUPnjag2Rnmfc36Dbh24Vh/IHYJTBOJ2UDIJAxO2ae NYkCPgGLhFuWjuCA== To: Borislav Petkov , Ingo Molnar , Dave Hansen , "H. Peter Anvin" , x86@kernel.org, x86-cpuid@lists.linux.dev Cc: Thomas Gleixner , linux-kernel@vger.kernel.org, "Ahmed S. Darwish" Subject: [PATCH v1 1/9] tools/x86/kcpuid: Remove unused variable Date: Thu, 18 Jul 2024 15:47:41 +0200 Message-ID: <20240718134755.378115-2-darwi@linutronix.de> In-Reply-To: <20240718134755.378115-1-darwi@linutronix.de> References: <20240718134755.378115-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Global variable "num_leafs" is set in multiple places but is never read anywhere. Remove it. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index 24b7d017ec2c..e1973d8b322e 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -76,7 +76,6 @@ struct cpuid_range { */ struct cpuid_range *leafs_basic, *leafs_ext; =20 -static int num_leafs; static bool is_amd; static bool show_details; static bool show_raw; @@ -246,7 +245,6 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax) allzero =3D cpuid_store(range, f, subleaf, eax, ebx, ecx, edx); if (allzero) continue; - num_leafs++; =20 if (!has_subleafs(f)) continue; @@ -272,7 +270,6 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax) eax, ebx, ecx, edx); if (allzero) continue; - num_leafs++; } =20 } --=20 2.45.2 From nobody Wed Dec 17 01:11:21 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82EB0140E37 for ; Thu, 18 Jul 2024 13:48:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721310495; cv=none; b=kaEj5PbhbktD8SpZnUQS8VEtLK5wBR9s/RcrC4dQhz6njasg0y1RCMdkCgRja4KZIlk9Zj5fh3kY//pMmoj3o3tTybMyxga/axPIAAmPlYA+lybP3h/TiHU2WnkNcl2PDhIXZ8Pv1JAE6Qtjs9eg90HARRHb85fWSjhWBNTpEgU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721310495; c=relaxed/simple; bh=BGGsL3a5xjiuuIDamsAibYynkz0WjXbniB4VwvZ52b4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=celqRWC89wfG6xM3d2fY981QL8pfOjsGn0ccGufQuj1ybvD5CZ9bPRBbZccqC0YXIrXH/jXSG34O6Av/5XUaDg9MCVrOd46Ua6/UR0DzBceifjwdzQ2LtJLyaPjrdPcc01+GmtyLgSQeMcpfy642ygcIOId0IQgb0Bgte5XJjP4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=DAYenlJc; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=onVoMKfr; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="DAYenlJc"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="onVoMKfr" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1721310492; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7Umcf2zmF9IhfYteUxUaw3o2Qql3nqUK1ghOyWeUxCc=; b=DAYenlJcfPZj2ref++6hNSl4di3+nEIXIn+SVlBVh5x1KFa/Hs5aMClhJov2aKAmCFhs2q cHGmSyl8r9JPiyYiXyny71hz7uZCQoWDS4x6veG/iQuNpLptW0qCtC/O5fWwJNJR2Awcj/ /3p5oVwjftohnMpLcZ1j4x0tzv4kzvgXnIo1KZPCMUWHJwRt31OyzuM6WSP4ABuIXU7WJ4 eKlPf816yJzcL8LjazUfY2k9F9weuMZ20ycUjJOzBbW69t65I9y49GCSzxB6nGvjcKiQS4 I58GBGVWrPykmvncRfuRcbtFQ4OjhbXg1wcrJxyCM7FJVxDSp3U/Kr5s6awAog== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1721310492; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7Umcf2zmF9IhfYteUxUaw3o2Qql3nqUK1ghOyWeUxCc=; b=onVoMKfr5nAYPOhobyB1ZdHEBZL5emA1sIX0nN2yFXQqjN6lPfkDOFNNbGG5m6nCYAZcu4 jHfjfAAjkuovPQAQ== To: Borislav Petkov , Ingo Molnar , Dave Hansen , "H. Peter Anvin" , x86@kernel.org, x86-cpuid@lists.linux.dev Cc: Thomas Gleixner , linux-kernel@vger.kernel.org, "Ahmed S. Darwish" Subject: [PATCH v1 2/9] tools/x86/kcpuid: Properly align long-description columns Date: Thu, 18 Jul 2024 15:47:42 +0200 Message-ID: <20240718134755.378115-3-darwi@linutronix.de> In-Reply-To: <20240718134755.378115-1-darwi@linutronix.de> References: <20240718134755.378115-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When kcpuid is invoked with "--all --details", the detailed description column is not properly aligned for all bitfield rows: CPUID_0x4_ECX[0x0]: cache_level : 0x1 - Cache Level ... cache_self_init - Cache Self Initialization This is due to differences in output handling between boolean single-bit "bitflags" and multi-bit bitfields. For the former, the bitfield's value is not outputted as it is implied to be true by just outputting the bitflag's name in its respective line. If long descriptions were requested through the --all parameter, properly align the bitflag's description columns through extra tabs. With that, the sample output above becomes: CPUID_0x4_ECX[0x0]: cache_level : 0x1 - Cache Level ... cache_self_init - Cache Self Initialization Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index e1973d8b322e..08f64d9ecb40 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -449,8 +449,9 @@ static void decode_bits(u32 value, struct reg_desc *rde= sc, enum cpuid_reg reg) if (start =3D=3D end) { /* single bit flag */ if (value & (1 << start)) - printf("\t%-20s %s%s\n", + printf("\t%-20s %s%s%s\n", bdesc->simp, + show_flags_only ? "" : "\t\t\t", show_details ? "-" : "", show_details ? bdesc->detail : "" ); --=20 2.45.2 From nobody Wed Dec 17 01:11:21 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA1801422BC for ; Thu, 18 Jul 2024 13:48:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721310497; cv=none; b=PdhBjlCoe2tUivgYsgPMAyzGtUZ/D+hPHpNRrtme6nmQvi7eaomusGmGiD78S07HJmkJMWtrCCsjXJaKxqoFAe5zAZpQzKLEl8iA3bzzNsZcmOnb1tqi19GvZ75UcC/Visnbac7iUlsD+bhAgp7yHzCeeC1Xhs9lxMqsoOgU+BY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721310497; c=relaxed/simple; bh=ieb26+HvROHpjrBlsfNQn3VahOfpbPTOekx+lC0dgHM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UFYHdXtvGn7YEd09flKLGY3kboMd+PSoFiDQpcgCMjLScdrMLpK5YNagi/wA5OnyAlrO3rKsTnubGgW//Lt/kKPw5Y+AwMOKmcoS4tfjqxCpV/HamzjbvkRS+nVp3umY68wobWko5ps6GbMMVVgWzXqBREu43mW184tcMQbbdh8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=1thGcdOs; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=hMmbL945; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="1thGcdOs"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="hMmbL945" From: "Ahmed S. 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Peter Anvin" , x86@kernel.org, x86-cpuid@lists.linux.dev Cc: Thomas Gleixner , linux-kernel@vger.kernel.org, "Ahmed S. Darwish" Subject: [PATCH v1 3/9] tools/x86/kcpuid: Set max possible subleaves count to 64 Date: Thu, 18 Jul 2024 15:47:43 +0200 Message-ID: <20240718134755.378115-4-darwi@linutronix.de> In-Reply-To: <20240718134755.378115-1-darwi@linutronix.de> References: <20240718134755.378115-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" cpuid.csv will be extended in further commits with all-publicly-known CPUID leaves and bitfields. One of the new leaves is 0xd for extended CPU state enumeration. Depending on XCR0 dword bits, it can export up to 64 subleaves. Set kcpuid.c MAX_SUBLEAF_NUM to 64. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index 08f64d9ecb40..a87cddc19554 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -203,7 +203,7 @@ static void raw_dump_range(struct cpuid_range *range) } } =20 -#define MAX_SUBLEAF_NUM 32 +#define MAX_SUBLEAF_NUM 64 struct cpuid_range *setup_cpuid_range(u32 input_eax) { u32 max_func, idx_func; --=20 2.45.2 From nobody Wed Dec 17 01:11:21 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E799142E8D for ; Thu, 18 Jul 2024 13:48:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721310501; cv=none; b=R2emWMpUTlPGiU1VVRwwoBndsQ51/whdq8xRldnrFopkjLxBUhhARcWUubMpPkXUqJNWRZw1FPsKVWU0ZhQ78zmoS1j+AzgH30z13cZag2hB4aFnVwN94XPxqhx9XmjehekBEP8/WJyIP8/g6vbn4DZySzbxGUCQ/Ypee6pI+Bo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721310501; c=relaxed/simple; bh=YQguu2KHDGLSQtluTqZhX9pzhXNXS2HlFcfYCnZAL4g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kFPoO9cqrqUSlNmW0cFTRaxbKBCcUK/vIwD+YA+wF7JwH5wfN9jJ+H3Nb1Kbu6dwFRyLvMjMg9hEv9H+PpbNgXmwQUjxca4lxE8PrslDMueasNuMuiako94qvvCk+IW5jzV2ur2IOuuh6VDoFGLk86X7c1gk0sV9UHGRLhCuEhE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Q2NJB9ej; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=FNm6GMU8; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Q2NJB9ej"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="FNm6GMU8" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1721310496; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cBX60tEUojcaueoLY683EuE1AdH6RbQ/WsO6+FqW4Yw=; b=Q2NJB9ejiD85toYHlbZryyW0wCDyPIww5b53tx6wEQJ0Hn66MC+EjzUUVpoAn7nisJlXFN 6rOqeGOWDb8AzqBTPmSqsOHt3NnDbvsmKGsQiofEgnkaI+b9yehF5l0nd+ACCZ23NincF7 icpii5kUuC4d9PYoEkKS/efTSRPtB43UrvH9bIdlkhwtnqXmpLFPWN2MN16NHcXov7hbvM Vj+4bZ9VJCLX4IoQyriFnyzADauazKtaQx8iSrV0rbu+79jGL425QMuCMClUAk+td8bBiv 0XLSAqiIpjAAROC8TrNtDR1fXOlBhq8fh+x1s2iUi5fl7p+XR5X/qIZ0e6QHpQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1721310496; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cBX60tEUojcaueoLY683EuE1AdH6RbQ/WsO6+FqW4Yw=; b=FNm6GMU8EJUJj9kUCgrv/mQlyVpncV/QhSwBcu/XMYBQsbNKgCWMWqOA9n9q6KF8dnhTXe KsruR9C7VMaTXiAw== To: Borislav Petkov , Ingo Molnar , Dave Hansen , "H. Peter Anvin" , x86@kernel.org, x86-cpuid@lists.linux.dev Cc: Thomas Gleixner , linux-kernel@vger.kernel.org, "Ahmed S. Darwish" Subject: [PATCH v1 4/9] tools/x86/kcpuid: Protect against faulty "max subleaf" values Date: Thu, 18 Jul 2024 15:47:44 +0200 Message-ID: <20240718134755.378115-5-darwi@linutronix.de> In-Reply-To: <20240718134755.378115-1-darwi@linutronix.de> References: <20240718134755.378115-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Protect against the kcpuid code parsing faulty max subleaf numbers through a min() expression. Thus, ensuring that max_subleaf will always be =E2=89=A4 MAX_SUBLEAF_NUM. Use "u32" for the subleaf numbers since kcpuid is compiled with -Wextra, which includes signed/unsigned comparisons warnings. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index a87cddc19554..c93015ee02e0 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -7,7 +7,8 @@ #include #include =20 -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#define min(a, b) (((a) < (b)) ? (a) : (b)) =20 typedef unsigned int u32; typedef unsigned long long u64; @@ -207,11 +208,10 @@ static void raw_dump_range(struct cpuid_range *range) struct cpuid_range *setup_cpuid_range(u32 input_eax) { u32 max_func, idx_func; - int subleaf; struct cpuid_range *range; + u32 subleaf, max_subleaf; u32 eax, ebx, ecx, edx; u32 f =3D input_eax; - int max_subleaf; bool allzero; =20 eax =3D input_eax; @@ -256,7 +256,7 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax) * others have to be tried (0xf) */ if (f =3D=3D 0x7 || f =3D=3D 0x14 || f =3D=3D 0x17 || f =3D=3D 0x18) - max_subleaf =3D (eax & 0xff) + 1; + max_subleaf =3D min((eax & 0xff) + 1, max_subleaf); =20 if (f =3D=3D 0xb) max_subleaf =3D 2; --=20 2.45.2 From nobody Wed Dec 17 01:11:21 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E3FD13E8AE for ; Thu, 18 Jul 2024 13:48:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721310502; cv=none; b=prK+W8pPwnoPXyrp9+vx8WZqHQ7GRiOzeulsFuaH0GbN3X7WTu8m7bedD7BQu8igoKxu53iz1boa1x5l2GgfJnEjUQRZrvrDSU/MRn+LdicwP6tasP7oKNlr0x+AywuPXeErB0+yTmr9Yw2eYnv7pOhmP5IhFnP4BzS5rIVUjis= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721310502; c=relaxed/simple; bh=3bnhIpIPATYvjQ1WJKVL2yW74O40GkBPPq/Iy/ikT+I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=otZ6dWRJc+AZyFB0i97Y7Ser8kr/4tJkO5U/vSeTpNJSoCKRWTcuAbmUAbCOvo+scAx8zU0QPx/jeDW7J8L+0ixMVGb2MTlw2WhHgWh5OLhSd31T2VnuF/kp33qusIQsUTmd9PmJdcPwXtOxRerZJs4ctQliuNpKGS287lI4eCI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=bj1wk4v+; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ipOCnBt0; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="bj1wk4v+"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ipOCnBt0" From: "Ahmed S. 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Peter Anvin" , x86@kernel.org, x86-cpuid@lists.linux.dev Cc: Thomas Gleixner , linux-kernel@vger.kernel.org, "Ahmed S. Darwish" Subject: [PATCH v1 5/9] tools/x86/kcpuid: Strip bitfield names leading/trailing whitespace Date: Thu, 18 Jul 2024 15:47:45 +0200 Message-ID: <20240718134755.378115-6-darwi@linutronix.de> In-Reply-To: <20240718134755.378115-1-darwi@linutronix.de> References: <20240718134755.378115-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" While parsing and saving bitfield names from the CSV file, an extra leading space is copied verbatim. That extra space is not a big issue now, but further commits will add a new CSV file with much more padding for the bitfield's name column. Strip leading/trailing whitespaces while saving bitfield names. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index c93015ee02e0..ccbf3b36724f 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -381,7 +381,7 @@ static int parse_line(char *line) if (start) bdesc->start =3D strtoul(start, NULL, 0); =20 - strcpy(bdesc->simp, tokens[4]); + strcpy(bdesc->simp, strtok(tokens[4], " \t")); strcpy(bdesc->detail, tokens[5]); return 0; =20 --=20 2.45.2 From nobody Wed Dec 17 01:11:21 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBED7143891 for ; Thu, 18 Jul 2024 13:48:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721310504; cv=none; b=HrB5hE2m3l+/ovR08tERzTBKCpHzLRiIyrK+KgeejU6f/XIAvRfeyZz57b2VLMkf117jkbojPX5pRfhKoiHmXmxLrDQ3T8pNuT6y4vJtfTlmnozTuVnC7jqrhbbqu7GtsHcAuqYxldoyvdCCpi7ifx/2r2tpN1F+nXWgi3xY7/g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721310504; c=relaxed/simple; bh=omyVhzXb1POuFb3g3JKHB8dVH7nIuqPhKHn1MTX2ckE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=j0kdP7076akNqWLkf8pPI0z6pfpKaHKaBFBPPErj81I8xvUl2BH5KKvDd9dskBPOIHQxHnWoY8TtZ0c6YExL1aUGskFPVoEWjDKnX2jH24kBIEaTQWDqM2GoKTgjLX2QO7Ps4G7kebVt00n8vFuhl71wfV9AGWw3tatyK8IMv+Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=rM1IhNQy; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=KzGOUU6B; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="rM1IhNQy"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="KzGOUU6B" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1721310501; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3cssV5FJl85ZfJCD7dQMLFaOjrMNVhp+60A/FUsQHzE=; b=rM1IhNQyw8LaolVhJGtrW/+KMo+vOI/tp/1FC1I9mr+3qEgxarpuLJ6dWIGeYKpYuHiL+w SI9rYAHYEWk+JNRtVRKNhbmxMLci+EZF3FRx1cNtwaWrm73fkPUIqrXCbGfq/kllXVZc7Y 7uS8qX02cvPAaJkCYaJvKalOOYUWAYOUiejJP61MijpR84Ud5W8q5sq7AXqRrs77WUcocq 14K3VlSwdhsIgdA4/Rx/6KGBvmgoW2xI/7s9pa6gMcJeSqyP7ViX/OsCkqgehFzvtgfv9F BFwqYIIVq9OdkcKkQYlXLLiDN0Hgx8xOhCZNufL5WHZLG2zf0pmZ98hL5843Lw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1721310501; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3cssV5FJl85ZfJCD7dQMLFaOjrMNVhp+60A/FUsQHzE=; b=KzGOUU6BcdUc49xEDKBeAYnUTE4IbKG5NJB/n8UnKKO64UDZJHZGrxPNeZIuDF5cd7RXpW 8p5WDgU8qJdh0RAw== To: Borislav Petkov , Ingo Molnar , Dave Hansen , "H. Peter Anvin" , x86@kernel.org, x86-cpuid@lists.linux.dev Cc: Thomas Gleixner , linux-kernel@vger.kernel.org, "Ahmed S. Darwish" Subject: [PATCH v1 6/9] tools/x86/kcpuid: Recognize all leaves with subleaves Date: Thu, 18 Jul 2024 15:47:46 +0200 Message-ID: <20240718134755.378115-7-darwi@linutronix.de> In-Reply-To: <20240718134755.378115-1-darwi@linutronix.de> References: <20240718134755.378115-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" cpuid.csv will be extended in further commits with all-publicly-known CPUID leaves and bitfields. Thus, modify has_subleafs() to identify all known leaves with subleaves. Remove the redundant "is_amd" check since all x86 vendors already report the maxium supported extended leaf at leaf 0x80000000 EAX register. The extra mentioned leaves are: - Leaf 0x12, Intel Software Guard Extensions (SGX) enumeration - Leaf 0x14, Intel process trace (PT) enumeration - Leaf 0x17, Intel SoC vendor attributes enumeration - Leaf 0x1b, Intel PCONFIG (Platform configuration) enumeration - Leaf 0x1d, Intel AMX (Advanced Matrix Extensions) tile information - Leaf 0x1f, Intel v2 extended topology enumeration - Leaf 0x23, Intel ArchPerfmonExt (Architectural PMU ext) enumeration - Leaf 0x80000020, AMD Platform QoS extended features enumeration - Leaf 0x80000026, AMD v2 extended topology enumeration Set the 'max_subleaf' variable for all the newly marked leaves with extra subleaves. Ideally, this should be fetched from the CSV file instead, but the current kcpuid code architecture has two runs: one run to serially invoke the cpuid instructions and save all the output in-memory, and one run to parse this in-memory output through the CSV specification. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 39 ++++++++++++++++------------------ 1 file changed, 18 insertions(+), 21 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index ccbf3b36724f..beb4fde48145 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -98,27 +98,17 @@ static inline void cpuid(u32 *eax, u32 *ebx, u32 *ecx, = u32 *edx) =20 static inline bool has_subleafs(u32 f) { - if (f =3D=3D 0x7 || f =3D=3D 0xd) - return true; - - if (is_amd) { - if (f =3D=3D 0x8000001d) + u32 with_subleaves[] =3D { + 0x4, 0x7, 0xb, 0xd, 0xf, 0x10, 0x12, + 0x14, 0x17, 0x18, 0x1b, 0x1d, 0x1f, 0x23, + 0x8000001d, 0x80000020, 0x80000026, + }; + + for (unsigned i =3D 0; i < ARRAY_SIZE(with_subleaves); i++) + if (f =3D=3D with_subleaves[i]) return true; - return false; - } =20 - switch (f) { - case 0x4: - case 0xb: - case 0xf: - case 0x10: - case 0x14: - case 0x18: - case 0x1f: - return true; - default: - return false; - } + return false; } =20 static void leaf_print_raw(struct subleaf *leaf) @@ -255,11 +245,18 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax) * Some can provide the exact number of subleafs, * others have to be tried (0xf) */ - if (f =3D=3D 0x7 || f =3D=3D 0x14 || f =3D=3D 0x17 || f =3D=3D 0x18) + if (f =3D=3D 0x7 || f =3D=3D 0x14 || f =3D=3D 0x17 || f =3D=3D 0x18 || f= =3D=3D 0x1d) max_subleaf =3D min((eax & 0xff) + 1, max_subleaf); - if (f =3D=3D 0xb) max_subleaf =3D 2; + if (f =3D=3D 0x1f) + max_subleaf =3D 6; + if (f =3D=3D 0x23) + max_subleaf =3D 4; + if (f =3D=3D 0x80000020) + max_subleaf =3D 4; + if (f =3D=3D 0x80000026) + max_subleaf =3D 5; =20 for (subleaf =3D 1; subleaf < max_subleaf; subleaf++) { eax =3D f; --=20 2.45.2 From nobody Wed Dec 17 01:11:21 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61B9A13E88B for ; Thu, 18 Jul 2024 13:48:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721310506; cv=none; b=i21WD7uIvm3NJ158Opxc/KRhQLVbM8w6AhF6ewvYtC45T6BoXyF+D+dHi+X2l3oLorixWrIsPHDFyeXETd6J5wk6Aq0qFJFDrkdsgTiR0b5LK7/pSAkyg6RlMSfRRxERZR7o93vCEAlBx0WzakVNHuuEBp6r8q07vF1jP/IqwK8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721310506; c=relaxed/simple; bh=OOTpUM8hhqy1KXrLRcwqprmY1TDDOxn6rAHfKP7MTQo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KJjxwhNEe9PVjGygiOh94QHiwdAGqdY/9740uXmGYkLO6rphqVoPa1wRnHjKYmjTWFPPBO8pOHPeZb3afOaKA9agiGYKZKjGNzRBnP5swMQJms8Jv6LtiY468FdnTd6Ebw2Pbv4B95YRugNXyI2AE8TmCOCwVE6wM8xxQX+QieE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Xmoymz7G; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=43CymuwJ; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Xmoymz7G"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="43CymuwJ" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1721310503; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nh3LDCA/zxyfmQviVCKs8MIpfCuX+Z1MRa25LfO8bGY=; b=Xmoymz7Gdraf8PrFInCcWxzhzMIf9DzldEGL404TTFXUsfbLZy5h9sPviND2kL4PacaytR wB7jQYWnRJltrVyKq7UkNGFZSrnfwtbOqtDxdUfzbxIIIoPdwr4udNiofaMmoskTmTOBzF dzfgT3r9xUeBzsengkA9r/d569gJ9uEyGhJeJCf1dI96dyidCl5Y1zIsxWlAk1dM56K5qO 0I91IbqO8DcJzemSyKKmhj5qY1vnoCwUFaZbpEFxHQunk3ctYeQGbJXpflgsIJfygGl1T4 Mm19Cr0B5+BL2Im5lqch513Zcy/TYbh8lYC2LffOWvhJa0L9zM1lvaH08+BehA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1721310503; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nh3LDCA/zxyfmQviVCKs8MIpfCuX+Z1MRa25LfO8bGY=; b=43CymuwJBuUEkFxJpj5oMTX9npWECbUVnKFx0y1Ri9Hm5ucnnXvh6iXkKrK7k9gaSRe/P0 A39YFd9sRiXqazCA== To: Borislav Petkov , Ingo Molnar , Dave Hansen , "H. Peter Anvin" , x86@kernel.org, x86-cpuid@lists.linux.dev Cc: Thomas Gleixner , linux-kernel@vger.kernel.org, "Ahmed S. Darwish" Subject: [PATCH v1 7/9] tools/x86/kcpuid: Parse subleaf ranges if provided Date: Thu, 18 Jul 2024 15:47:47 +0200 Message-ID: <20240718134755.378115-8-darwi@linutronix.de> In-Reply-To: <20240718134755.378115-1-darwi@linutronix.de> References: <20240718134755.378115-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It's a common pattern in cpuid leaves to have the same bitfields format repeated across a number of subleaves. Typically, this is used for enumerating hierarchial structures like cache and TLB levels, CPU topology levels, etc. Modify kcpuid.c to handle subleaf ranges in the CSV file subleaves column. For example, make it able to parse lines in the form: # LEAF, SUBLEAVES, reg, bits, short_name , ... 0xb, 1:0, eax, 4:0, x2apic_id_shift , ... 0xb, 1:0, ebx, 15:0, domain_lcpus_count , ... 0xb, 1:0, ecx, 7:0, domain_nr , ... This way, full output can be printed to the user. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 50 ++++++++++++++++++++++------------ 1 file changed, 32 insertions(+), 18 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index beb4fde48145..c321db86750b 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -307,6 +307,8 @@ static int parse_line(char *line) struct bits_desc *bdesc; int reg_index; char *start, *end; + u32 subleaf_start, subleaf_end; + unsigned bit_start, bit_end; =20 /* Skip comments and NULL line */ if (line[0] =3D=3D '#' || line[0] =3D=3D '\n') @@ -345,13 +347,25 @@ static int parse_line(char *line) return 0; =20 /* subleaf */ - sub =3D strtoul(tokens[1], NULL, 0); - if ((int)sub > func->nr) - return -1; + buf =3D tokens[1]; + end =3D strtok(buf, ":"); + start =3D strtok(NULL, ":"); + subleaf_end =3D strtoul(end, NULL, 0); + + /* A subleaf range is given? */ + if (start) { + subleaf_start =3D strtoul(start, NULL, 0); + subleaf_end =3D min(subleaf_end, (u32)(func->nr - 1)); + if (subleaf_start > subleaf_end) + return 0; + } else { + subleaf_start =3D subleaf_end; + if (subleaf_start > (u32)(func->nr - 1)) + return 0; + } =20 - leaf =3D &func->leafs[sub]; + /* register */ buf =3D tokens[2]; - if (strcasestr(buf, "EAX")) reg_index =3D R_EAX; else if (strcasestr(buf, "EBX")) @@ -363,23 +377,23 @@ static int parse_line(char *line) else goto err_exit; =20 - reg =3D &leaf->info[reg_index]; - bdesc =3D ®->descs[reg->nr++]; - /* bit flag or bits field */ buf =3D tokens[3]; - end =3D strtok(buf, ":"); - bdesc->end =3D strtoul(end, NULL, 0); - bdesc->start =3D bdesc->end; - - /* start !=3D NULL means it is bit fields */ start =3D strtok(NULL, ":"); - if (start) - bdesc->start =3D strtoul(start, NULL, 0); - - strcpy(bdesc->simp, strtok(tokens[4], " \t")); - strcpy(bdesc->detail, tokens[5]); + bit_end =3D strtoul(end, NULL, 0); + bit_start =3D (start) ? strtoul(start, NULL, 0) : bit_end; + + for (sub =3D subleaf_start; sub <=3D subleaf_end; sub++) { + leaf =3D &func->leafs[sub]; + reg =3D &leaf->info[reg_index]; + bdesc =3D ®->descs[reg->nr++]; + + bdesc->end =3D bit_end; + bdesc->start =3D bit_start; + strcpy(bdesc->simp, strtok(tokens[4], " \t")); + strcpy(bdesc->detail, tokens[5]); + } return 0; =20 err_exit: --=20 2.45.2 From nobody Wed Dec 17 01:11:21 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0D7D1448D7 for ; Thu, 18 Jul 2024 13:48:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721310513; cv=none; b=MSlFnGMG4W4q7Gk19D5wDk97xCiYyxyah+jNIihPzY9faj1DxqSQdCxk64RZKjqQy0BdEtkuigSGrjuRyT4S8YaFYFtnHYUiRRdrZNzWS048Zy0EqQH7oopxVcdsyh+tXQ0CUepEC9Dh9fYLG/YMoRDioLU1HRyXw7KakjFuEPc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721310513; c=relaxed/simple; bh=JkwuSJ0fPqbsgPRmHJ4QugYXJ43TWCSddAyaB7tJZ+E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rQ5DyJzAxQeseaMbYR6qUukXrE2ff/GRW0ORUkizBV3uFkIUMnPyHplvNs5P8CvsXX5NFth4+H/IxhyAtK+NRQdsPWiFb5baJbM3K/Ti9EjfL6GGPEa47uikxyYA7i1cUnifM7MamhjUjS9KIdoeNGVIwAoExQ29EzzBjhKd/lQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=JFrLQO6g; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=K4ABq+SK; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="JFrLQO6g"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="K4ABq+SK" From: "Ahmed S. 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Peter Anvin" , x86@kernel.org, x86-cpuid@lists.linux.dev Cc: Thomas Gleixner , linux-kernel@vger.kernel.org, "Ahmed S. Darwish" Subject: [PATCH v1 8/9] tools/x86/kcpuid: Introduce a complete cpuid bitfields CSV file Date: Thu, 18 Jul 2024 15:47:48 +0200 Message-ID: <20240718134755.378115-9-darwi@linutronix.de> In-Reply-To: <20240718134755.378115-1-darwi@linutronix.de> References: <20240718134755.378115-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable For parsing the cpuid bitfields, kcpuid uses an incomplete CSV file with 300+ bitfields. Use an auto-generated CSV file from the x86-cpuid.org project instead. It provides complete bitfields coverage: 830+ bitfields, all with proper descriptions. The auto-generated file has the following blurb automatically added: # SPDX-License-Identifier: CC0-1.0 # Generator: x86-cpuid-db v1.0 The generator tag includes the project's workspace "git describe" version string. It is intended for projects like KernelCI, to aid in verifying that the auto-generated files have not been tampered with. The file also has the blurb: # Auto-generated file. # Please submit all updates and bugfixes to https://x86-cpuid.org It's thus kindly requested that the Linux kernel's x86 tree maintainers enforce sending all updates to x86-cpuid.org's upstream database first, thus benefiting the whole ecosystem. Signed-off-by: Ahmed S. Darwish Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v1.0/LICENSE.rst Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db --- tools/arch/x86/kcpuid/cpuid.csv | 1430 ++++++++++++++++++++++--------- 1 file changed, 1016 insertions(+), 414 deletions(-) diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.= csv index e0c25b75327e..d751eb8585d0 100644 --- a/tools/arch/x86/kcpuid/cpuid.csv +++ b/tools/arch/x86/kcpuid/cpuid.csv @@ -1,451 +1,1053 @@ -# The basic row format is: -# LEAF, SUBLEAF, register_name, bits, short_name, long_description - -# Leaf 00H - 0, 0, EAX, 31:0, max_basic_leafs, Max input value for suppo= rted subleafs - -# Leaf 01H - 1, 0, EAX, 3:0, stepping, Stepping ID - 1, 0, EAX, 7:4, model, Model - 1, 0, EAX, 11:8, family, Family ID - 1, 0, EAX, 13:12, processor, Processor Type - 1, 0, EAX, 19:16, model_ext, Extended Model ID - 1, 0, EAX, 27:20, family_ext, Extended Family ID - - 1, 0, EBX, 7:0, brand, Brand Index - 1, 0, EBX, 15:8, clflush_size, CLFLUSH line size (value * 8= ) in bytes - 1, 0, EBX, 23:16, max_cpu_id, Maxim number of addressable lo= gic cpu in this package - 1, 0, EBX, 31:24, apic_id, Initial APIC ID - - 1, 0, ECX, 0, sse3, Streaming SIMD Extensions 3(SSE3) - 1, 0, ECX, 1, pclmulqdq, PCLMULQDQ instruction supported - 1, 0, ECX, 2, dtes64, DS area uses 64-bit layout - 1, 0, ECX, 3, mwait, MONITOR/MWAIT supported - 1, 0, ECX, 4, ds_cpl, CPL Qualified Debug Store which al= lows for branch message storage qualified by CPL - 1, 0, ECX, 5, vmx, Virtual Machine Extensions supported - 1, 0, ECX, 6, smx, Safer Mode Extension supported - 1, 0, ECX, 7, eist, Enhanced Intel SpeedStep Technology - 1, 0, ECX, 8, tm2, Thermal Monitor 2 - 1, 0, ECX, 9, ssse3, Supplemental Streaming SIMD Extensi= ons 3 (SSSE3) - 1, 0, ECX, 10, l1_ctx_id, L1 data cache could be set to e= ither adaptive mode or shared mode (check IA32_MISC_ENABLE bit 24 definitio= n) - 1, 0, ECX, 11, sdbg, IA32_DEBUG_INTERFACE MSR for silicon= debug supported - 1, 0, ECX, 12, fma, FMA extensions using YMM state suppor= ted - 1, 0, ECX, 13, cmpxchg16b, 'CMPXCHG16B - Compare and Exch= ange Bytes' supported - 1, 0, ECX, 14, xtpr_update, xTPR Update Control supported - 1, 0, ECX, 15, pdcm, Perfmon and Debug Capability present - 1, 0, ECX, 17, pcid, Process-Context Identifiers feature = present - 1, 0, ECX, 18, dca, Prefetching data from a memory mapped= device supported - 1, 0, ECX, 19, sse4_1, SSE4.1 feature present - 1, 0, ECX, 20, sse4_2, SSE4.2 feature present - 1, 0, ECX, 21, x2apic, x2APIC supported - 1, 0, ECX, 22, movbe, MOVBE instruction supported - 1, 0, ECX, 23, popcnt, POPCNT instruction supported - 1, 0, ECX, 24, tsc_deadline_timer, LAPIC supports one-sho= t operation using a TSC deadline value - 1, 0, ECX, 25, aesni, AESNI instruction supported - 1, 0, ECX, 26, xsave, XSAVE/XRSTOR processor extended sta= tes (XSETBV/XGETBV/XCR0) - 1, 0, ECX, 27, osxsave, OS has set CR4.OSXSAVE bit to ena= ble XSETBV/XGETBV/XCR0 - 1, 0, ECX, 28, avx, AVX instruction supported - 1, 0, ECX, 29, f16c, 16-bit floating-point conversion ins= truction supported - 1, 0, ECX, 30, rdrand, RDRAND instruction supported - - 1, 0, EDX, 0, fpu, x87 FPU on chip - 1, 0, EDX, 1, vme, Virtual-8086 Mode Enhancement - 1, 0, EDX, 2, de, Debugging Extensions - 1, 0, EDX, 3, pse, Page Size Extensions - 1, 0, EDX, 4, tsc, Time Stamp Counter - 1, 0, EDX, 5, msr, RDMSR and WRMSR Support - 1, 0, EDX, 6, pae, Physical Address Extensions - 1, 0, EDX, 7, mce, Machine Check Exception - 1, 0, EDX, 8, cx8, CMPXCHG8B instr - 1, 0, EDX, 9, apic, APIC on Chip - 1, 0, EDX, 11, sep, SYSENTER and SYSEXIT instrs - 1, 0, EDX, 12, mtrr, Memory Type Range Registers - 1, 0, EDX, 13, pge, Page Global Bit - 1, 0, EDX, 14, mca, Machine Check Architecture - 1, 0, EDX, 15, cmov, Conditional Move Instrs - 1, 0, EDX, 16, pat, Page Attribute Table - 1, 0, EDX, 17, pse36, 36-Bit Page Size Extension - 1, 0, EDX, 18, psn, Processor Serial Number - 1, 0, EDX, 19, clflush, CLFLUSH instr -# 1, 0, EDX, 20, - 1, 0, EDX, 21, ds, Debug Store - 1, 0, EDX, 22, acpi, Thermal Monitor and Software Control= led Clock Facilities - 1, 0, EDX, 23, mmx, Intel MMX Technology - 1, 0, EDX, 24, fxsr, XSAVE and FXRSTOR Instrs - 1, 0, EDX, 25, sse, SSE - 1, 0, EDX, 26, sse2, SSE2 - 1, 0, EDX, 27, ss, Self Snoop - 1, 0, EDX, 28, hit, Max APIC IDs - 1, 0, EDX, 29, tm, Thermal Monitor -# 1, 0, EDX, 30, - 1, 0, EDX, 31, pbe, Pending Break Enable - -# Leaf 02H -# cache and TLB descriptor info - -# Leaf 03H -# Precessor Serial Number, introduced on Pentium III, not valid for -# latest models - -# Leaf 04H -# thread/core and cache topology - 4, 0, EAX, 4:0, cache_type, Cache type like instr/data or = unified - 4, 0, EAX, 7:5, cache_level, Cache Level (starts at 1) - 4, 0, EAX, 8, cache_self_init, Cache Self Initialization - 4, 0, EAX, 9, fully_associate, Fully Associative cache -# 4, 0, EAX, 13:10, resvd, resvd - 4, 0, EAX, 25:14, max_logical_id, Max number of addressable = IDs for logical processors sharing the cache - 4, 0, EAX, 31:26, max_phy_id, Max number of addressable IDs = for processors in phy package - - 4, 0, EBX, 11:0, cache_linesize, Size of a cache line in by= tes - 4, 0, EBX, 21:12, cache_partition, Physical Line partitions - 4, 0, EBX, 31:22, cache_ways, Ways of associativity - 4, 0, ECX, 31:0, cache_sets, Number of Sets - 1 - 4, 0, EDX, 0, c_wbinvd, 1 means WBINVD/INVD is not ganra= nteed to act upon lower level caches of non-originating threads sharing thi= s cache - 4, 0, EDX, 1, c_incl, Whether cache is inclusive of lowe= r cache level - 4, 0, EDX, 2, c_comp_index, Complex Cache Indexing - -# Leaf 05H -# MONITOR/MWAIT - 5, 0, EAX, 15:0, min_mon_size, Smallest monitor line size in bytes - 5, 0, EBX, 15:0, max_mon_size, Largest monitor line size in bytes - 5, 0, ECX, 0, mwait_ext, Enum of Monitor-Mwait extensions suppo= rted - 5, 0, ECX, 1, mwait_irq_break, Largest monitor line size in byt= es - 5, 0, EDX, 3:0, c0_sub_stats, Number of C0* sub C-states supporte= d using MWAIT - 5, 0, EDX, 7:4, c1_sub_stats, Number of C1* sub C-states supporte= d using MWAIT - 5, 0, EDX, 11:8, c2_sub_stats, Number of C2* sub C-states supporte= d using MWAIT - 5, 0, EDX, 15:12, c3_sub_stats, Number of C3* sub C-states supporte= d using MWAIT - 5, 0, EDX, 19:16, c4_sub_stats, Number of C4* sub C-states supporte= d using MWAIT - 5, 0, EDX, 23:20, c5_sub_stats, Number of C5* sub C-states supporte= d using MWAIT - 5, 0, EDX, 27:24, c6_sub_stats, Number of C6* sub C-states supporte= d using MWAIT - 5, 0, EDX, 31:28, c7_sub_stats, Number of C7* sub C-states supporte= d using MWAIT - -# Leaf 06H -# Thermal & Power Management - - 6, 0, EAX, 0, dig_temp, Digital temperature sensor supported - 6, 0, EAX, 1, turbo, Intel Turbo Boost - 6, 0, EAX, 2, arat, Always running APIC timer -# 6, 0, EAX, 3, resv, Reserved - 6, 0, EAX, 4, pln, Power limit notifications supported - 6, 0, EAX, 5, ecmd, Clock modulation duty cycle extension suppo= rted - 6, 0, EAX, 6, ptm, Package thermal management supported - 6, 0, EAX, 7, hwp, HWP base register - 6, 0, EAX, 8, hwp_notify, HWP notification - 6, 0, EAX, 9, hwp_act_window, HWP activity window - 6, 0, EAX, 10, hwp_energy, HWP energy performance preference - 6, 0, EAX, 11, hwp_pkg_req, HWP package level request -# 6, 0, EAX, 12, resv, Reserved - 6, 0, EAX, 13, hdc, HDC base registers supported - 6, 0, EAX, 14, turbo3, Turbo Boost Max 3.0 - 6, 0, EAX, 15, hwp_cap, Highest Performance change supported - 6, 0, EAX, 16, hwp_peci, HWP PECI override is supported - 6, 0, EAX, 17, hwp_flex, Flexible HWP is supported - 6, 0, EAX, 18, hwp_fast, Fast access mode for the IA32_HWP_REQUE= ST MSR is supported -# 6, 0, EAX, 19, resv, Reserved - 6, 0, EAX, 20, hwp_ignr, Ignoring Idle Logical Processor HWP req= uest is supported - - 6, 0, EBX, 3:0, therm_irq_thresh, Number of Interrupt Thresholds = in Digital Thermal Sensor - 6, 0, ECX, 0, aperfmperf, Presence of IA32_MPERF and IA32_APERF - 6, 0, ECX, 3, energ_bias, Performance-energy bias preference su= pported - -# Leaf 07H -# ECX =3D=3D 0 -# AVX512 refers to https://en.wikipedia.org/wiki/AVX-512 -# XXX: Do we really need to enumerate each and every AVX512 sub features - - 7, 0, EBX, 0, fsgsbase, RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE sup= ported - 7, 0, EBX, 1, tsc_adjust, TSC_ADJUST MSR supported - 7, 0, EBX, 2, sgx, Software Guard Extensions - 7, 0, EBX, 3, bmi1, BMI1 - 7, 0, EBX, 4, hle, Hardware Lock Elision - 7, 0, EBX, 5, avx2, AVX2 -# 7, 0, EBX, 6, fdp_excp_only, x87 FPU Data Pointer updated only= on x87 exceptions - 7, 0, EBX, 7, smep, Supervisor-Mode Execution Prevention - 7, 0, EBX, 8, bmi2, BMI2 - 7, 0, EBX, 9, rep_movsb, Enhanced REP MOVSB/STOSB - 7, 0, EBX, 10, invpcid, INVPCID instruction - 7, 0, EBX, 11, rtm, Restricted Transactional Memory - 7, 0, EBX, 12, rdt_m, Intel RDT Monitoring capability - 7, 0, EBX, 13, depc_fpu_cs_ds, Deprecates FPU CS and FPU DS - 7, 0, EBX, 14, mpx, Memory Protection Extensions - 7, 0, EBX, 15, rdt_a, Intel RDT Allocation capability - 7, 0, EBX, 16, avx512f, AVX512 Foundation instr - 7, 0, EBX, 17, avx512dq, AVX512 Double and Quadword AVX512 instr - 7, 0, EBX, 18, rdseed, RDSEED instr - 7, 0, EBX, 19, adx, ADX instr - 7, 0, EBX, 20, smap, Supervisor Mode Access Prevention - 7, 0, EBX, 21, avx512ifma, AVX512 Integer Fused Multiply Add -# 7, 0, EBX, 22, resvd, resvd - 7, 0, EBX, 23, clflushopt, CLFLUSHOPT instr - 7, 0, EBX, 24, clwb, CLWB instr - 7, 0, EBX, 25, intel_pt, Intel Processor Trace instr - 7, 0, EBX, 26, avx512pf, Prefetch - 7, 0, EBX, 27, avx512er, AVX512 Exponent Reciproca instr - 7, 0, EBX, 28, avx512cd, AVX512 Conflict Detection instr - 7, 0, EBX, 29, sha, Intel Secure Hash Algorithm Extensions instr - 7, 0, EBX, 30, avx512bw, AVX512 Byte & Word instr - 7, 0, EBX, 31, avx512vl, AVX512 Vector Length Extentions (VL) - 7, 0, ECX, 0, prefetchwt1, X - 7, 0, ECX, 1, avx512vbmi, AVX512 Vector Byte Manipulation Instr= uctions - 7, 0, ECX, 2, umip, User-mode Instruction Prevention - - 7, 0, ECX, 3, pku, Protection Keys for User-mode pages - 7, 0, ECX, 4, ospke, CR4 PKE set to enable protection keys -# 7, 0, ECX, 16:5, resvd, resvd - 7, 0, ECX, 21:17, mawau, The value of MAWAU used by the BNDLDX and = BNDSTX instructions in 64-bit mode - 7, 0, ECX, 22, rdpid, RDPID and IA32_TSC_AUX -# 7, 0, ECX, 29:23, resvd, resvd - 7, 0, ECX, 30, sgx_lc, SGX Launch Configuration -# 7, 0, ECX, 31, resvd, resvd - -# Leaf 08H -# - - -# Leaf 09H -# Direct Cache Access (DCA) information - 9, 0, ECX, 31:0, dca_cap, The value of IA32_PLATFORM_DCA_CAP +# SPDX-License-Identifier: CC0-1.0 +# Generator: x86-cpuid-db v1.0 =20 -# Leaf 0AH -# Architectural Performance Monitoring # -# Do we really need to print out the PMU related stuff? -# Does normal user really care about it? +# Auto-generated file. +# Please submit all updates and bugfixes to https://x86-cpuid.org # - 0xA, 0, EAX, 7:0, pmu_ver, Performance Monitoring Unit versi= on - 0xA, 0, EAX, 15:8, pmu_gp_cnt_num, Numer of general-purose PM= U counters per logical CPU - 0xA, 0, EAX, 23:16, pmu_cnt_bits, Bit wideth of PMU counter - 0xA, 0, EAX, 31:24, pmu_ebx_bits, Length of EBX bit vector to = enumerate PMU events - - 0xA, 0, EBX, 0, pmu_no_core_cycle_evt, Core cycle event no= t available - 0xA, 0, EBX, 1, pmu_no_instr_ret_evt, Instruction retired = event not available - 0xA, 0, EBX, 2, pmu_no_ref_cycle_evt, Reference cycles eve= nt not available - 0xA, 0, EBX, 3, pmu_no_llc_ref_evt, Last-level cache refer= ence event not available - 0xA, 0, EBX, 4, pmu_no_llc_mis_evt, Last-level cache misse= s event not available - 0xA, 0, EBX, 5, pmu_no_br_instr_ret_evt, Branch instructio= n retired event not available - 0xA, 0, EBX, 6, pmu_no_br_mispredict_evt, Branch mispredic= t retired event not available - - 0xA, 0, ECX, 4:0, pmu_fixed_cnt_num, Performance Monitoring = Unit version - 0xA, 0, ECX, 12:5, pmu_fixed_cnt_bits, Numer of PMU counters = per logical CPU - -# Leaf 0BH -# Extended Topology Enumeration Leaf -# - - 0xB, 0, EAX, 4:0, id_shift, Number of bits to shift right on= x2APIC ID to get a unique topology ID of the next level type - 0xB, 0, EBX, 15:0, cpu_nr, Number of logical processors at th= is level type - 0xB, 0, ECX, 15:8, lvl_type, 0-Invalid 1-SMT 2-Core - 0xB, 0, EDX, 31:0, x2apic_id, x2APIC ID the current logical p= rocessor - - -# Leaf 0DH -# Processor Extended State =20 - 0xD, 0, EAX, 0, x87, X87 state - 0xD, 0, EAX, 1, sse, SSE state - 0xD, 0, EAX, 2, avx, AVX state - 0xD, 0, EAX, 4:3, mpx, MPX state - 0xD, 0, EAX, 7:5, avx512, AVX-512 state - 0xD, 0, EAX, 9, pkru, PKRU state - - 0xD, 0, EBX, 31:0, max_sz_xcr0, Maximum size (bytes) required= by enabled features in XCR0 - 0xD, 0, ECX, 31:0, max_sz_xsave, Maximum size (bytes) of the = XSAVE/XRSTOR save area - - 0xD, 1, EAX, 0, xsaveopt, XSAVEOPT available - 0xD, 1, EAX, 1, xsavec, XSAVEC and compacted form supported - 0xD, 1, EAX, 2, xgetbv, XGETBV supported - 0xD, 1, EAX, 3, xsaves, XSAVES/XRSTORS and IA32_XSS suppor= ted - - 0xD, 1, EBX, 31:0, max_sz_xcr0, Maximum size (bytes) required= by enabled features in XCR0 - 0xD, 1, ECX, 8, pt, PT state - 0xD, 1, ECX, 11, cet_usr, CET user state - 0xD, 1, ECX, 12, cet_supv, CET supervisor state - 0xD, 1, ECX, 13, hdc, HDC state - 0xD, 1, ECX, 16, hwp, HWP state - -# Leaf 0FH -# Intel RDT Monitoring - - 0xF, 0, EBX, 31:0, rmid_range, Maximum range (zero-based) of = RMID within this physical processor of all types - 0xF, 0, EDX, 1, l3c_rdt_mon, L3 Cache RDT Monitoring suppo= rted - - 0xF, 1, ECX, 31:0, rmid_range, Maximum range (zero-based) of = RMID of this types - 0xF, 1, EDX, 0, l3c_ocp_mon, L3 Cache occupancy Monitoring= supported - 0xF, 1, EDX, 1, l3c_tbw_mon, L3 Cache Total Bandwidth Moni= toring supported - 0xF, 1, EDX, 2, l3c_lbw_mon, L3 Cache Local Bandwidth Moni= toring supported +# The basic row format is: +# LEAF, SUBLEAVES, reg, bits, short_name , long_des= cription + +# Leaf 0H +# Maximum standard leaf number + CPU vendor string + + 0, 0, eax, 31:0, max_std_leaf , Highest = cpuid standard leaf supported + 0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vend= or ID string bytes 0 - 3 + 0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vend= or ID string bytes 8 - 11 + 0, 0, edx, 31:0, cpu_vendorid_1 , CPU vend= or ID string bytes 4 - 7 + +# Leaf 1H +# CPU FMS (Family/Model/Stepping) + standard feature flags + + 1, 0, eax, 3:0, stepping , Stepping= ID + 1, 0, eax, 7:4, base_model , Base CPU= model ID + 1, 0, eax, 11:8, base_family_id , Base CPU= family ID + 1, 0, eax, 13:12, cpu_type , CPU type + 1, 0, eax, 19:16, ext_model , Extended= CPU model ID + 1, 0, eax, 27:20, ext_family , Extended= CPU family ID + 1, 0, ebx, 7:0, brand_id , Brand in= dex + 1, 0, ebx, 15:8, clflush_size , CLFLUSH = instruction cache line size + 1, 0, ebx, 23:16, n_logical_cpu , Logical = CPU (HW threads) count + 1, 0, ebx, 31:24, local_apic_id , Initial = local APIC physical ID + 1, 0, ecx, 0, pni , Streamin= g SIMD Extensions 3 (SSE3) + 1, 0, ecx, 1, pclmulqdq , PCLMULQD= Q instruction support + 1, 0, ecx, 2, dtes64 , 64-bit D= S save area + 1, 0, ecx, 3, monitor , MONITOR/= MWAIT support + 1, 0, ecx, 4, ds_cpl , CPL Qual= ified Debug Store + 1, 0, ecx, 5, vmx , Virtual = Machine Extensions + 1, 0, ecx, 6, smx , Safer Mo= de Extensions + 1, 0, ecx, 7, est , Enhanced= Intel SpeedStep + 1, 0, ecx, 8, tm2 , Thermal = Monitor 2 + 1, 0, ecx, 9, ssse3 , Suppleme= ntal SSE3 + 1, 0, ecx, 10, cid , L1 Conte= xt ID + 1, 0, ecx, 11, sdbg , Sillicon= Debug + 1, 0, ecx, 12, fma , FMA exte= nsions using YMM state + 1, 0, ecx, 13, cx16 , CMPXCHG1= 6B instruction support + 1, 0, ecx, 14, xtpr , xTPR Upd= ate Control + 1, 0, ecx, 15, pdcm , Perfmon = and Debug Capability + 1, 0, ecx, 17, pcid , Process-= context identifiers + 1, 0, ecx, 18, dca , Direct C= ache Access + 1, 0, ecx, 19, sse4_1 , SSE4.1 + 1, 0, ecx, 20, sse4_2 , SSE4.2 + 1, 0, ecx, 21, x2apic , X2APIC s= upport + 1, 0, ecx, 22, movbe , MOVBE in= struction support + 1, 0, ecx, 23, popcnt , POPCNT i= nstruction support + 1, 0, ecx, 24, tsc_deadline_timer , APIC tim= er one-shot operation + 1, 0, ecx, 25, aes , AES inst= ructions + 1, 0, ecx, 26, xsave , XSAVE (a= nd related instructions) support + 1, 0, ecx, 27, osxsave , XSAVE (a= nd related instructions) are enabled by OS + 1, 0, ecx, 28, avx , AVX inst= ructions support + 1, 0, ecx, 29, f16c , Half-pre= cision floating-point conversion support + 1, 0, ecx, 30, rdrand , RDRAND i= nstruction support + 1, 0, ecx, 31, guest_status , System i= s running as guest; (para-)virtualized system + 1, 0, edx, 0, fpu , Floating= -Point Unit on-chip (x87) + 1, 0, edx, 1, vme , Virtual-= 8086 Mode Extensions + 1, 0, edx, 2, de , Debuggin= g Extensions + 1, 0, edx, 3, pse , Page Siz= e Extension + 1, 0, edx, 4, tsc , Time Sta= mp Counter + 1, 0, edx, 5, msr , Model-Sp= ecific Registers (RDMSR and WRMSR support) + 1, 0, edx, 6, pae , Physical= Address Extensions + 1, 0, edx, 7, mce , Machine = Check Exception + 1, 0, edx, 8, cx8 , CMPXCHG8= B instruction + 1, 0, edx, 9, apic , APIC on-= chip + 1, 0, edx, 11, sep , SYSENTER= , SYSEXIT, and associated MSRs + 1, 0, edx, 12, mtrr , Memory T= ype Range Registers + 1, 0, edx, 13, pge , Page Glo= bal Extensions + 1, 0, edx, 14, mca , Machine = Check Architecture + 1, 0, edx, 15, cmov , Conditio= nal Move Instruction + 1, 0, edx, 16, pat , Page Att= ribute Table + 1, 0, edx, 17, pse36 , Page Siz= e Extension (36-bit) + 1, 0, edx, 18, pn , Processo= r Serial Number + 1, 0, edx, 19, clflush , CLFLUSH = instruction + 1, 0, edx, 21, dts , Debug St= ore + 1, 0, edx, 22, acpi , Thermal = monitor and clock control + 1, 0, edx, 23, mmx , MMX inst= ructions + 1, 0, edx, 24, fxsr , FXSAVE a= nd FXRSTOR instructions + 1, 0, edx, 25, sse , SSE inst= ructions + 1, 0, edx, 26, sse2 , SSE2 ins= tructions + 1, 0, edx, 27, ss , Self Sno= op + 1, 0, edx, 28, ht , Hyper-th= reading + 1, 0, edx, 29, tm , Thermal = Monitor + 1, 0, edx, 30, ia64 , Legacy I= A-64 (Itanium) support bit, now resreved + 1, 0, edx, 31, pbe , Pending = Break Enable + +# Leaf 2H +# Intel cache and TLB information one-byte descriptors + + 2, 0, eax, 7:0, iteration_count , Number o= f times this CPUD leaf must be queried + 2, 0, eax, 15:8, desc1 , Descript= or #1 + 2, 0, eax, 23:16, desc2 , Descript= or #2 + 2, 0, eax, 30:24, desc3 , Descript= or #3 + 2, 0, eax, 31, eax_invalid , Descript= ors 1-3 are invalid if set + 2, 0, ebx, 7:0, desc4 , Descript= or #4 + 2, 0, ebx, 15:8, desc5 , Descript= or #5 + 2, 0, ebx, 23:16, desc6 , Descript= or #6 + 2, 0, ebx, 30:24, desc7 , Descript= or #7 + 2, 0, ebx, 31, ebx_invalid , Descript= ors 4-7 are invalid if set + 2, 0, ecx, 7:0, desc8 , Descript= or #8 + 2, 0, ecx, 15:8, desc9 , Descript= or #9 + 2, 0, ecx, 23:16, desc10 , Descript= or #10 + 2, 0, ecx, 30:24, desc11 , Descript= or #11 + 2, 0, ecx, 31, ecx_invalid , Descript= ors 8-11 are invalid if set + 2, 0, edx, 7:0, desc12 , Descript= or #12 + 2, 0, edx, 15:8, desc13 , Descript= or #13 + 2, 0, edx, 23:16, desc14 , Descript= or #14 + 2, 0, edx, 30:24, desc15 , Descript= or #15 + 2, 0, edx, 31, edx_invalid , Descript= ors 12-15 are invalid if set + +# Leaf 4H +# Intel deterministic cache parameters + + 4, 31:0, eax, 4:0, cache_type , Cache ty= pe field + 4, 31:0, eax, 7:5, cache_level , Cache le= vel (1-based) + 4, 31:0, eax, 8, cache_self_init , Self-ini= tialializing cache level + 4, 31:0, eax, 9, fully_associative , Fully-as= sociative cache + 4, 31:0, eax, 25:14, num_threads_sharing , Number l= ogical CPUs sharing this cache + 4, 31:0, eax, 31:26, num_cores_on_die , Number o= f cores in the physical package + 4, 31:0, ebx, 11:0, cache_linesize , System c= oherency line size (0-based) + 4, 31:0, ebx, 21:12, cache_npartitions , Physical= line partitions (0-based) + 4, 31:0, ebx, 31:22, cache_nways , Ways of = associativity (0-based) + 4, 31:0, ecx, 30:0, cache_nsets , Cache nu= mber of sets (0-based) + 4, 31:0, edx, 0, wbinvd_rll_no_guarantee, WBINVD/I= NVD not guaranteed for Remote Lower-Level caches + 4, 31:0, edx, 1, ll_inclusive , Cache is= inclusive of Lower-Level caches + 4, 31:0, edx, 2, complex_indexing , Not a di= rect-mapped cache (complex function) + +# Leaf 5H +# MONITOR/MWAIT instructions enumeration + + 5, 0, eax, 15:0, min_mon_size , Smallest= monitor-line size, in bytes + 5, 0, ebx, 15:0, max_mon_size , Largest = monitor-line size, in bytes + 5, 0, ecx, 0, mwait_ext , Enumerat= ion of MONITOR/MWAIT extensions is supported + 5, 0, ecx, 1, mwait_irq_break , Interrup= ts as a break-event for MWAIT is supported + 5, 0, edx, 3:0, n_c0_substates , Number o= f C0 sub C-states supported using MWAIT + 5, 0, edx, 7:4, n_c1_substates , Number o= f C1 sub C-states supported using MWAIT + 5, 0, edx, 11:8, n_c2_substates , Number o= f C2 sub C-states supported using MWAIT + 5, 0, edx, 15:12, n_c3_substates , Number o= f C3 sub C-states supported using MWAIT + 5, 0, edx, 19:16, n_c4_substates , Number o= f C4 sub C-states supported using MWAIT + 5, 0, edx, 23:20, n_c5_substates , Number o= f C5 sub C-states supported using MWAIT + 5, 0, edx, 27:24, n_c6_substates , Number o= f C6 sub C-states supported using MWAIT + 5, 0, edx, 31:28, n_c7_substates , Number o= f C7 sub C-states supported using MWAIT + +# Leaf 6H +# Thermal and Power Management enumeration + + 6, 0, eax, 0, dtherm , Digital = temprature sensor + 6, 0, eax, 1, turbo_boost , Intel Tu= rbo Boost + 6, 0, eax, 2, arat , Always-R= unning APIC Timer (not affected by p-state) + 6, 0, eax, 4, pln , Power Li= mit Notification (PLN) event + 6, 0, eax, 5, ecmd , Clock mo= dulation duty cycle extension + 6, 0, eax, 6, pts , Package = thermal management + 6, 0, eax, 7, hwp , HWP (Har= dware P-states) base registers are supported + 6, 0, eax, 8, hwp_notify , HWP noti= fication (IA32_HWP_INTERRUPT MSR) + 6, 0, eax, 9, hwp_act_window , HWP acti= vity window (IA32_HWP_REQUEST[bits 41:32]) supported + 6, 0, eax, 10, hwp_epp , HWP Ener= gy Performance Preference + 6, 0, eax, 11, hwp_pkg_req , HWP Pack= age Level Request + 6, 0, eax, 13, hdc_base_regs , HDC base= registers are supported + 6, 0, eax, 14, turbo_boost_3_0 , Intel Tu= rbo Boost Max 3.0 + 6, 0, eax, 15, hwp_capabilities , HWP High= est Performance change + 6, 0, eax, 16, hwp_peci_override , HWP PECI= override + 6, 0, eax, 17, hwp_flexible , Flexible= HWP + 6, 0, eax, 18, hwp_fast , IA32_HWP= _REQUEST MSR fast access mode + 6, 0, eax, 19, hfi , HW_FEEDB= ACK MSRs supported + 6, 0, eax, 20, hwp_ignore_idle , Ignoring= idle logical CPU HWP req is supported + 6, 0, eax, 23, thread_director , Intel th= read director support + 6, 0, eax, 24, therm_interrupt_bit25 , IA32_THE= RM_INTERRUPT MSR bit 25 is supported + 6, 0, ebx, 3:0, n_therm_thresholds , Digital = thermometer thresholds + 6, 0, ecx, 0, aperfmperf , MPERF/AP= ERF MSRs (effective frequency interface) + 6, 0, ecx, 3, epb , IA32_ENE= RGY_PERF_BIAS MSR support + 6, 0, ecx, 15:8, thrd_director_nclasses , Number o= f classes, Intel thread director + 6, 0, edx, 0, perfcap_reporting , Performa= nce capability reporting + 6, 0, edx, 1, encap_reporting , Energy e= fficiency capability reporting + 6, 0, edx, 11:8, feedback_sz , HW feedb= ack interface struct size, in 4K pages + 6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This log= ical CPU index @ HW feedback struct, 0-based + +# Leaf 7H +# Extended CPU features enumeration + + 7, 0, eax, 31:0, leaf7_n_subleaves , Number o= f cpuid 0x7 subleaves + 7, 0, ebx, 0, fsgsbase , FSBASE/G= SBASE read/write support + 7, 0, ebx, 1, tsc_adjust , IA32_TSC= _ADJUST MSR supported + 7, 0, ebx, 2, sgx , Intel SG= X (Software Guard Extensions) + 7, 0, ebx, 3, bmi1 , Bit mani= pulation extensions group 1 + 7, 0, ebx, 4, hle , Hardware= Lock Elision + 7, 0, ebx, 5, avx2 , AVX2 ins= truction set + 7, 0, ebx, 6, fdp_excptn_only , FPU Data= Pointer updated only on x87 exceptions + 7, 0, ebx, 7, smep , Supervis= or Mode Execution Protection + 7, 0, ebx, 8, bmi2 , Bit mani= pulation extensions group 2 + 7, 0, ebx, 9, erms , Enhanced= REP MOVSB/STOSB + 7, 0, ebx, 10, invpcid , INVPCID = instruction (Invalidate Processor Context ID) + 7, 0, ebx, 11, rtm , Intel re= stricted transactional memory + 7, 0, ebx, 12, cqm , Intel RD= T-CMT / AMD Platform-QoS cache monitoring + 7, 0, ebx, 13, zero_fcs_fds , Deprecat= ed FPU CS/DS (stored as zero) + 7, 0, ebx, 14, mpx , Intel me= mory protection extensions + 7, 0, ebx, 15, rdt_a , Intel RD= T / AMD Platform-QoS Enforcemeent + 7, 0, ebx, 16, avx512f , AVX-512 = foundation instructions + 7, 0, ebx, 17, avx512dq , AVX-512 = double/quadword instructions + 7, 0, ebx, 18, rdseed , RDSEED i= nstruction + 7, 0, ebx, 19, adx , ADCX/ADO= X instructions + 7, 0, ebx, 20, smap , Supervis= or mode access prevention + 7, 0, ebx, 21, avx512ifma , AVX-512 = integer fused multiply add + 7, 0, ebx, 23, clflushopt , CLFLUSHO= PT instruction + 7, 0, ebx, 24, clwb , CLWB ins= truction + 7, 0, ebx, 25, intel_pt , Intel pr= ocessor trace + 7, 0, ebx, 26, avx512pf , AVX-512 = prefetch instructions + 7, 0, ebx, 27, avx512er , AVX-512 = exponent/reciprocal instrs + 7, 0, ebx, 28, avx512cd , AVX-512 = conflict detection instrs + 7, 0, ebx, 29, sha_ni , SHA/SHA2= 56 instructions + 7, 0, ebx, 30, avx512bw , AVX-512 = BW (byte/word granular) instructions + 7, 0, ebx, 31, avx512vl , AVX-512 = VL (128/256 vector length) extensions + 7, 0, ecx, 0, prefetchwt1 , PREFETCH= WT1 (Intel Xeon Phi only) + 7, 0, ecx, 1, avx512vbmi , AVX-512 = Vector byte manipulation instrs + 7, 0, ecx, 2, umip , User mod= e instruction protection + 7, 0, ecx, 3, pku , Protecti= on keys for user-space + 7, 0, ecx, 4, ospke , OS prote= ction keys enable + 7, 0, ecx, 5, waitpkg , WAITPKG = instructions + 7, 0, ecx, 6, avx512_vbmi2 , AVX-512 = vector byte manipulation instrs group 2 + 7, 0, ecx, 7, cet_ss , CET shad= ow stack features + 7, 0, ecx, 8, gfni , Galois f= ield new instructions + 7, 0, ecx, 9, vaes , Vector A= ES instrs + 7, 0, ecx, 10, vpclmulqdq , VPCLMULQ= DQ 256-bit instruction support + 7, 0, ecx, 11, avx512_vnni , Vector n= eural network instructions + 7, 0, ecx, 12, avx512_bitalg , AVX-512 = bit count/shiffle + 7, 0, ecx, 13, tme , Intel to= tal memory encryption + 7, 0, ecx, 14, avx512_vpopcntdq , AVX-512:= POPCNT for vectors of DW/QW + 7, 0, ecx, 16, la57 , 57-bit l= inear addreses (five-level paging) + 7, 0, ecx, 21:17, mawau_val_lm , BNDLDX/B= NDSTX MAWAU value in 64-bit mode + 7, 0, ecx, 22, rdpid , RDPID in= struction + 7, 0, ecx, 23, key_locker , Intel ke= y locker support + 7, 0, ecx, 24, bus_lock_detect , OS bus-l= ock detection + 7, 0, ecx, 25, cldemote , CLDEMOTE= instruction + 7, 0, ecx, 27, movdiri , MOVDIRI = instruction + 7, 0, ecx, 28, movdir64b , MOVDIR64= B instruction + 7, 0, ecx, 29, enqcmd , Enqueue = stores supported (ENQCMD{,S}) + 7, 0, ecx, 30, sgx_lc , Intel SG= X launch configuration + 7, 0, ecx, 31, pks , Protecti= on keys for supervisor-mode pages + 7, 0, edx, 1, sgx_keys , Intel SG= X attestation services + 7, 0, edx, 2, avx512_4vnniw , AVX-512 = neural network instructions + 7, 0, edx, 3, avx512_4fmaps , AVX-512 = multiply accumulation single precision + 7, 0, edx, 4, fsrm , Fast sho= rt REP MOV + 7, 0, edx, 5, uintr , CPU supp= orts user interrupts + 7, 0, edx, 8, avx512_vp2intersect , VP2INTER= SECT{D,Q} instructions + 7, 0, edx, 9, srdbs_ctrl , SRBDS mi= tigation MSR available + 7, 0, edx, 10, md_clear , VERW MD_= CLEAR microcode support + 7, 0, edx, 11, rtm_always_abort , XBEGIN (= RTM transaction) always aborts + 7, 0, edx, 13, tsx_force_abort , MSR TSX_= FORCE_ABORT, RTM_ABORT bit, supported + 7, 0, edx, 14, serialize , SERIALIZ= E instruction + 7, 0, edx, 15, hybrid_cpu , The CPU = is identified as a 'hybrid part' + 7, 0, edx, 16, tsxldtrk , TSX susp= end/resume load address tracking + 7, 0, edx, 18, pconfig , PCONFIG = instruction + 7, 0, edx, 19, arch_lbr , Intel ar= chitectural LBRs + 7, 0, edx, 20, ibt , CET indi= rect branch tracking + 7, 0, edx, 22, amx_bf16 , AMX-BF16= : tile bfloat16 support + 7, 0, edx, 23, avx512_fp16 , AVX-512 = FP16 instructions + 7, 0, edx, 24, amx_tile , AMX-TILE= : tile architecture support + 7, 0, edx, 25, amx_int8 , AMX-INT8= : tile 8-bit integer support + 7, 0, edx, 26, spec_ctrl , Speculat= ion Control (IBRS/IBPB: indirect branch restrictions) + 7, 0, edx, 27, intel_stibp , Single t= hread indirect branch predictors + 7, 0, edx, 28, flush_l1d , FLUSH L1= D cache: IA32_FLUSH_CMD MSR + 7, 0, edx, 29, arch_capabilities , Intel IA= 32_ARCH_CAPABILITIES MSR + 7, 0, edx, 30, core_capabilities , IA32_COR= E_CAPABILITIES MSR + 7, 0, edx, 31, spec_ctrl_ssbd , Speculat= ive store bypass disable + 7, 1, eax, 4, avx_vnni , AVX-VNNI= instructions + 7, 1, eax, 5, avx512_bf16 , AVX-512 = bFloat16 instructions + 7, 1, eax, 6, lass , Linear a= ddress space separation + 7, 1, eax, 7, cmpccxadd , CMPccXAD= D instructions + 7, 1, eax, 8, arch_perfmon_ext , ArchPerf= monExt: CPUID leaf 0x23 is supported + 7, 1, eax, 10, fzrm , Fast zer= o-length REP MOVSB + 7, 1, eax, 11, fsrs , Fast sho= rt REP STOSB + 7, 1, eax, 12, fsrc , Fast Sho= rt REP CMPSB/SCASB + 7, 1, eax, 17, fred , FRED: Fl= exible return and event delivery transitions + 7, 1, eax, 18, lkgs , LKGS: Lo= ad 'kernel' (userspace) GS + 7, 1, eax, 19, wrmsrns , WRMSRNS = instr (WRMSR-non-serializing) + 7, 1, eax, 21, amx_fp16 , AMX-FP16= : FP16 tile operations + 7, 1, eax, 22, hreset , History = reset support + 7, 1, eax, 23, avx_ifma , Integer = fused multiply add + 7, 1, eax, 26, lam , Linear a= ddress masking + 7, 1, eax, 27, rd_wr_msrlist , RDMSRLIS= T/WRMSRLIST instructions + 7, 1, ebx, 0, intel_ppin , Protecte= d processor inventory number (PPIN{,_CTL} MSRs) + 7, 1, edx, 4, avx_vnni_int8 , AVX-VNNI= -INT8 instructions + 7, 1, edx, 5, avx_ne_convert , AVX-NE-C= ONVERT instructions + 7, 1, edx, 8, amx_complex , AMX-COMP= LEX instructions (starting from Granite Rapids) + 7, 1, edx, 14, prefetchit_0_1 , PREFETCH= IT0/1 instructions + 7, 1, edx, 18, cet_sss , CET supe= rvisor shadow stacks safe to use + 7, 2, edx, 0, intel_psfd , Intel pr= edictive store forward disable + 7, 2, edx, 1, ipred_ctrl , MSR bits= IA32_SPEC_CTRL.IPRED_DIS_{U,S} + 7, 2, edx, 2, rrsba_ctrl , MSR bits= IA32_SPEC_CTRL.RRSBA_DIS_{U,S} + 7, 2, edx, 3, ddp_ctrl , MSR bit = IA32_SPEC_CTRL.DDPD_U + 7, 2, edx, 4, bhi_ctrl , MSR bit = IA32_SPEC_CTRL.BHI_DIS_S + 7, 2, edx, 5, mcdt_no , MCDT mit= igation not needed + 7, 2, edx, 6, uclock_disable , UC-lock = disable is supported + +# Leaf 9H +# Intel DCA (Direct Cache Access) enumeration + + 9, 0, eax, 0, dca_enabled_in_bios , DCA is e= nabled in BIOS + +# Leaf AH +# Intel PMU (Performance Monitoring Unit) enumeration + + 0xa, 0, eax, 7:0, pmu_version , Performa= nce monitoring unit version ID + 0xa, 0, eax, 15:8, pmu_n_gcounters , Number o= f general PMU counters per logical CPU + 0xa, 0, eax, 23:16, pmu_gcounters_nbits , Bitwidth= of PMU general counters + 0xa, 0, eax, 31:24, pmu_cpuid_ebx_bits , Length o= f cpuid leaf 0xa EBX bit vector + 0xa, 0, ebx, 0, no_core_cycle_evt , Core cyc= le event not available + 0xa, 0, ebx, 1, no_insn_retired_evt , Instruct= ion retired event not available + 0xa, 0, ebx, 2, no_refcycle_evt , Referenc= e cycles event not available + 0xa, 0, ebx, 3, no_llc_ref_evt , LLC-refe= rence event not available + 0xa, 0, ebx, 4, no_llc_miss_evt , LLC-miss= es event not available + 0xa, 0, ebx, 5, no_br_insn_ret_evt , Branch i= nstruction retired event not available + 0xa, 0, ebx, 6, no_br_mispredict_evt , Branch m= ispredict retired event not available + 0xa, 0, ebx, 7, no_td_slots_evt , Topdown = slots event not available + 0xa, 0, ecx, 31:0, pmu_fcounters_bitmap , Fixed-fu= nction PMU counters support bitmap + 0xa, 0, edx, 4:0, pmu_n_fcounters , Number o= f fixed PMU counters + 0xa, 0, edx, 12:5, pmu_fcounters_nbits , Bitwidth= of PMU fixed counters + 0xa, 0, edx, 15, anythread_depr , AnyThrea= d deprecation + +# Leaf BH +# CPUs v1 extended topology enumeration + + 0xb, 1:0, eax, 4:0, x2apic_id_shift , Bit widt= h of this level (previous levels inclusive) + 0xb, 1:0, ebx, 15:0, domain_lcpus_count , Logical = CPUs count across all instances of this domain + 0xb, 1:0, ecx, 7:0, domain_nr , This dom= ain level (subleaf ID) + 0xb, 1:0, ecx, 15:8, domain_type , This dom= ain type + 0xb, 1:0, edx, 31:0, x2apic_id , x2APIC I= D of current logical CPU + +# Leaf DH +# Processor extended state enumeration + + 0xd, 0, eax, 0, xcr0_x87 , XCR0.X87= (bit 0) supported + 0xd, 0, eax, 1, xcr0_sse , XCR0.SEE= (bit 1) supported + 0xd, 0, eax, 2, xcr0_avx , XCR0.AVX= (bit 2) supported + 0xd, 0, eax, 3, xcr0_mpx_bndregs , XCR0.BND= REGS (bit 3) supported (MPX BND0-BND3 regs) + 0xd, 0, eax, 4, xcr0_mpx_bndcsr , XCR0.BND= CSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS regs) + 0xd, 0, eax, 5, xcr0_avx512_opmask , XCR0.OPM= ASK (bit 5) supported (AVX-512 k0-k7 regs) + 0xd, 0, eax, 6, xcr0_avx512_zmm_hi256 , XCR0.ZMM= _Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 regs) + 0xd, 0, eax, 7, xcr0_avx512_hi16_zmm , XCR0.HI1= 6_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 regs) + 0xd, 0, eax, 9, xcr0_pkru , XCR0.PKR= U (bit 9) supported (XSAVE PKRU reg) + 0xd, 0, eax, 11, xcr0_cet_u , AMD XCR0= .CET_U (bit 11) supported (CET supervisor state) + 0xd, 0, eax, 12, xcr0_cet_s , AMD XCR0= .CET_S (bit 12) support (CET user state) + 0xd, 0, eax, 17, xcr0_tileconfig , XCR0.TIL= ECONFIG (bit 17) supported (AMX can manage TILECONFIG) + 0xd, 0, eax, 18, xcr0_tiledata , XCR0.TIL= EDATA (bit 18) supported (AMX can manage TILEDATA) + 0xd, 0, ebx, 31:0, xsave_sz_xcr0_enabled , XSAVE/XR= STR area byte size, for XCR0 enabled features + 0xd, 0, ecx, 31:0, xsave_sz_max , XSAVE/XR= STR area max byte size, all CPU features + 0xd, 0, edx, 30, xcr0_lwp , AMD XCR0= .LWP (bit 62) supported (Light-weight Profiling) + 0xd, 1, eax, 0, xsaveopt , XSAVEOPT= instruction + 0xd, 1, eax, 1, xsavec , XSAVEC i= nstruction + 0xd, 1, eax, 2, xgetbv1 , XGETBV i= nstruction with ECX =3D 1 + 0xd, 1, eax, 3, xsaves , XSAVES/X= RSTORS instructions (and XSS MSR) + 0xd, 1, eax, 4, xfd , Extended= feature disable support + 0xd, 1, ebx, 31:0, xsave_sz_xcr0_xmms_enabled, XSAVE= area size, all XCR0 and XMMS features enabled + 0xd, 1, ecx, 8, xss_pt , PT state= , supported + 0xd, 1, ecx, 10, xss_pasid , PASID st= ate, supported + 0xd, 1, ecx, 11, xss_cet_u , CET user= state, supported + 0xd, 1, ecx, 12, xss_cet_p , CET supe= rvisor state, supported + 0xd, 1, ecx, 13, xss_hdc , HDC stat= e, supported + 0xd, 1, ecx, 14, xss_uintr , UINTR st= ate, supported + 0xd, 1, ecx, 15, xss_lbr , LBR stat= e, supported + 0xd, 1, ecx, 16, xss_hwp , HWP stat= e, supported + 0xd, 63:2, eax, 31:0, xsave_sz , Size of = save area for subleaf-N feature, in bytes + 0xd, 63:2, ebx, 31:0, xsave_offset , Offset o= f save area for subleaf-N feature, in bytes + 0xd, 63:2, ecx, 0, is_xss_bit , Subleaf = N describes an XSS bit, otherwise XCR0 bit + 0xd, 63:2, ecx, 1, compacted_xsave_64byte_aligned, W= hen compacted, subleaf-N feature xsave area is 64-byte aligned + +# Leaf FH +# Intel RDT / AMD PQoS resource monitoring + + 0xf, 0, ebx, 31:0, core_rmid_max , RMID max= , within this core, all types (0-based) + 0xf, 0, edx, 1, cqm_llc , LLC QoS-= monitoring supported + 0xf, 1, eax, 7:0, l3c_qm_bitwidth , L3 QoS-m= onitoring counter bitwidth (24-based) + 0xf, 1, eax, 8, l3c_qm_overflow_bit , QM_CTR M= SR bit 61 is an overflow bit + 0xf, 1, ebx, 31:0, l3c_qm_conver_factor , QM_CTR M= SR conversion factor to bytes + 0xf, 1, ecx, 31:0, l3c_qm_rmid_max , L3 QoS-m= onitoring max RMID + 0xf, 1, edx, 0, cqm_occup_llc , L3 QoS o= ccupancy monitoring supported + 0xf, 1, edx, 1, cqm_mbm_total , L3 QoS t= otal bandwidth monitoring supported + 0xf, 1, edx, 2, cqm_mbm_local , L3 QoS l= ocal bandwidth monitoring supported =20 # Leaf 10H -# Intel RDT Allocation - - 0x10, 0, EBX, 1, l3c_rdt_alloc, L3 Cache Allocation support= ed - 0x10, 0, EBX, 2, l2c_rdt_alloc, L2 Cache Allocation support= ed - 0x10, 0, EBX, 3, mem_bw_alloc, Memory Bandwidth Allocation = supported - +# Intel RDT / AMD PQoS allocation enumeration + + 0x10, 0, ebx, 1, cat_l3 , L3 Cache= Allocation Technology supported + 0x10, 0, ebx, 2, cat_l2 , L2 Cache= Allocation Technology supported + 0x10, 0, ebx, 3, mba , Memory B= andwidth Allocation supported + 0x10, 2:1, eax, 4:0, cat_cbm_len , L3/L2_CA= T capacity bitmask length, minus-one notation + 0x10, 2:1, ebx, 31:0, cat_units_bitmap , L3/L2_CA= T bitmap of allocation units + 0x10, 2:1, ecx, 1, l3_cat_cos_infreq_updates, L3_CAT= COS updates should be infrequent + 0x10, 2:1, ecx, 2, cdp_l3 , L3/L2_CA= T CDP (Code and Data Prioritization) + 0x10, 2:1, ecx, 3, cat_sparse_1s , L3/L2_CA= T non-contiguous 1s value supported + 0x10, 2:1, edx, 15:0, cat_cos_max , L3/L2_CA= T max COS (Class of Service) supported + 0x10, 3, eax, 11:0, mba_max_delay , Max MBA = throttling value; minus-one notation + 0x10, 3, ecx, 0, per_thread_mba , Per-thre= ad MBA controls are supported + 0x10, 3, ecx, 2, mba_delay_linear , Delay va= lues are linear + 0x10, 3, edx, 15:0, mba_cos_max , MBA max = Class of Service supported =20 # Leaf 12H -# SGX Capability -# -# Some detailed SGX features not added yet - - 0x12, 0, EAX, 0, sgx1, L3 Cache Allocation supported - 0x12, 1, EAX, 0, sgx2, L3 Cache Allocation supported - +# Intel Software Guard Extensions (SGX) enumeration + + 0x12, 0, eax, 0, sgx1 , SGX1 lea= f functions supported + 0x12, 0, eax, 1, sgx2 , SGX2 lea= f functions supported + 0x12, 0, eax, 5, enclv_leaves , ENCLV le= aves (E{INC,DEC}VIRTCHILD, ESETCONTEXT) supported + 0x12, 0, eax, 6, encls_leaves , ENCLS le= aves (ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC) supported + 0x12, 0, eax, 7, enclu_everifyreport2 , ENCLU le= af EVERIFYREPORT2 supported + 0x12, 0, eax, 10, encls_eupdatesvn , ENCLS le= af EUPDATESVN supported + 0x12, 0, eax, 11, sgx_edeccssa , ENCLU le= af EDECCSSA supported + 0x12, 0, ebx, 0, miscselect_exinfo , SSA.MISC= frame: reporting #PF and #GP exceptions inside enclave supported + 0x12, 0, ebx, 1, miscselect_cpinfo , SSA.MISC= frame: reporting #CP exceptions inside enclave supported + 0x12, 0, edx, 7:0, max_enclave_sz_not64 , Maximum = enclave size in non-64-bit mode (log2) + 0x12, 0, edx, 15:8, max_enclave_sz_64 , Maximum = enclave size in 64-bit mode (log2) + 0x12, 1, eax, 0, secs_attr_init , ATTRIBUT= ES.INIT supported (enclave initialized by EINIT) + 0x12, 1, eax, 1, secs_attr_debug , ATTRIBUT= ES.DEBUG supported (enclave permits debugger read/write) + 0x12, 1, eax, 2, secs_attr_mode64bit , ATTRIBUT= ES.MODE64BIT supported (enclave runs in 64-bit mode) + 0x12, 1, eax, 4, secs_attr_provisionkey , ATTRIBUT= ES.PROVISIONKEY supported (provisioning key available) + 0x12, 1, eax, 5, secs_attr_einittoken_key, ATTRIBU= TES.EINITTOKEN_KEY supported (EINIT token key available) + 0x12, 1, eax, 6, secs_attr_cet , ATTRIBUT= ES.CET supported (enable CET attributes) + 0x12, 1, eax, 7, secs_attr_kss , ATTRIBUT= ES.KSS supported (Key Separation and Sharing enabled) + 0x12, 1, eax, 10, secs_attr_aexnotify , ATTRIBUT= ES.AEXNOTIFY supported (enclave threads may get AEX notifications + 0x12, 1, ecx, 0, xfrm_x87 , Enclave = XFRM.X87 (bit 0) supported + 0x12, 1, ecx, 1, xfrm_sse , Enclave = XFRM.SEE (bit 1) supported + 0x12, 1, ecx, 2, xfrm_avx , Enclave = XFRM.AVX (bit 2) supported + 0x12, 1, ecx, 3, xfrm_mpx_bndregs , Enclave = XFRM.BNDREGS (bit 3) supported (MPX BND0-BND3 regs) + 0x12, 1, ecx, 4, xfrm_mpx_bndcsr , Enclave = XFRM.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS regs) + 0x12, 1, ecx, 5, xfrm_avx512_opmask , Enclave = XFRM.OPMASK (bit 5) supported (AVX-512 k0-k7 regs) + 0x12, 1, ecx, 6, xfrm_avx512_zmm_hi256 , Enclave = XFRM.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 regs) + 0x12, 1, ecx, 7, xfrm_avx512_hi16_zmm , Enclave = XFRM.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 regs) + 0x12, 1, ecx, 9, xfrm_pkru , Enclave = XFRM.PKRU (bit 9) supported (XSAVE PKRU reg) + 0x12, 1, ecx, 17, xfrm_tileconfig , Enclave = XFRM.TILECONFIG (bit 17) supported (AMX can manage TILECONFIG) + 0x12, 1, ecx, 18, xfrm_tiledata , Enclave = XFRM.TILEDATA (bit 18) supported (AMX can manage TILEDATA) + 0x12, 31:2, eax, 3:0, subleaf_type , Subleaf = type (dictates output layout) + 0x12, 31:2, eax, 31:12, epc_sec_base_addr_0 , EPC sect= ion base addr, bits[12:31] + 0x12, 31:2, ebx, 19:0, epc_sec_base_addr_1 , EPC sect= ion base addr, bits[32:51] + 0x12, 31:2, ecx, 3:0, epc_sec_type , EPC sect= ion type / property encoding + 0x12, 31:2, ecx, 31:12, epc_sec_size_0 , EPC sect= ion size, bits[12:31] + 0x12, 31:2, edx, 19:0, epc_sec_size_1 , EPC sect= ion size, bits[32:51] =20 # Leaf 14H -# Intel Processor Tracer -# +# Intel Processor Trace enumeration + + 0x14, 0, eax, 31:0, pt_max_subleaf , Max cpui= d 0x14 subleaf + 0x14, 0, ebx, 0, cr3_filtering , IA32_RTI= T_CR3_MATCH is accessible + 0x14, 0, ebx, 1, psb_cyc , Configur= able PSB and cycle-accurate mode + 0x14, 0, ebx, 2, ip_filtering , IP/Trace= Stop filtering; Warm-reset PT MSRs preservation + 0x14, 0, ebx, 3, mtc_timing , MTC timi= ng packet; COFI-based packets suppression + 0x14, 0, ebx, 4, ptwrite , PTWRITE = support + 0x14, 0, ebx, 5, power_event_trace , Power Ev= ent Trace support + 0x14, 0, ebx, 6, psb_pmi_preserve , PSB and = PMI preservation support + 0x14, 0, ebx, 7, event_trace , Event Tr= ace packet generation through IA32_RTIT_CTL.EventEn + 0x14, 0, ebx, 8, tnt_disable , TNT pack= et generation disable through IA32_RTIT_CTL.DisTNT + 0x14, 0, ecx, 0, topa_output , ToPA out= put scheme support + 0x14, 0, ecx, 1, topa_multiple_entries , ToPA tab= les can hold multiple entries + 0x14, 0, ecx, 2, single_range_output , Single-r= ange output scheme supported + 0x14, 0, ecx, 3, trance_transport_output, Trace Tr= ansport subsystem output support + 0x14, 0, ecx, 31, ip_payloads_lip , IP paylo= ads have LIP values (CS base included) + 0x14, 1, eax, 2:0, num_address_ranges , Filterin= g number of configurable Address Ranges + 0x14, 1, eax, 31:16, mtc_periods_bmp , Bitmap o= f supported MTC period encodings + 0x14, 1, ebx, 15:0, cycle_thresholds_bmp , Bitmap o= f supported Cycle Threshold encodings + 0x14, 1, ebx, 31:16, psb_periods_bmp , Bitmap o= f supported Configurable PSB frequency encodings =20 # Leaf 15H -# Time Stamp Counter and Nominal Core Crystal Clock Information +# Intel TSC (Time Stamp Counter) enumeration =20 - 0x15, 0, EAX, 31:0, tsc_denominator, The denominator of the TS= C/=E2=80=9Dcore crystal clock=E2=80=9D ratio - 0x15, 0, EBX, 31:0, tsc_numerator, The numerator of the TSC/= =E2=80=9Dcore crystal clock=E2=80=9D ratio - 0x15, 0, ECX, 31:0, nom_freq, Nominal frequency of the core cr= ystal clock in Hz + 0x15, 0, eax, 31:0, tsc_denominator , Denomina= tor of the TSC/'core crystal clock' ratio + 0x15, 0, ebx, 31:0, tsc_numerator , Numerato= r of the TSC/'core crystal clock' ratio + 0x15, 0, ecx, 31:0, cpu_crystal_hz , Core cry= stal clock nominal frequency, in Hz =20 # Leaf 16H -# Processor Frequency Information +# Intel processor fequency enumeration =20 - 0x16, 0, EAX, 15:0, cpu_base_freq, Processor Base Frequency in= MHz - 0x16, 0, EBX, 15:0, cpu_max_freq, Maximum Frequency in MHz - 0x16, 0, ECX, 15:0, bus_freq, Bus (Reference) Frequency in MHz + 0x16, 0, eax, 15:0, cpu_base_mhz , Processo= r base frequency, in MHz + 0x16, 0, ebx, 15:0, cpu_max_mhz , Processo= r max frequency, in MHz + 0x16, 0, ecx, 15:0, bus_mhz , Bus refe= rence frequency, in MHz =20 # Leaf 17H -# System-On-Chip Vendor Attribute - - 0x17, 0, EAX, 31:0, max_socid, Maximum input value of supporte= d sub-leaf - 0x17, 0, EBX, 15:0, soc_vid, SOC Vendor ID - 0x17, 0, EBX, 16, std_vid, SOC Vendor ID is assigned via an = industry standard scheme - 0x17, 0, ECX, 31:0, soc_pid, SOC Project ID assigned by vendor - 0x17, 0, EDX, 31:0, soc_sid, SOC Stepping ID +# Intel SoC vendor attributes enumeration + + 0x17, 0, eax, 31:0, soc_max_subleaf , Max cpui= d leaf 0x17 subleaf + 0x17, 0, ebx, 15:0, soc_vendor_id , SoC vend= or ID + 0x17, 0, ebx, 16, is_vendor_scheme , Assigned= by industry enumaeratoion scheme (not Intel) + 0x17, 0, ecx, 31:0, soc_proj_id , SoC proj= ect ID, assigned by vendor + 0x17, 0, edx, 31:0, soc_stepping_id , Soc proj= ect stepping ID, assigned by vendor + 0x17, 3:1, eax, 31:0, vendor_brand_a , Vendor B= rand ID string, bytes subleaf_nr * (0 -> 3) + 0x17, 3:1, ebx, 31:0, vendor_brand_b , Vendor B= rand ID string, bytes subleaf_nr * (4 -> 7) + 0x17, 3:1, ecx, 31:0, vendor_brand_c , Vendor B= rand ID string, bytes subleaf_nr * (8 -> 11) + 0x17, 3:1, edx, 31:0, vendor_brand_d , Vendor B= rand ID string, bytes subleaf_nr * (12 -> 15) =20 # Leaf 18H -# Deterministic Address Translation Parameters - +# Intel determenestic address translation (TLB) parameters + + 0x18, 31:0, eax, 31:0, tlb_max_subleaf , Max cpui= d 0x18 subleaf + 0x18, 31:0, ebx, 0, tlb_4k_page , TLB 4KB-= page entries supported + 0x18, 31:0, ebx, 1, tlb_2m_page , TLB 2MB-= page entries supported + 0x18, 31:0, ebx, 2, tlb_4m_page , TLB 4MB-= page entries supported + 0x18, 31:0, ebx, 3, tlb_1g_page , TLB 1GB-= page entries supported + 0x18, 31:0, ebx, 10:8, hard_partitioning , (Hard/So= ft) partitioning between logical CPUs sharing this struct + 0x18, 31:0, ebx, 31:16, n_way_associative , Ways of = associativity + 0x18, 31:0, ecx, 31:0, n_sets , Number o= f sets + 0x18, 31:0, edx, 4:0, tlb_type , Translat= ion cache type (TLB type) + 0x18, 31:0, edx, 7:5, tlb_cache_level , Translat= ion cache level (1-based) + 0x18, 31:0, edx, 8, is_fully_associative , Fully-as= sociative structure + 0x18, 31:0, edx, 25:14, tlb_max_addressible_ids, Max num = of addressible IDs for logical CPUs sharing this TLB - 1 =20 # Leaf 19H -# Key Locker Leaf +# Intel Key Locker enumeration =20 + 0x19, 0, eax, 0, kl_cpl0_only , CPL0-onl= y key Locker restriction supported + 0x19, 0, eax, 1, kl_no_encrypt , No-encry= pt key locker restriction supported + 0x19, 0, eax, 2, kl_no_decrypt , No-decry= pt key locker restriction supported + 0x19, 0, ebx, 0, aes_keylocker , AES key = locker instructions supported + 0x19, 0, ebx, 2, aes_keylocker_wide , AES wide= key locker instructions supported + 0x19, 0, ebx, 4, kl_msr_iwkey , Key lock= er MSRs and IWKEY backups supported + 0x19, 0, ecx, 0, loadiwkey_no_backup , LOADIWKE= Y NoBackup parameter supported + 0x19, 0, ecx, 1, iwkey_rand , IWKEY ra= ndomization (KeySource encoding 1) supported =20 # Leaf 1AH -# Hybrid Information - - 0x1A, 0, EAX, 31:24, core_type, 20H-Intel_Atom 40H-Intel_Core - +# Intel hybrid CPUs identification (e.g. Atom, Core) + + 0x1a, 0, eax, 23:0, core_native_model , This cor= e's native model ID + 0x1a, 0, eax, 31:24, core_type , This cor= e's type + +# Leaf 1BH +# Intel PCONFIG (Platform configuration) enumeration + + 0x1b, 31:0, eax, 11:0, pconfig_subleaf_type , CPUID 0x= 1b subleaf type + 0x1b, 31:0, ebx, 31:0, pconfig_target_id_x , A suppor= ted PCONFIG target ID + 0x1b, 31:0, ecx, 31:0, pconfig_target_id_y , A suppor= ted PCONFIG target ID + 0x1b, 31:0, edx, 31:0, pconfig_target_id_z , A suppor= ted PCONFIG target ID + +# Leaf 1CH +# Intel LBR (Last Branch Record) enumeration + + 0x1c, 0, eax, 0, lbr_depth_8 , Max stac= k depth (number of LBR entries) =3D 8 + 0x1c, 0, eax, 1, lbr_depth_16 , Max stac= k depth (number of LBR entries) =3D 16 + 0x1c, 0, eax, 2, lbr_depth_24 , Max stac= k depth (number of LBR entries) =3D 24 + 0x1c, 0, eax, 3, lbr_depth_32 , Max stac= k depth (number of LBR entries) =3D 32 + 0x1c, 0, eax, 4, lbr_depth_40 , Max stac= k depth (number of LBR entries) =3D 40 + 0x1c, 0, eax, 5, lbr_depth_48 , Max stac= k depth (number of LBR entries) =3D 48 + 0x1c, 0, eax, 6, lbr_depth_56 , Max stac= k depth (number of LBR entries) =3D 56 + 0x1c, 0, eax, 7, lbr_depth_64 , Max stac= k depth (number of LBR entries) =3D 64 + 0x1c, 0, eax, 30, lbr_deep_c_reset , LBRs may= be cleared on MWAIT C-state > C1 + 0x1c, 0, eax, 31, lbr_ip_is_lip , LBR IP c= ontain Last IP, otherwise effective IP + 0x1c, 0, ebx, 0, lbr_cpl , CPL filt= ering (non-zero IA32_LBR_CTL[2:1]) supported + 0x1c, 0, ebx, 1, lbr_branch_filter , Branch f= iltering (non-zero IA32_LBR_CTL[22:16]) supported + 0x1c, 0, ebx, 2, lbr_call_stack , Call-sta= ck mode (IA32_LBR_CTL[3] =3D 1) supported + 0x1c, 0, ecx, 0, lbr_mispredict , Branch m= isprediction bit supported (IA32_LBR_x_INFO[63]) + 0x1c, 0, ecx, 1, lbr_timed_lbr , Timed LB= Rs (CPU cycles since last LBR entry) supported + 0x1c, 0, ecx, 2, lbr_branch_type , Branch t= ype field (IA32_LBR_INFO_x[59:56]) supported + 0x1c, 0, ecx, 19:16, lbr_events_gpc_bmp , LBR PMU-= events logging support; bitmap for first 4 GP (general-purpose) Counters + +# Leaf 1DH +# Intel AMX (Advanced Matrix Extensions) tile information + + 0x1d, 0, eax, 31:0, amx_max_palette , Highest = palette ID / subleaf ID + 0x1d, 1, eax, 15:0, amx_palette_size , AMX pale= tte total tiles size, in bytes + 0x1d, 1, eax, 31:16, amx_tile_size , AMX sing= le tile's size, in bytes + 0x1d, 1, ebx, 15:0, amx_tile_row_size , AMX tile= single row's size, in bytes + 0x1d, 1, ebx, 31:16, amx_palette_nr_tiles , AMX pale= tte number of tiles + 0x1d, 1, ecx, 15:0, amx_tile_nr_rows , AMX tile= max number of rows + +# Leaf 1EH +# Intel AMX, TMUL (Tile-matrix MULtiply) accelerator unit enumeration + + 0x1e, 0, ebx, 7:0, tmul_maxk , TMUL uni= t maximum height, K (rows or columns) + 0x1e, 0, ebx, 23:8, tmul_maxn , TMUL uni= t maxiumum SIMD dimension, N (column bytes) =20 # Leaf 1FH -# V2 Extended Topology - A preferred superset to leaf 0BH - - -# According to SDM -# 40000000H - 4FFFFFFFH is invalid range +# Intel extended topology enumeration v2 + + 0x1f, 5:0, eax, 4:0, x2apic_id_shift , Bit widt= h of this level (previous levels inclusive) + 0x1f, 5:0, ebx, 15:0, domain_lcpus_count , Logical = CPUs count across all instances of this domain + 0x1f, 5:0, ecx, 7:0, domain_level , This dom= ain level (subleaf ID) + 0x1f, 5:0, ecx, 15:8, domain_type , This dom= ain type + 0x1f, 5:0, edx, 31:0, x2apic_id , x2APIC I= D of current logical CPU + +# Leaf 20H +# Intel HRESET (History Reset) enumeration + + 0x20, 0, eax, 31:0, hreset_nr_subleaves , CPUID 0x= 20 max subleaf + 1 + 0x20, 0, ebx, 0, hreset_thread_director , HRESET o= f Intel thread director is supported + +# Leaf 21H +# Intel TD (Trust Domain) guest execution environment enumeration + + 0x21, 0, ebx, 31:0, tdx_vendorid_0 , TDX vend= or ID string bytes 0 - 3 + 0x21, 0, ecx, 31:0, tdx_vendorid_2 , CPU vend= or ID string bytes 8 - 11 + 0x21, 0, edx, 31:0, tdx_vendorid_1 , CPU vend= or ID string bytes 4 - 7 + +# Leaf 23H +# Intel Architectural Performance Monitoring Extended (ArchPerfmonExt) + + 0x23, 0, eax, 1, subleaf_1_counters , Subleaf = 1, PMU counters bitmaps, is valid + 0x23, 0, eax, 3, subleaf_3_events , Subleaf = 3, PMU events bitmaps, is valid + 0x23, 0, ebx, 0, unitmask2 , IA32_PER= FEVTSELx MSRs UnitMask2 is supported + 0x23, 0, ebx, 1, zbit , IA32_PER= FEVTSELx MSRs Z-bit is supported + 0x23, 1, eax, 31:0, pmu_gp_counters_bitmap , General-= purpose PMU counters bitmap + 0x23, 1, ebx, 31:0, pmu_f_counters_bitmap , Fixed PM= U counters bitmap + 0x23, 3, eax, 0, core_cycles_evt , Core cyc= les event supported + 0x23, 3, eax, 1, insn_retired_evt , Instruct= ions retired event supported + 0x23, 3, eax, 2, ref_cycles_evt , Referenc= e cycles event supported + 0x23, 3, eax, 3, llc_refs_evt , Last-lev= el cache references event supported + 0x23, 3, eax, 4, llc_misses_evt , Last-lev= el cache misses event supported + 0x23, 3, eax, 5, br_insn_ret_evt , Branch i= nstruction retired event supported + 0x23, 3, eax, 6, br_mispr_evt , Branch m= ispredict retired event supported + 0x23, 3, eax, 7, td_slots_evt , Topdown = slots event supported + 0x23, 3, eax, 8, td_backend_bound_evt , Topdown = backend bound event supported + 0x23, 3, eax, 9, td_bad_spec_evt , Topdown = bad speculation event supported + 0x23, 3, eax, 10, td_frontend_bound_evt , Topdown = frontend bound event supported + 0x23, 3, eax, 11, td_retiring_evt , Topdown = retiring event support + +# Leaf 40000000H +# Maximum hypervisor standard leaf + hypervisor vendor string + +0x40000000, 0, eax, 31:0, max_hyp_leaf , Maximum = hypervisor standard leaf number +0x40000000, 0, ebx, 31:0, hypervisor_id_0 , Hypervis= or ID string bytes 0 - 3 +0x40000000, 0, ecx, 31:0, hypervisor_id_1 , Hypervis= or ID string bytes 4 - 7 +0x40000000, 0, edx, 31:0, hypervisor_id_2 , Hypervis= or ID string bytes 8 - 11 + +# Leaf 80000000H +# Maximum extended leaf number + CPU vendor string (AMD) + +0x80000000, 0, eax, 31:0, max_ext_leaf , Maximum = extended cpuid leaf supported +0x80000000, 0, ebx, 31:0, cpu_vendorid_0 , Vendor I= D string bytes 0 - 3 +0x80000000, 0, ecx, 31:0, cpu_vendorid_2 , Vendor I= D string bytes 8 - 11 +0x80000000, 0, edx, 31:0, cpu_vendorid_1 , Vendor I= D string bytes 4 - 7 =20 # Leaf 80000001H -# Extended Processor Signature and Feature Bits - -0x80000001, 0, EAX, 27:20, extfamily, Extended family -0x80000001, 0, EAX, 19:16, extmodel, Extended model -0x80000001, 0, EAX, 11:8, basefamily, Description of Family -0x80000001, 0, EAX, 11:8, basemodel, Model numbers vary with product -0x80000001, 0, EAX, 3:0, stepping, Processor stepping (revision) fo= r a specific model - -0x80000001, 0, EBX, 31:28, pkgtype, Specifies the package type - -0x80000001, 0, ECX, 0, lahf_lm, LAHF/SAHF available in 64-bit mode -0x80000001, 0, ECX, 1, cmplegacy, Core multi-processing legacy mo= de -0x80000001, 0, ECX, 2, svm, Indicates support for: VMRUN, VMLOAD,= VMSAVE, CLGI, VMMCALL, and INVLPGA -0x80000001, 0, ECX, 3, extapicspace, Extended APIC register space -0x80000001, 0, ECX, 4, altmovecr8, Indicates support for LOCK MOV= CR0 means MOV CR8 -0x80000001, 0, ECX, 5, lzcnt, LZCNT -0x80000001, 0, ECX, 6, sse4a, EXTRQ, INSERTQ, MOVNTSS, and MOVNTS= D instruction support -0x80000001, 0, ECX, 7, misalignsse, Misaligned SSE Mode -0x80000001, 0, ECX, 8, prefetchw, PREFETCHW -0x80000001, 0, ECX, 9, osvw, OS Visible Work-around support -0x80000001, 0, ECX, 10, ibs, Instruction Based Sampling -0x80000001, 0, ECX, 11, xop, Extended operation support -0x80000001, 0, ECX, 12, skinit, SKINIT and STGI support -0x80000001, 0, ECX, 13, wdt, Watchdog timer support -0x80000001, 0, ECX, 15, lwp, Lightweight profiling support -0x80000001, 0, ECX, 16, fma4, Four-operand FMA instruction support -0x80000001, 0, ECX, 17, tce, Translation cache extension -0x80000001, 0, ECX, 22, TopologyExtensions, Indicates support for = Core::X86::Cpuid::CachePropEax0 and Core::X86::Cpuid::ExtApicId -0x80000001, 0, ECX, 23, perfctrextcore, Indicates support for Core= ::X86::Msr::PERF_CTL0 - 5 and Core::X86::Msr::PERF_CTR -0x80000001, 0, ECX, 24, perfctrextdf, Indicates support for Core::= X86::Msr::DF_PERF_CTL and Core::X86::Msr::DF_PERF_CTR -0x80000001, 0, ECX, 26, databreakpointextension, Indicates data br= eakpoint support for Core::X86::Msr::DR0_ADDR_MASK, Core::X86::Msr::DR1_ADD= R_MASK, Core::X86::Msr::DR2_ADDR_MASK and Core::X86::Msr::DR3_ADDR_MASK -0x80000001, 0, ECX, 27, perftsc, Performance time-stamp counter su= pported -0x80000001, 0, ECX, 28, perfctrextllc, Indicates support for L3 pe= rformance counter extensions -0x80000001, 0, ECX, 29, mwaitextended, MWAITX and MONITORX capabil= ity is supported -0x80000001, 0, ECX, 30, admskextn, Indicates support for address m= ask extension (to 32 bits and to all 4 DRs) for instruction breakpoints - -0x80000001, 0, EDX, 0, fpu, x87 floating point unit on-chip -0x80000001, 0, EDX, 1, vme, Virtual-mode enhancements -0x80000001, 0, EDX, 2, de, Debugging extensions, IO breakpoints, = CR4.DE -0x80000001, 0, EDX, 3, pse, Page-size extensions (4 MB pages) -0x80000001, 0, EDX, 4, tsc, Time stamp counter, RDTSC/RDTSCP inst= ructions, CR4.TSD -0x80000001, 0, EDX, 5, msr, Model-specific registers (MSRs), with= RDMSR and WRMSR instructions -0x80000001, 0, EDX, 6, pae, Physical-address extensions (PAE) -0x80000001, 0, EDX, 7, mce, Machine Check Exception, CR4.MCE -0x80000001, 0, EDX, 8, cmpxchg8b, CMPXCHG8B instruction -0x80000001, 0, EDX, 9, apic, advanced programmable interrupt cont= roller (APIC) exists and is enabled -0x80000001, 0, EDX, 11, sysret, SYSCALL/SYSRET supported -0x80000001, 0, EDX, 12, mtrr, Memory-type range registers -0x80000001, 0, EDX, 13, pge, Page global extension, CR4.PGE -0x80000001, 0, EDX, 14, mca, Machine check architecture, MCG_CAP -0x80000001, 0, EDX, 15, cmov, Conditional move instructions, CMOV,= FCOMI, FCMOV -0x80000001, 0, EDX, 16, pat, Page attribute table -0x80000001, 0, EDX, 17, pse36, Page-size extensions -0x80000001, 0, EDX, 20, exec_dis, Execute Disable Bit available -0x80000001, 0, EDX, 22, mmxext, AMD extensions to MMX instructions -0x80000001, 0, EDX, 23, mmx, MMX instructions -0x80000001, 0, EDX, 24, fxsr, FXSAVE and FXRSTOR instructions -0x80000001, 0, EDX, 25, ffxsr, FXSAVE and FXRSTOR instruction opti= mizations -0x80000001, 0, EDX, 26, 1gb_page, 1GB page supported -0x80000001, 0, EDX, 27, rdtscp, RDTSCP and IA32_TSC_AUX are availa= ble -0x80000001, 0, EDX, 29, lm, 64b Architecture supported -0x80000001, 0, EDX, 30, threednowext, AMD extensions to 3DNow! ins= tructions -0x80000001, 0, EDX, 31, threednow, 3DNow! instructions - -# Leaf 80000002H/80000003H/80000004H -# Processor Brand String +# Extended CPU feature identifiers + +0x80000001, 0, eax, 3:0, e_stepping_id , Stepping= ID +0x80000001, 0, eax, 7:4, e_base_model , Base pro= cessor model +0x80000001, 0, eax, 11:8, e_base_family , Base pro= cessor family +0x80000001, 0, eax, 19:16, e_ext_model , Extended= processor model +0x80000001, 0, eax, 27:20, e_ext_family , Extended= processor family +0x80000001, 0, ebx, 15:0, brand_id , Brand ID +0x80000001, 0, ebx, 31:28, pkg_type , Package = type +0x80000001, 0, ecx, 0, lahf_lm , LAHF and= SAHF in 64-bit mode +0x80000001, 0, ecx, 1, cmp_legacy , Multi-pr= ocessing legacy mode (No HT) +0x80000001, 0, ecx, 2, svm , Secure V= irtual Machine +0x80000001, 0, ecx, 3, extapic , Extended= APIC space +0x80000001, 0, ecx, 4, cr8_legacy , LOCK MOV= CR0 means MOV CR8 +0x80000001, 0, ecx, 5, abm , LZCNT ad= vanced bit manipulation +0x80000001, 0, ecx, 6, sse4a , SSE4A su= pport +0x80000001, 0, ecx, 7, misalignsse , Misalign= ed SSE mode +0x80000001, 0, ecx, 8, 3dnowprefetch , 3DNow PR= EFETCH/PREFETCHW support +0x80000001, 0, ecx, 9, osvw , OS visib= le workaround +0x80000001, 0, ecx, 10, ibs , Instruct= ion based sampling +0x80000001, 0, ecx, 11, xop , XOP: ext= ended operation (AVX instructions) +0x80000001, 0, ecx, 12, skinit , SKINIT/S= TGI support +0x80000001, 0, ecx, 13, wdt , Watchdog= timer support +0x80000001, 0, ecx, 15, lwp , Lightwei= ght profiling +0x80000001, 0, ecx, 16, fma4 , 4-operan= d FMA instruction +0x80000001, 0, ecx, 17, tce , Translat= ion cache extension +0x80000001, 0, ecx, 19, nodeid_msr , NodeId M= SR (0xc001100c) +0x80000001, 0, ecx, 21, tbm , Trailing= bit manipulations +0x80000001, 0, ecx, 22, topoext , Topology= Extensions (cpuid leaf 0x8000001d) +0x80000001, 0, ecx, 23, perfctr_core , Core per= formance counter extensions +0x80000001, 0, ecx, 24, perfctr_nb , NB/DF pe= rformance counter extensions +0x80000001, 0, ecx, 26, bpext , Data acc= ess breakpoint extension +0x80000001, 0, ecx, 27, ptsc , Performa= nce time-stamp counter +0x80000001, 0, ecx, 28, perfctr_llc , LLC (L3)= performance counter extensions +0x80000001, 0, ecx, 29, mwaitx , MWAITX/M= ONITORX support +0x80000001, 0, ecx, 30, addr_mask_ext , Breakpoi= nt address mask extension (to bit 31) +0x80000001, 0, edx, 0, e_fpu , Floating= -Point Unit on-chip (x87) +0x80000001, 0, edx, 1, e_vme , Virtual-= 8086 Mode Extensions +0x80000001, 0, edx, 2, e_de , Debuggin= g Extensions +0x80000001, 0, edx, 3, e_pse , Page Siz= e Extension +0x80000001, 0, edx, 4, e_tsc , Time Sta= mp Counter +0x80000001, 0, edx, 5, e_msr , Model-Sp= ecific Registers (RDMSR and WRMSR support) +0x80000001, 0, edx, 6, pae , Physical= Address Extensions +0x80000001, 0, edx, 7, mce , Machine = Check Exception +0x80000001, 0, edx, 8, cx8 , CMPXCHG8= B instruction +0x80000001, 0, edx, 9, apic , APIC on-= chip +0x80000001, 0, edx, 11, syscall , SYSCALL = and SYSRET instructions +0x80000001, 0, edx, 12, mtrr , Memory T= ype Range Registers +0x80000001, 0, edx, 13, pge , Page Glo= bal Extensions +0x80000001, 0, edx, 14, mca , Machine = Check Architecture +0x80000001, 0, edx, 15, cmov , Conditio= nal Move Instruction +0x80000001, 0, edx, 16, pat , Page Att= ribute Table +0x80000001, 0, edx, 17, pse36 , Page Siz= e Extension (36-bit) +0x80000001, 0, edx, 19, mp , Out-of-s= pec AMD Multiprocessing bit +0x80000001, 0, edx, 20, nx , No-execu= te page protection +0x80000001, 0, edx, 22, mmxext , AMD MMX = extensions +0x80000001, 0, edx, 24, e_fxsr , FXSAVE a= nd FXRSTOR instructions +0x80000001, 0, edx, 25, fxsr_opt , FXSAVE a= nd FXRSTOR optimizations +0x80000001, 0, edx, 26, pdpe1gb , 1-GB lar= ge page support +0x80000001, 0, edx, 27, rdtscp , RDTSCP i= nstruction +0x80000001, 0, edx, 29, lm , Long mod= e (x86-64, 64-bit support) +0x80000001, 0, edx, 30, 3dnowext , AMD 3DNo= w extensions +0x80000001, 0, edx, 31, 3dnow , 3DNow in= structions + +# Leaf 80000002H +# CPU brand ID string, bytes 0 - 15 + +0x80000002, 0, eax, 31:0, cpu_brandid_0 , CPU bran= d ID string, bytes 0 - 3 +0x80000002, 0, ebx, 31:0, cpu_brandid_1 , CPU bran= d ID string, bytes 4 - 7 +0x80000002, 0, ecx, 31:0, cpu_brandid_2 , CPU bran= d ID string, bytes 8 - 11 +0x80000002, 0, edx, 31:0, cpu_brandid_3 , CPU bran= d ID string, bytes 12 - 15 + +# Leaf 80000003H +# CPU brand ID string, bytes 16 - 31 + +0x80000003, 0, eax, 31:0, cpu_brandid_4 , CPU bran= d ID string bytes, 16 - 19 +0x80000003, 0, ebx, 31:0, cpu_brandid_5 , CPU bran= d ID string bytes, 20 - 23 +0x80000003, 0, ecx, 31:0, cpu_brandid_6 , CPU bran= d ID string bytes, 24 - 27 +0x80000003, 0, edx, 31:0, cpu_brandid_7 , CPU bran= d ID string bytes, 28 - 31 + +# Leaf 80000004H +# CPU brand ID string, bytes 32 - 47 + +0x80000004, 0, eax, 31:0, cpu_brandid_8 , CPU bran= d ID string, bytes 32 - 35 +0x80000004, 0, ebx, 31:0, cpu_brandid_9 , CPU bran= d ID string, bytes 36 - 39 +0x80000004, 0, ecx, 31:0, cpu_brandid_10 , CPU bran= d ID string, bytes 40 - 43 +0x80000004, 0, edx, 31:0, cpu_brandid_11 , CPU bran= d ID string, bytes 44 - 47 =20 # Leaf 80000005H -# Reserved +# AMD L1 cache and L1 TLB enumeration + +0x80000005, 0, eax, 7:0, l1_itlb_2m_4m_nentries , L1 ITLB = #entires, 2M and 4M pages +0x80000005, 0, eax, 15:8, l1_itlb_2m_4m_assoc , L1 ITLB = associativity, 2M and 4M pages +0x80000005, 0, eax, 23:16, l1_dtlb_2m_4m_nentries , L1 DTLB = #entires, 2M and 4M pages +0x80000005, 0, eax, 31:24, l1_dtlb_2m_4m_assoc , L1 DTLB = associativity, 2M and 4M pages +0x80000005, 0, ebx, 7:0, l1_itlb_4k_nentries , L1 ITLB = #entries, 4K pages +0x80000005, 0, ebx, 15:8, l1_itlb_4k_assoc , L1 ITLB = associativity, 4K pages +0x80000005, 0, ebx, 23:16, l1_dtlb_4k_nentries , L1 DTLB = #entries, 4K pages +0x80000005, 0, ebx, 31:24, l1_dtlb_4k_assoc , L1 DTLB = associativity, 4K pages +0x80000005, 0, ecx, 7:0, l1_dcache_line_size , L1 dcach= e line size, in bytes +0x80000005, 0, ecx, 15:8, l1_dcache_nlines , L1 dcach= e lines per tag +0x80000005, 0, ecx, 23:16, l1_dcache_assoc , L1 dcach= e associativity +0x80000005, 0, ecx, 31:24, l1_dcache_size_kb , L1 dcach= e size, in KB +0x80000005, 0, edx, 7:0, l1_icache_line_size , L1 icach= e line size, in bytes +0x80000005, 0, edx, 15:8, l1_icache_nlines , L1 icach= e lines per tag +0x80000005, 0, edx, 23:16, l1_icache_assoc , L1 icach= e associativity +0x80000005, 0, edx, 31:24, l1_icache_size_kb , L1 icach= e size, in KB =20 # Leaf 80000006H -# Extended L2 Cache Features - -0x80000006, 0, ECX, 7:0, clsize, Cache Line size in bytes -0x80000006, 0, ECX, 15:12, l2c_assoc, L2 Associativity -0x80000006, 0, ECX, 31:16, csize, Cache size in 1K units - +# (Mostly AMD) L2 TLB, L2 cache, and L3 cache enumeration + +0x80000006, 0, eax, 11:0, l2_itlb_2m_4m_nentries , L2 iTLB = #entries, 2M and 4M pages +0x80000006, 0, eax, 15:12, l2_itlb_2m_4m_assoc , L2 iTLB = associativity, 2M and 4M pages +0x80000006, 0, eax, 27:16, l2_dtlb_2m_4m_nentries , L2 dTLB = #entries, 2M and 4M pages +0x80000006, 0, eax, 31:28, l2_dtlb_2m_4m_assoc , L2 dTLB = associativity, 2M and 4M pages +0x80000006, 0, ebx, 11:0, l2_itlb_4k_nentries , L2 iTLB = #entries, 4K pages +0x80000006, 0, ebx, 15:12, l2_itlb_4k_assoc , L2 iTLB = associativity, 4K pages +0x80000006, 0, ebx, 27:16, l2_dtlb_4k_nentries , L2 dTLB = #entries, 4K pages +0x80000006, 0, ebx, 31:28, l2_dtlb_4k_assoc , L2 dTLB = associativity, 4K pages +0x80000006, 0, ecx, 7:0, l2_line_size , L2 cache= line size, in bytes +0x80000006, 0, ecx, 11:8, l2_nlines , L2 cache= number of lines per tag +0x80000006, 0, ecx, 15:12, l2_assoc , L2 cache= associativity +0x80000006, 0, ecx, 31:16, l2_size_kb , L2 cache= size, in KB +0x80000006, 0, edx, 7:0, l3_line_size , L3 cache= line size, in bytes +0x80000006, 0, edx, 11:8, l3_nlines , L3 cache= number of lines per tag +0x80000006, 0, edx, 15:12, l3_assoc , L3 cache= associativity +0x80000006, 0, edx, 31:18, l3_size_range , L3 cache= size range =20 # Leaf 80000007H - -0x80000007, 0, EDX, 8, nonstop_tsc, Invariant TSC available - +# CPU power management (mostly AMD) and AMD RAS enumeration + +0x80000007, 0, ebx, 0, overflow_recov , MCA over= flow conditions not fatal +0x80000007, 0, ebx, 1, succor , Software= containment of UnCORRectable errors +0x80000007, 0, ebx, 2, hw_assert , Hardware= assert MSRs +0x80000007, 0, ebx, 3, smca , Scalable= MCA (MCAX MSRs) +0x80000007, 0, ecx, 31:0, cpu_pwr_sample_ratio , CPU powe= r sample time ratio +0x80000007, 0, edx, 0, digital_temp , Digital = temprature sensor +0x80000007, 0, edx, 1, powernow_freq_id , PowerNOW= ! frequency scaling +0x80000007, 0, edx, 2, powernow_volt_id , PowerNOW= ! voltage scaling +0x80000007, 0, edx, 3, thermal_trip , THERMTRI= P (Thermal Trip) +0x80000007, 0, edx, 4, hw_thermal_control , Hardware= thermal control +0x80000007, 0, edx, 5, sw_thermal_control , Software= thermal control +0x80000007, 0, edx, 6, 100mhz_steps , 100 MHz = multiplier control +0x80000007, 0, edx, 7, hw_pstate , Hardware= P-state control +0x80000007, 0, edx, 8, constant_tsc , TSC tick= s at constant rate across all P and C states +0x80000007, 0, edx, 9, cpb , Core per= formance boost +0x80000007, 0, edx, 10, eff_freq_ro , Read-onl= y effective frequency interface +0x80000007, 0, edx, 11, proc_feedback , Processo= r feedback interface (deprecated) +0x80000007, 0, edx, 12, acc_power , Processo= r power reporting interface +0x80000007, 0, edx, 13, connected_standby , CPU Conn= ected Standby support +0x80000007, 0, edx, 14, rapl , Runtime = Average Power Limit interface =20 # Leaf 80000008H - -0x80000008, 0, EAX, 7:0, phy_adr_bits, Physical Address Bits -0x80000008, 0, EAX, 15:8, lnr_adr_bits, Linear Address Bits -0x80000007, 0, EBX, 9, wbnoinvd, WBNOINVD - -# 0x8000001E -# EAX: Extended APIC ID -0x8000001E, 0, EAX, 31:0, extended_apic_id, Extended APIC ID -# EBX: Core Identifiers -0x8000001E, 0, EBX, 7:0, core_id, Identifies the logical core ID -0x8000001E, 0, EBX, 15:8, threads_per_core, The number of threads per co= re is threads_per_core + 1 -# ECX: Node Identifiers -0x8000001E, 0, ECX, 7:0, node_id, Node ID -0x8000001E, 0, ECX, 10:8, nodes_per_processor, Nodes per processor { 0: = 1 node, else reserved } - -# 8000001F: AMD Secure Encryption -0x8000001F, 0, EAX, 0, sme, Secure Memory Encryption -0x8000001F, 0, EAX, 1, sev, Secure Encrypted Virtualization -0x8000001F, 0, EAX, 2, vmpgflush, VM Page Flush MSR -0x8000001F, 0, EAX, 3, seves, SEV Encrypted State -0x8000001F, 0, EBX, 5:0, c-bit, Page table bit number used to enable me= mory encryption -0x8000001F, 0, EBX, 11:6, mem_encrypt_physaddr_width, Reduction of physi= cal address space in bits with SME enabled -0x8000001F, 0, ECX, 31:0, num_encrypted_guests, Maximum ASID value that = may be used for an SEV-enabled guest -0x8000001F, 0, EDX, 31:0, minimum_sev_asid, Minimum ASID value that must= be used for an SEV-enabled, SEV-ES-disabled guest +# CPU capacity parameters and extended feature flags (mostly AMD) + +0x80000008, 0, eax, 7:0, phys_addr_bits , Max phys= ical address bits +0x80000008, 0, eax, 15:8, virt_addr_bits , Max virt= ual address bits +0x80000008, 0, eax, 23:16, guest_phys_addr_bits , Max nest= ed-paging guest physical address bits +0x80000008, 0, ebx, 0, clzero , CLZERO s= upported +0x80000008, 0, ebx, 1, irperf , Instruct= ion retired counter MSR +0x80000008, 0, ebx, 2, xsaveerptr , XSAVE/XR= STOR always saves/restores FPU error pointers +0x80000008, 0, ebx, 3, invlpgb , INVLPGB = broadcasts a TLB invalidate to all threads +0x80000008, 0, ebx, 4, rdpru , RDPRU (R= ead Processor Register at User level) supported +0x80000008, 0, ebx, 6, mba , Memory B= andwidth Allocation (AMD bit) +0x80000008, 0, ebx, 8, mcommit , MCOMMIT = (Memory commit) supported +0x80000008, 0, ebx, 9, wbnoinvd , WBNOINVD= supported +0x80000008, 0, ebx, 12, amd_ibpb , Indirect= Branch Prediction Barrier +0x80000008, 0, ebx, 13, wbinvd_int , Interrup= tible WBINVD/WBNOINVD +0x80000008, 0, ebx, 14, amd_ibrs , Indirect= Branch Restricted Speculation +0x80000008, 0, ebx, 15, amd_stibp , Single T= hread Indirect Branch Prediction mode +0x80000008, 0, ebx, 16, ibrs_always_on , IBRS alw= ays-on preferred +0x80000008, 0, ebx, 17, amd_stibp_always_on , STIBP al= ways-on preferred +0x80000008, 0, ebx, 18, ibrs_fast , IBRS is = preferred over software solution +0x80000008, 0, ebx, 19, ibrs_same_mode , IBRS pro= vides same mode protection +0x80000008, 0, ebx, 20, no_efer_lmsle , EFER[LMS= LE] bit (Long-Mode Segment Limit Enable) unsupported +0x80000008, 0, ebx, 21, tlb_flush_nested , INVLPGB = RAX[5] bit can be set (nested translations) +0x80000008, 0, ebx, 23, amd_ppin , Protecte= d Processor Inventory Number +0x80000008, 0, ebx, 24, amd_ssbd , Speculat= ive Store Bypass Disable +0x80000008, 0, ebx, 25, virt_ssbd , virtuali= zed SSBD (Speculative Store Bypass Disable) +0x80000008, 0, ebx, 26, amd_ssb_no , SSBD not= needed (fixed in HW) +0x80000008, 0, ebx, 27, cppc , Collabor= ative Processor Performance Control +0x80000008, 0, ebx, 28, amd_psfd , Predicti= ve Store Forward Disable +0x80000008, 0, ebx, 29, btc_no , CPU not = affected by Branch Type Confusion +0x80000008, 0, ebx, 30, ibpb_ret , IBPB cle= ars RSB/RAS too +0x80000008, 0, ebx, 31, brs , Branch S= ampling supported +0x80000008, 0, ecx, 7:0, cpu_nthreads , Number o= f physical threads - 1 +0x80000008, 0, ecx, 15:12, apicid_coreid_len , Number o= f thread core ID bits (shift) in APIC ID +0x80000008, 0, ecx, 17:16, perf_tsc_len , Performa= nce time-stamp counter size +0x80000008, 0, edx, 15:0, invlpgb_max_pages , INVLPGB = maximum page count +0x80000008, 0, edx, 31:16, rdpru_max_reg_id , RDPRU ma= x register ID (ECX input) + +# Leaf 8000000AH +# AMD SVM (Secure Virtual Machine) enumeration + +0x8000000a, 0, eax, 7:0, svm_version , SVM revi= sion number +0x8000000a, 0, ebx, 31:0, svm_nasid , Number o= f address space identifiers (ASID) +0x8000000a, 0, edx, 0, npt , Nested p= aging +0x8000000a, 0, edx, 1, lbrv , LBR virt= ualization +0x8000000a, 0, edx, 2, svm_lock , SVM lock +0x8000000a, 0, edx, 3, nrip_save , NRIP sav= e support on #VMEXIT +0x8000000a, 0, edx, 4, tsc_scale , MSR base= d TSC rate control +0x8000000a, 0, edx, 5, vmcb_clean , VMCB cle= an bits support +0x8000000a, 0, edx, 6, flushbyasid , Flush by= ASID + Extended VMCB TLB_Control +0x8000000a, 0, edx, 7, decodeassists , Decode A= ssists support +0x8000000a, 0, edx, 10, pausefilter , Pause in= tercept filter +0x8000000a, 0, edx, 12, pfthreshold , Pause fi= lter threshold +0x8000000a, 0, edx, 13, avic , Advanced= virtual interrupt controller +0x8000000a, 0, edx, 15, v_vmsave_vmload , Virtual = VMSAVE/VMLOAD (nested virt) +0x8000000a, 0, edx, 16, vgif , Virtuali= ze the Global Interrupt Flag +0x8000000a, 0, edx, 17, gmet , Guest mo= de execution trap +0x8000000a, 0, edx, 18, x2avic , Virtual = x2APIC +0x8000000a, 0, edx, 19, sss_check , Supervis= or Shadow Stack restrictions +0x8000000a, 0, edx, 20, v_spec_ctrl , Virtual = SPEC_CTRL +0x8000000a, 0, edx, 21, ro_gpt , Read-Onl= y guest page table support +0x8000000a, 0, edx, 23, h_mce_override , Host MCE= override +0x8000000a, 0, edx, 24, tlbsync_int , TLBSYNC = intercept + INVLPGB/TLBSYNC in VMCB +0x8000000a, 0, edx, 25, vnmi , NMI virt= ualization +0x8000000a, 0, edx, 26, ibs_virt , IBS Virt= ualization +0x8000000a, 0, edx, 27, ext_lvt_off_chg , Extended= LVT offset fault change +0x8000000a, 0, edx, 28, svme_addr_chk , Guest SV= ME addr check + +# Leaf 80000019H +# AMD TLB 1G-pages enumeration + +0x80000019, 0, eax, 11:0, l1_itlb_1g_nentries , L1 iTLB = #entries, 1G pages +0x80000019, 0, eax, 15:12, l1_itlb_1g_assoc , L1 iTLB = associativity, 1G pages +0x80000019, 0, eax, 27:16, l1_dtlb_1g_nentries , L1 dTLB = #entries, 1G pages +0x80000019, 0, eax, 31:28, l1_dtlb_1g_assoc , L1 dTLB = associativity, 1G pages +0x80000019, 0, ebx, 11:0, l2_itlb_1g_nentries , L2 iTLB = #entries, 1G pages +0x80000019, 0, ebx, 15:12, l2_itlb_1g_assoc , L2 iTLB = associativity, 1G pages +0x80000019, 0, ebx, 27:16, l2_dtlb_1g_nentries , L2 dTLB = #entries, 1G pages +0x80000019, 0, ebx, 31:28, l2_dtlb_1g_assoc , L2 dTLB = associativity, 1G pages + +# Leaf 8000001AH +# AMD instruction optimizations enumeration + +0x8000001a, 0, eax, 0, fp_128 , Internal= FP/SIMD exec data path is 128-bits wide +0x8000001a, 0, eax, 1, movu_preferred , SSE: MOV= U* better than MOVL*/MOVH* +0x8000001a, 0, eax, 2, fp_256 , internal= FP/SSE exec data path is 256-bits wide + +# Leaf 8000001BH +# AMD IBS (Instruction-Based Sampling) enumeration + +0x8000001b, 0, eax, 0, ibs_flags_valid , IBS feat= ure flags valid +0x8000001b, 0, eax, 1, ibs_fetch_sampling , IBS fetc= h sampling supported +0x8000001b, 0, eax, 2, ibs_op_sampling , IBS exec= ution sampling supported +0x8000001b, 0, eax, 3, ibs_rdwr_op_counter , IBS read= /write of op counter supported +0x8000001b, 0, eax, 4, ibs_op_count , IBS OP c= ounting mode supported +0x8000001b, 0, eax, 5, ibs_branch_target , IBS bran= ch target address reporting supported +0x8000001b, 0, eax, 6, ibs_op_counters_ext , IBS IbsO= pCurCnt/IbsOpMaxCnt extend by 7 bits +0x8000001b, 0, eax, 7, ibs_rip_invalid_chk , IBS inva= lid RIP indication supported +0x8000001b, 0, eax, 8, ibs_op_branch_fuse , IBS fuse= d branch micro-op indication supported +0x8000001b, 0, eax, 9, ibs_fetch_ctl_ext , IBS Fetc= h Control Extended MSR (0xc001103c) supported +0x8000001b, 0, eax, 10, ibs_op_data_4 , IBS op d= ata 4 MSR supported +0x8000001b, 0, eax, 11, ibs_l3_miss_filter , IBS L3-m= iss filtering supported (Zen4+) + +# Leaf 8000001CH +# AMD LWP (Lightweight Profiling) + +0x8000001c, 0, eax, 0, os_lwp_avail , LWP is a= vailable to application programs (supported by OS) +0x8000001c, 0, eax, 1, os_lpwval , LWPVAL i= nstruction (EventId=3D1) is supported by OS +0x8000001c, 0, eax, 2, os_lwp_ire , Instruct= ions Retired Event (EventId=3D2) is supported by OS +0x8000001c, 0, eax, 3, os_lwp_bre , Branch R= etired Event (EventId=3D3) is supported by OS +0x8000001c, 0, eax, 4, os_lwp_dme , DCache M= iss Event (EventId=3D4) is supported by OS +0x8000001c, 0, eax, 5, os_lwp_cnh , CPU Cloc= ks Not Halted event (EventId=3D5) is supported by OS +0x8000001c, 0, eax, 6, os_lwp_rnh , CPU Refe= rence clocks Not Halted event (EventId=3D6) is supported by OS +0x8000001c, 0, eax, 29, os_lwp_cont , LWP samp= ling in continuous mode is supported by OS +0x8000001c, 0, eax, 30, os_lwp_ptsc , Performa= nce Time Stamp Counter in event records is supported by OS +0x8000001c, 0, eax, 31, os_lwp_int , Interrup= t on threshold overflow is supported by OS +0x8000001c, 0, ebx, 7:0, lwp_lwpcb_sz , LWP Cont= rol Block size, in quadwords +0x8000001c, 0, ebx, 15:8, lwp_event_sz , LWP even= t record size, in bytes +0x8000001c, 0, ebx, 23:16, lwp_max_events , LWP max = supported EventId value (EventID 255 not included) +0x8000001c, 0, ebx, 31:24, lwp_event_offset , LWP even= ts area offset in the LWP Control Block +0x8000001c, 0, ecx, 4:0, lwp_latency_max , Num of b= its in cache latency counters (10 to 31) +0x8000001c, 0, ecx, 5, lwp_data_adddr , Cache mi= ss events report the data address of the reference +0x8000001c, 0, ecx, 8:6, lwp_latency_rnd , Amount b= y which cache latency is rounded +0x8000001c, 0, ecx, 15:9, lwp_version , LWP impl= ementation version +0x8000001c, 0, ecx, 23:16, lwp_buf_min_sz , LWP even= t ring buffer min size, in units of 32 event records +0x8000001c, 0, ecx, 28, lwp_branch_predict , Branches= Retired events can be filtered +0x8000001c, 0, ecx, 29, lwp_ip_filtering , IP filte= ring (IPI, IPF, BaseIP, and LimitIP @ LWPCP) supported +0x8000001c, 0, ecx, 30, lwp_cache_levels , Cache-re= lated events can be filtered by cache level +0x8000001c, 0, ecx, 31, lwp_cache_latency , Cache-re= lated events can be filtered by latency +0x8000001c, 0, edx, 0, hw_lwp_avail , LWP is a= vailable in Hardware +0x8000001c, 0, edx, 1, hw_lpwval , LWPVAL i= nstruction (EventId=3D1) is available in HW +0x8000001c, 0, edx, 2, hw_lwp_ire , Instruct= ions Retired Event (EventId=3D2) is available in HW +0x8000001c, 0, edx, 3, hw_lwp_bre , Branch R= etired Event (EventId=3D3) is available in HW +0x8000001c, 0, edx, 4, hw_lwp_dme , DCache M= iss Event (EventId=3D4) is available in HW +0x8000001c, 0, edx, 5, hw_lwp_cnh , CPU Cloc= ks Not Halted event (EventId=3D5) is available in HW +0x8000001c, 0, edx, 6, hw_lwp_rnh , CPU Refe= rence clocks Not Halted event (EventId=3D6) is available in HW +0x8000001c, 0, edx, 29, hw_lwp_cont , LWP samp= ling in continuous mode is available in HW +0x8000001c, 0, edx, 30, hw_lwp_ptsc , Performa= nce Time Stamp Counter in event records is available in HW +0x8000001c, 0, edx, 31, hw_lwp_int , Interrup= t on threshold overflow is available in HW + +# Leaf 8000001DH +# AMD deterministic cache parameters + +0x8000001d, 31:0, eax, 4:0, cache_type , Cache ty= pe field +0x8000001d, 31:0, eax, 7:5, cache_level , Cache le= vel (1-based) +0x8000001d, 31:0, eax, 8, cache_self_init , Self-ini= tializing cache level +0x8000001d, 31:0, eax, 9, fully_associative , Fully-as= sociative cache +0x8000001d, 31:0, eax, 25:14, num_threads_sharing , Number o= f logical CPUs sharing cache +0x8000001d, 31:0, ebx, 11:0, cache_linesize , System c= oherency line size (0-based) +0x8000001d, 31:0, ebx, 21:12, cache_npartitions , Physical= line partitions (0-based) +0x8000001d, 31:0, ebx, 31:22, cache_nways , Ways of = associativity (0-based) +0x8000001d, 31:0, ecx, 30:0, cache_nsets , Cache nu= mber of sets (0-based) +0x8000001d, 31:0, edx, 0, wbinvd_rll_no_guarantee, WBINVD/I= NVD not guaranteed for Remote Lower-Level caches +0x8000001d, 31:0, edx, 1, ll_inclusive , Cache is= inclusive of Lower-Level caches + +# Leaf 8000001EH +# AMD CPU topology enumeration + +0x8000001e, 0, eax, 31:0, ext_apic_id , Extended= APIC ID +0x8000001e, 0, ebx, 7:0, core_id , Unique p= er-socket logical core unit ID +0x8000001e, 0, ebx, 15:8, core_nthreas , #Threads= per core (zero-based) +0x8000001e, 0, ecx, 7:0, node_id , Node (di= e) ID of invoking logical CPU +0x8000001e, 0, ecx, 10:8, nnodes_per_socket , #nodes i= n invoking logical CPU's package/socket + +# Leaf 8000001FH +# AMD encrypted memory capabilities enumeration (SME/SEV) + +0x8000001f, 0, eax, 0, sme , Secure M= emory Encryption supported +0x8000001f, 0, eax, 1, sev , Secure E= ncrypted Virtualization supported +0x8000001f, 0, eax, 2, vm_page_flush , VM Page = Flush MSR (0xc001011e) available +0x8000001f, 0, eax, 3, sev_es , SEV Encr= ypted State supported +0x8000001f, 0, eax, 4, sev_nested_paging , SEV secu= re nested paging supported +0x8000001f, 0, eax, 5, vm_permission_levels , VMPL sup= ported +0x8000001f, 0, eax, 6, rpmquery , RPMQUERY= instruction supported +0x8000001f, 0, eax, 7, vmpl_sss , VMPL sup= ervisor shadwo stack supported +0x8000001f, 0, eax, 8, secure_tsc , Secure T= SC supported +0x8000001f, 0, eax, 9, v_tsc_aux , Hardware= virtualizes TSC_AUX +0x8000001f, 0, eax, 10, sme_coherent , HW enfor= ces cache coherency across encryption domains +0x8000001f, 0, eax, 11, req_64bit_hypervisor , SEV gues= t mandates 64-bit hypervisor +0x8000001f, 0, eax, 12, restricted_injection , Restrict= ed Injection supported +0x8000001f, 0, eax, 13, alternate_injection , Alternat= e Injection supported +0x8000001f, 0, eax, 14, debug_swap , SEV-ES: = full debug state swap is supported +0x8000001f, 0, eax, 15, disallow_host_ibs , SEV-ES: = Disallowing IBS use by the host is supported +0x8000001f, 0, eax, 16, virt_transparent_enc , Virtual = Transparent Encryption +0x8000001f, 0, eax, 17, vmgexit_paremeter , VmgexitP= arameter is supported in SEV_FEATURES +0x8000001f, 0, eax, 18, virt_tom_msr , Virtual = TOM MSR is supported +0x8000001f, 0, eax, 19, virt_ibs , IBS stat= e virtualization is supported for SEV-ES guests +0x8000001f, 0, eax, 24, vmsa_reg_protection , VMSA reg= ister protection is supported +0x8000001f, 0, eax, 25, smt_protection , SMT prot= ection is supported +0x8000001f, 0, eax, 28, svsm_page_msr , SVSM com= munication page MSR (0xc001f000h) is supported +0x8000001f, 0, eax, 29, nested_virt_snp_msr , VIRT_RMP= UPDATE/VIRT_PSMASH MSRs are supported +0x8000001f, 0, ebx, 5:0, pte_cbit_pos , PTE bit = number used to enable memory encryption +0x8000001f, 0, ebx, 11:6, phys_addr_reduction_nbits, Reduct= ion of phys address space when encryption is enabled, in bits +0x8000001f, 0, ebx, 15:12, vmpl_count , Number o= f VM permission levels (VMPL) supported +0x8000001f, 0, ecx, 31:0, enc_guests_max , Max supp= orted number of simultaneous encrypted guests +0x8000001f, 0, edx, 31:0, min_sev_asid_no_sev_es , Mininum = ASID for SEV-enabled SEV-ES-disabled guest + +# Leaf 80000020H +# AMD Platform QoS extended feature IDs + +0x80000020, 0, ebx, 1, mba , Memory B= andwidth Allocation support +0x80000020, 0, ebx, 2, smba , Slow Mem= ory Bandwidth Allocation support +0x80000020, 0, ebx, 3, bmec , Bandwidt= h Monitoring Event Configuration support +0x80000020, 0, ebx, 4, l3rr , L3 Range= Reservation support +0x80000020, 1, eax, 31:0, mba_limit_len , MBA enfo= rcement limit size +0x80000020, 1, edx, 31:0, mba_cos_max , MBA max = Class of Service number (zero-based) +0x80000020, 2, eax, 31:0, smba_limit_len , SMBA enf= orcement limit size +0x80000020, 2, edx, 31:0, smba_cos_max , SMBA max= Class of Service number (zero-based) +0x80000020, 3, ebx, 7:0, bmec_num_events , BMEC num= ber of bandwidth events available +0x80000020, 3, ecx, 0, bmec_local_reads , Local NU= MA reads can be tracked +0x80000020, 3, ecx, 1, bmec_remote_reads , Remote N= UMA reads can be tracked +0x80000020, 3, ecx, 2, bmec_local_nontemp_wr , Local NU= MA non-temporal writes can be tracked +0x80000020, 3, ecx, 3, bmec_remote_nontemp_wr , Remote N= UMA non-temporal writes can be tracked +0x80000020, 3, ecx, 4, bmec_local_slow_mem_rd , Local NU= MA slow-memory reads can be tracked +0x80000020, 3, ecx, 5, bmec_remote_slow_mem_rd, Remote N= UMA slow-memory reads can be tracked +0x80000020, 3, ecx, 6, bmec_all_dirty_victims , Dirty Qo= S victims to all types of memory can be tracked + +# Leaf 80000021H +# AMD extended features enumeration 2 + +0x80000021, 0, eax, 0, no_nested_data_bp , No neste= d data breakpoints +0x80000021, 0, eax, 1, fsgs_non_serializing , WRMSR to= {FS,GS,KERNEL_GS}_BASE is non-serializing +0x80000021, 0, eax, 2, lfence_rdtsc , LFENCE a= lways serializing / synchronizes RDTSC +0x80000021, 0, eax, 3, smm_page_cfg_lock , SMM pagi= ng configuration lock is supported +0x80000021, 0, eax, 6, null_sel_clr_base , Null sel= ector clears base +0x80000021, 0, eax, 7, upper_addr_ignore , EFER MSR= Upper Address Ignore Enable bit supported +0x80000021, 0, eax, 8, autoibrs , EFER MSR= Automatic IBRS enable bit supported +0x80000021, 0, eax, 9, no_smm_ctl_msr , SMM_CTL = MSR (0xc0010116) is not present +0x80000021, 0, eax, 10, fsrs_supported , Fast Sho= rt Rep Stosb (FSRS) is supported +0x80000021, 0, eax, 11, fsrc_supported , Fast Sho= rt Repe Cmpsb (FSRC) is supported +0x80000021, 0, eax, 13, prefetch_ctl_msr , Prefetch= control MSR is supported +0x80000021, 0, eax, 17, user_cpuid_disable , #GP when= executing CPUID at CPL > 0 is supported +0x80000021, 0, eax, 18, epsf_supported , Enhanced= Predictive Store Forwarding (EPSF) is supported +0x80000021, 0, ebx, 11:0, microcode_patch_size , Size of = microcode patch, in 16-byte units + +# Leaf 80000022H +# AMD Performance Monitoring v2 enumeration + +0x80000022, 0, eax, 0, perfmon_v2 , Performa= nce monitoring v2 supported +0x80000022, 0, eax, 1, lbr_v2 , Last Bra= nch Record v2 extensions (LBR Stack) +0x80000022, 0, eax, 2, lbr_pmc_freeze , Freezing= core performance counters / LBR Stack supported +0x80000022, 0, ebx, 3:0, n_pmc_core , Number o= f core perfomance counters +0x80000022, 0, ebx, 9:4, lbr_v2_stack_size , Number o= f available LBR stack entries +0x80000022, 0, ebx, 15:10, n_pmc_northbridge , Number o= f available northbridge (data fabric) performance counters +0x80000022, 0, ebx, 21:16, n_pmc_umc , Number o= f available UMC performance counters +0x80000022, 0, ecx, 31:0, active_umc_bitmask , Active U= MCs bitmask + +# Leaf 80000023H +# AMD Secure Multi-key Encryption enumeration + +0x80000023, 0, eax, 0, mem_hmk_mode , MEM-HMK = encryption mode is supported +0x80000023, 0, ebx, 15:0, mem_hmk_avail_keys , MEM-HMK = mode: total num of available encryption keys + +# Leaf 80000026H +# AMD extended topology enumeration v2 + +0x80000026, 3:0, eax, 4:0, x2apic_id_shift , Bit widt= h of this level (previous levels inclusive) +0x80000026, 3:0, eax, 29, core_has_pwreff_ranking, This cor= e has a power efficiency ranking +0x80000026, 3:0, eax, 30, domain_has_hybrid_cores, This dom= ain level has hybrid (E, P) cores +0x80000026, 3:0, eax, 31, domain_core_count_asymm, The 'Cor= e' domain has asymmetric cores count +0x80000026, 3:0, ebx, 15:0, domain_lcpus_count , Number o= f logical CPUs at this domain instance +0x80000026, 3:0, ebx, 23:16, core_pwreff_ranking , This cor= e's static power efficiency ranking +0x80000026, 3:0, ebx, 27:24, core_native_model_id , This cor= e's native model ID +0x80000026, 3:0, ebx, 31:28, core_type , This cor= e's type +0x80000026, 3:0, ecx, 7:0, domain_level , This dom= ain level (subleaf ID) +0x80000026, 3:0, ecx, 15:8, domain_type , This dom= ain type +0x80000026, 3:0, edx, 31:0, x2apic_id , x2APIC I= D of current logical CPU --=20 2.45.2 From nobody Wed Dec 17 01:11:21 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA02213C687 for ; Thu, 18 Jul 2024 13:48:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; 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Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1721310509; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=M0IE5GYwEyXTF1wT/SvpMPXeXglNDdssNBGW9kCeBSM=; b=h4d+j8JRRPx/0B9ztINOng8/8W9AKhjXh2axvwtbul7SapzwZDbp7E8QdqzLMBFTkqZJK6 5VdeH2GF1n7ElLXjX8VSC5vCXQINYsU5YfDsfbTYJEIWjrAj8aZDWyZvXWfP4enQnfTFB4 I1ESokkwg89fD5V/8SfjqOnkPMXwuHLUcC5yEInbbgIt7cO4CCjHKJixyW8J0MShtz43BQ AYuoL7Ilq4eSBJiESQdw6zTMNf+uwxa5Eu4R1EDlu0JGHw9eqKZTPCaWBx/QSpzwiAR1GO zhYcKnX576JNvqh5wev9eyd9WzzGjrkrQUKM9oNH8a63l/8+mbQsDJDZSB2mgQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1721310509; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=M0IE5GYwEyXTF1wT/SvpMPXeXglNDdssNBGW9kCeBSM=; b=aI+1grjGPx8vJWpjz35uzjDhbMH7dBJaAIneo7AJp9byYvaCdRUBBVQfoiNhrdZckENo7u cibhTjgusNnHcmCQ== To: Borislav Petkov , Ingo Molnar , Dave Hansen , "H. Peter Anvin" , x86@kernel.org, x86-cpuid@lists.linux.dev Cc: Thomas Gleixner , linux-kernel@vger.kernel.org, "Ahmed S. Darwish" Subject: [PATCH v1 9/9] MAINTAINERS: Add x86 cpuid database entry Date: Thu, 18 Jul 2024 15:47:49 +0200 Message-ID: <20240718134755.378115-10-darwi@linutronix.de> In-Reply-To: <20240718134755.378115-1-darwi@linutronix.de> References: <20240718134755.378115-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a specific entry for the x86 architecture cpuid database. Reference the x86-cpuid.org development mailing list to facilitate easy tracking by external stakeholders such as the Xen developers. Include myself as a reviewer. Note, this MAINTAINERS entry will also cover the auto-generated C cpuid bitfields header files to be submitted in a future series. Signed-off-by: Ahmed S. Darwish Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db Link: https://lore.kernel.org/x86-cpuid Link: https://x86-cpuid.org --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 958e935449e5..744962547049 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -24340,6 +24340,16 @@ F: Documentation/arch/x86/ F: Documentation/devicetree/bindings/x86/ F: arch/x86/ =20 +X86 CPUID DATABASE +M: Thomas Gleixner +M: Borislav Petkov +M: x86@kernel.org +R: Ahmed S. Darwish +L: x86-cpuid@lists.linux.dev +S: Maintained +W: https://x86-cpuid.org +F: tools/arch/x86/kcpuid/cpuid.csv + X86 ENTRY CODE M: Andy Lutomirski L: linux-kernel@vger.kernel.org --=20 2.45.2