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[211.75.127.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70b7eca69f0sm9443573b3a.150.2024.07.18.00.55.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jul 2024 00:55:12 -0700 (PDT) Received: from hqs-appsw-a2o.mp600.macronix.com (linux-patcher [172.17.236.67]) by twhmp6px (Postfix) with ESMTPS id 7D21580483; Thu, 18 Jul 2024 16:04:22 +0800 (CST) From: Cheng Ming Lin To: miquel.raynal@bootlin.com, vigneshr@ti.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: richard@nod.at, alvinzhou@mxic.com.tw, leoyu@mxic.com.tw, Cheng Ming Lin Subject: [PATCH v2 1/2] mtd: spinand: Add fixups for spinand Date: Thu, 18 Jul 2024 15:53:55 +0800 Message-Id: <20240718075356.488253-2-linchengming884@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240718075356.488253-1-linchengming884@gmail.com> References: <20240718075356.488253-1-linchengming884@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cheng Ming Lin Add struct spi_nand_fixups as SPI NAND fixup hooks. To determine whether the Plane Select bit should be inserted into the column address, add the member struct spinand_info to struct spinand_device to ascertain whether the device has fixups. In the function spinand_read_from_cache_op and spinand_write_to_cache_op, add an if statement to determine whether the device has fixups and their corresponding functions. If so, give the Plane Select bit to the column address. In the function spinand_match_and_init, add spinand_info in spinand_device for determing whether Plane Select bitg should be inserted. Signed-off-by: Cheng Ming Lin --- drivers/mtd/nand/spi/core.c | 7 +++++++ include/linux/mtd/spinand.h | 17 +++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index e0b6715e5dfe..d6d6f3832f9d 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -386,6 +386,9 @@ static int spinand_read_from_cache_op(struct spinand_de= vice *spinand, else rdesc =3D spinand->dirmaps[req->pos.plane].rdesc_ecc; =20 + if (spinand->info->fixups && spinand->info->fixups->read_from_cache) + column =3D spinand->info->fixups->read_from_cache(spinand, req, column); + while (nbytes) { ret =3D spi_mem_dirmap_read(rdesc, column, nbytes, buf); if (ret < 0) @@ -460,6 +463,9 @@ static int spinand_write_to_cache_op(struct spinand_dev= ice *spinand, else wdesc =3D spinand->dirmaps[req->pos.plane].wdesc_ecc; =20 + if (spinand->info->fixups && spinand->info->fixups->write_to_cache) + column =3D spinand->info->fixups->write_to_cache(spinand, req, column); + while (nbytes) { ret =3D spi_mem_dirmap_write(wdesc, column, nbytes, buf); if (ret < 0) @@ -1095,6 +1101,7 @@ int spinand_match_and_init(struct spinand_device *spi= nand, spinand->flags =3D table[i].flags; spinand->id.len =3D 1 + table[i].devid.len; spinand->select_target =3D table[i].select_target; + spinand->info =3D info; =20 op =3D spinand_select_op_variant(spinand, info->op_variants.read_cache); diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 5c19ead60499..c079c6ac1541 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -354,6 +354,7 @@ struct spinand_info { } op_variants; int (*select_target)(struct spinand_device *spinand, unsigned int target); + const struct spi_nand_fixups *fixups; }; =20 #define SPINAND_ID(__method, ...) \ @@ -379,6 +380,9 @@ struct spinand_info { #define SPINAND_SELECT_TARGET(__func) \ .select_target =3D __func, =20 +#define SPINAND_PLANE_SELECT_BIT(__func) \ + .fixups =3D __func, + #define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants, \ __flags, ...) \ { \ @@ -398,6 +402,18 @@ struct spinand_dirmap { struct spi_mem_dirmap_desc *rdesc_ecc; }; =20 +/** + * struct spi_nand_fixups - SPI NAND fixup hooks + * @write_to_cache: program load requires Plane Select bit in CADD. + * @read_from_cache: read from cache requires Plane Select bit in CADD. + */ +struct spi_nand_fixups { + unsigned int (*write_to_cache)(struct spinand_device *spinand, + const struct nand_page_io_req *req, unsigned int column); + u16 (*read_from_cache)(struct spinand_device *spinand, + const struct nand_page_io_req *req, u16 column); +}; + /** * struct spinand_device - SPI NAND device instance * @base: NAND device instance @@ -449,6 +465,7 @@ struct spinand_device { u8 *databuf; u8 *oobbuf; u8 *scratchbuf; + const struct spinand_info *info; const struct spinand_manufacturer *manufacturer; void *priv; }; --=20 2.25.1