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[211.75.127.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70b7eca69f0sm9443573b3a.150.2024.07.18.00.55.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jul 2024 00:55:12 -0700 (PDT) Received: from hqs-appsw-a2o.mp600.macronix.com (linux-patcher [172.17.236.67]) by twhmp6px (Postfix) with ESMTPS id 7D21580483; Thu, 18 Jul 2024 16:04:22 +0800 (CST) From: Cheng Ming Lin To: miquel.raynal@bootlin.com, vigneshr@ti.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: richard@nod.at, alvinzhou@mxic.com.tw, leoyu@mxic.com.tw, Cheng Ming Lin Subject: [PATCH v2 1/2] mtd: spinand: Add fixups for spinand Date: Thu, 18 Jul 2024 15:53:55 +0800 Message-Id: <20240718075356.488253-2-linchengming884@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240718075356.488253-1-linchengming884@gmail.com> References: <20240718075356.488253-1-linchengming884@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cheng Ming Lin Add struct spi_nand_fixups as SPI NAND fixup hooks. To determine whether the Plane Select bit should be inserted into the column address, add the member struct spinand_info to struct spinand_device to ascertain whether the device has fixups. In the function spinand_read_from_cache_op and spinand_write_to_cache_op, add an if statement to determine whether the device has fixups and their corresponding functions. If so, give the Plane Select bit to the column address. In the function spinand_match_and_init, add spinand_info in spinand_device for determing whether Plane Select bitg should be inserted. Signed-off-by: Cheng Ming Lin --- drivers/mtd/nand/spi/core.c | 7 +++++++ include/linux/mtd/spinand.h | 17 +++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index e0b6715e5dfe..d6d6f3832f9d 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -386,6 +386,9 @@ static int spinand_read_from_cache_op(struct spinand_de= vice *spinand, else rdesc =3D spinand->dirmaps[req->pos.plane].rdesc_ecc; =20 + if (spinand->info->fixups && spinand->info->fixups->read_from_cache) + column =3D spinand->info->fixups->read_from_cache(spinand, req, column); + while (nbytes) { ret =3D spi_mem_dirmap_read(rdesc, column, nbytes, buf); if (ret < 0) @@ -460,6 +463,9 @@ static int spinand_write_to_cache_op(struct spinand_dev= ice *spinand, else wdesc =3D spinand->dirmaps[req->pos.plane].wdesc_ecc; =20 + if (spinand->info->fixups && spinand->info->fixups->write_to_cache) + column =3D spinand->info->fixups->write_to_cache(spinand, req, column); + while (nbytes) { ret =3D spi_mem_dirmap_write(wdesc, column, nbytes, buf); if (ret < 0) @@ -1095,6 +1101,7 @@ int spinand_match_and_init(struct spinand_device *spi= nand, spinand->flags =3D table[i].flags; spinand->id.len =3D 1 + table[i].devid.len; spinand->select_target =3D table[i].select_target; + spinand->info =3D info; =20 op =3D spinand_select_op_variant(spinand, info->op_variants.read_cache); diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 5c19ead60499..c079c6ac1541 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -354,6 +354,7 @@ struct spinand_info { } op_variants; int (*select_target)(struct spinand_device *spinand, unsigned int target); + const struct spi_nand_fixups *fixups; }; =20 #define SPINAND_ID(__method, ...) \ @@ -379,6 +380,9 @@ struct spinand_info { #define SPINAND_SELECT_TARGET(__func) \ .select_target =3D __func, =20 +#define SPINAND_PLANE_SELECT_BIT(__func) \ + .fixups =3D __func, + #define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants, \ __flags, ...) \ { \ @@ -398,6 +402,18 @@ struct spinand_dirmap { struct spi_mem_dirmap_desc *rdesc_ecc; }; =20 +/** + * struct spi_nand_fixups - SPI NAND fixup hooks + * @write_to_cache: program load requires Plane Select bit in CADD. + * @read_from_cache: read from cache requires Plane Select bit in CADD. + */ +struct spi_nand_fixups { + unsigned int (*write_to_cache)(struct spinand_device *spinand, + const struct nand_page_io_req *req, unsigned int column); + u16 (*read_from_cache)(struct spinand_device *spinand, + const struct nand_page_io_req *req, u16 column); +}; + /** * struct spinand_device - SPI NAND device instance * @base: NAND device instance @@ -449,6 +465,7 @@ struct spinand_device { u8 *databuf; u8 *oobbuf; u8 *scratchbuf; + const struct spinand_info *info; const struct spinand_manufacturer *manufacturer; void *priv; }; --=20 2.25.1 From nobody Tue Dec 16 19:43:02 2025 Received: from mail-pg1-f170.google.com (mail-pg1-f170.google.com [209.85.215.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AED8574058 for ; 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[211.75.127.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fc0bc392a7sm86526905ad.230.2024.07.18.00.55.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jul 2024 00:55:12 -0700 (PDT) Received: from hqs-appsw-a2o.mp600.macronix.com (linux-patcher [172.17.236.67]) by twhmp6px (Postfix) with ESMTPS id F2151805EF; Thu, 18 Jul 2024 16:04:23 +0800 (CST) From: Cheng Ming Lin To: miquel.raynal@bootlin.com, vigneshr@ti.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: richard@nod.at, alvinzhou@mxic.com.tw, leoyu@mxic.com.tw, Cheng Ming Lin Subject: [PATCH v2 2/2] mtd: spinand: macronix: Fixups for Plane Select bit Date: Thu, 18 Jul 2024 15:53:56 +0800 Message-Id: <20240718075356.488253-3-linchengming884@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240718075356.488253-1-linchengming884@gmail.com> References: <20240718075356.488253-1-linchengming884@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cheng Ming Lin Macronix serial NAND flash with a two-plane structure requires insertion of Plane Select bit into the column address during the write_to_cache operation. Additionally, for MX35{U,F}2G14AC, insertion of Plane Select bit into the column address is required during the read_from_cache operation. Signed-off-by: Cheng Ming Lin --- drivers/mtd/nand/spi/macronix.c | 66 ++++++++++++++++++++++++++++++--- 1 file changed, 60 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macroni= x.c index 3f9e9c572854..eda67091edc0 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c @@ -100,6 +100,54 @@ static int mx35lf1ge4ab_ecc_get_status(struct spinand_= device *spinand, return -EINVAL; } =20 +/** + * write_plane_select_bit_in_cadd - Write Plane Select bit to the column a= ddress + * @spinand: SPI NAND device + * @req: NAND I/O request object + * @column: the column address + * + * Macronix serial NAND flash with a two-plane structure + * should insert Plane Select bit into the column address + * during the write_to_cache operation. + * + * Return: the column address after insertion of Plane Select bit + */ +static unsigned int write_plane_select_bit_in_cadd(struct spinand_device *= spinand, + const struct nand_page_io_req *req, unsigned int column) +{ + struct nand_device *nand =3D spinand_to_nand(spinand); + + return column | (req->pos.plane << fls(nanddev_page_size(nand))); +} + +/** + * read_plane_select_bit_in_cadd - Write Plane Select bit to the column ad= dress + * @spinand: SPI NAND device + * @req: NAND I/O request object + * @column: the column address + * + * MX35{U,F}2G14AC also need to insert Plane Select bit + * into the column address during the read_from_cache operation. + * + * Return: the column address after insertion of Plane Select bit + */ +static u16 read_plane_select_bit_in_cadd(struct spinand_device *spinand, + const struct nand_page_io_req *req, u16 column) +{ + struct nand_device *nand =3D spinand_to_nand(spinand); + + return column | (req->pos.plane << fls(nanddev_page_size(nand))); +} + +static const struct spi_nand_fixups write_fixups =3D { + .write_to_cache =3D write_plane_select_bit_in_cadd, +}; + +static const struct spi_nand_fixups read_and_write_fixups =3D { + .write_to_cache =3D write_plane_select_bit_in_cadd, + .read_from_cache =3D read_plane_select_bit_in_cadd, +}; + static const struct spinand_info macronix_spinand_table[] =3D { SPINAND_INFO("MX35LF1GE4AB", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x12), @@ -157,7 +205,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, - SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL), + SPINAND_PLANE_SELECT_BIT(&write_fixups)), SPINAND_INFO("MX35LF2G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x64, 0x03), NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), @@ -175,7 +224,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, - SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL), + SPINAND_PLANE_SELECT_BIT(&write_fixups)), SPINAND_INFO("MX35LF4G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x75, 0x03), NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), @@ -215,7 +265,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, - mx35lf1ge4ab_ecc_get_status)), + mx35lf1ge4ab_ecc_get_status), + SPINAND_PLANE_SELECT_BIT(&read_and_write_fixups)), SPINAND_INFO("MX35UF4G24AD", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb5, 0x03), NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 2, 1, 1), @@ -225,7 +276,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, - mx35lf1ge4ab_ecc_get_status)), + mx35lf1ge4ab_ecc_get_status), + SPINAND_PLANE_SELECT_BIT(&write_fixups)), SPINAND_INFO("MX35UF4G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xf5, 0x03), NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), @@ -255,7 +307,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, - mx35lf1ge4ab_ecc_get_status)), + mx35lf1ge4ab_ecc_get_status), + SPINAND_PLANE_SELECT_BIT(&read_and_write_fixups)), SPINAND_INFO("MX35UF2G24AD", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa4, 0x03), NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1), @@ -265,7 +318,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, - mx35lf1ge4ab_ecc_get_status)), + mx35lf1ge4ab_ecc_get_status), + SPINAND_PLANE_SELECT_BIT(&write_fixups)), SPINAND_INFO("MX35UF2G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xe4, 0x03), NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), --=20 2.25.1