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Thu, 18 Jul 2024 08:21:24 -0700 (PDT) Received: from [192.168.1.191] ([2a0a:ef40:ee7:2401:197d:e048:a80f:bc44]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3685b326692sm1590366f8f.80.2024.07.18.08.21.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jul 2024 08:21:23 -0700 (PDT) From: Rayyan Ansari Date: Thu, 18 Jul 2024 16:20:34 +0100 Subject: [PATCH] dt-bindings: PCI: qcom,pcie-sc7280: specify eight interrupts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240718-sc7280-pcie-interrupts-v1-1-2047afa3b5b7@linaro.org> X-B4-Tracking: v=1; b=H4sIAMEymWYC/x2MSQqAMAwAvyI5W6h19yviQduoudSSVBHEv1s8D sPMA4JMKDBkDzBeJHT4BEWegd1nv6EilxiMNpVui06JbU2nVbCUlI/IfIYoqnFl1dTa9ctiIMW BcaX7H4/T+36IWQqbaAAAAA== To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rayyan Ansari X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2545; i=rayyan.ansari@linaro.org; h=from:subject:message-id; bh=70PitR19WRCz/nbwyJYX2RKRkC4CGZpC/tvMtuCqIzk=; b=kA0DAAoWRqjRjlvEnYQByyZiAGaZMvOilltO35hsk32BjSn/bQSBoOL3hklYHPTkqSH6OZOU0 Yh1BAAWCgAdFiEEw4L0rOu3QhLUt3rKRqjRjlvEnYQFAmaZMvMACgkQRqjRjlvEnYTQowEAkHG5 GQLMNa0dS5EBYhjR6nwpefGqYsUe6v1UG2h6n/kBAI0GQ9b/NjWHm9AJwN8IcVxJBNcHrZumTEy tsLE6Ds0F X-Developer-Key: i=rayyan.ansari@linaro.org; a=openpgp; fpr=C382F4ACEBB74212D4B77ACA46A8D18E5BC49D84 In the previous commit to this binding, commit 756485bfbb85 ("dt-bindings: PCI: qcom,pcie-sc7280: Move SC7280 to de= dicated schema") the binding was changed to specify one interrupt, as the device tree at that moment in time did not describe the hardware fully. The device tree for sc7280 now specifies eight interrupts, due to commit b8ba66b40da3 ("arm64: dts: qcom: sc7280: Add additional MSI interrup= ts") As a result, change the bindings to reflect this. Signed-off-by: Rayyan Ansari Reviewed-by: Krzysztof Kozlowski Reviewed-by: Manivannan Sadhasivam --- .../devicetree/bindings/pci/qcom,pcie-sc7280.yaml | 24 ++++++++++++++++++= ---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml b/= Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml index 634da24ec3ed..5cf1f9165301 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml @@ -53,11 +53,19 @@ properties: - const: aggre1 # Aggre NoC PCIe1 AXI clock =20 interrupts: - maxItems: 1 + minItems: 8 + maxItems: 8 =20 interrupt-names: items: - - const: msi + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 =20 resets: maxItems: 1 @@ -137,8 +145,16 @@ examples: =20 dma-coherent; =20 - interrupts =3D ; - interrupt-names =3D "msi"; + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; #interrupt-cells =3D <1>; interrupt-map-mask =3D <0 0 0 0x7>; interrupt-map =3D <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH= >, --- base-commit: 73399b58e5e5a1b28a04baf42e321cfcfc663c2f change-id: 20240718-sc7280-pcie-interrupts-6d34650d9bb2 Best regards, --=20 Rayyan Ansari