From nobody Thu Dec 18 08:27:24 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75D5F20B0F; Wed, 17 Jul 2024 07:50:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721202628; cv=none; b=EM0bQVZpmBEQL2cCOYs+SOCO78HOcVKCFnJFwn30Va1ssF6OLQVajrXmTFBZXSAtIjeSRBY1bqUKZxcr87GPNDnLDrin5/nMTeNVIjv0J/bvzsRTk7flIjKlFG+GLhKXXxQNMC8cSUbXGMAHZBJjffwc1n4vrH5E1dQUFX+lt90= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721202628; c=relaxed/simple; bh=QgeNMP59ZJp2VsYUt26F0DEFpOxpr1YaaHlDBa9gCV4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pxec5sURRdg6w+85nHbT5t1hEHmUrAgIn9un46y0FynE2adBR8MOblpl0fElHyR3IkbImHifD0dOKIkoKu6gT9CKlmxl07vk52Cq7UeK+k812NWQp+NeP0fHjgvF1o4VMjCbOQtoRPXJCKRu0SZsBJvActGTBbdcWTb6GONZ+8o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=7aW+kwkq; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="7aW+kwkq" Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 46H5e15k010567; Wed, 17 Jul 2024 09:49:37 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= /wDzLMJfs3d0OO8qkL/AMn3f2Lm5+yPbKI78+MtQ96w=; b=7aW+kwkq+b4dF2Cs BSl2TJzJlgULsgzBc73ccKSf9OkeXSSTiz/MhEZcxYDdM1DlFl7zuaqIw+IMWEEY kQCQI7uEGBpVmN7gFPlDDxSaca7OXQwfQlYEM+WfE59nyCx2lB0yAkJ0NLYQtDER GWT2Nu3B+CiKKyRX9N0sBeYc/wKNXbCqPvNlpWkJcfGg9wciAw3RC/1Duq8ndihP Cd/e7+7T9ghOBXdfSm1H8UN6QxhpynnhnZ4k4Hyha/1i+1FUWomR5G7qsqoATpVn 1Fbh+TNeWyt4TSEDT7chKS6m5Nyt7RHiGseXigo7qU9z2q6cyVHf+EOrKwNF7Abs igN83w== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 40dwfh26at-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 17 Jul 2024 09:49:37 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 9B94B40045; Wed, 17 Jul 2024 09:49:32 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id EDF2B24148A; Wed, 17 Jul 2024 09:48:54 +0200 (CEST) Received: from localhost (10.48.86.111) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Wed, 17 Jul 2024 09:48:54 +0200 From: Valentin Caron To: Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Torgue CC: , , , , , Amelie Delaunay , Valentin Caron Subject: [PATCH v2 1/4] dt-bindings: rtc: stm32: describe pinmux nodes Date: Wed, 17 Jul 2024 09:48:32 +0200 Message-ID: <20240717074835.2210411-2-valentin.caron@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240717074835.2210411-1-valentin.caron@foss.st.com> References: <20240717074835.2210411-1-valentin.caron@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-17_04,2024-07-16_02,2024-05-17_01 Content-Type: text/plain; charset="utf-8" STM32 RTC is capable to handle 3 specific pins of the soc (out1, out2, out2_rmp) and to outputs 2 signals (LSCO, alarm-a). This feature is configured thanks to pinmux nodes and pinctrl framework. This feature is available with compatible st,stm32mp1-rtc and st,stm32mp25-rtc only. Signed-off-by: Valentin Caron --- .../devicetree/bindings/rtc/st,stm32-rtc.yaml | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml b/Docu= mentation/devicetree/bindings/rtc/st,stm32-rtc.yaml index 7a0fab721cf1..aae06e570c22 100644 --- a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml @@ -53,6 +53,28 @@ properties: override default rtc_ck parent clock phandle of the new parent clock= of rtc_ck maxItems: 1 =20 +patternProperties: + "^rtc-[a-z]+-[0-9]+$": + type: object + $ref: /schemas/pinctrl/pinmux-node.yaml + description: | + Configuration of STM32 RTC pins description. STM32 RTC is able to ou= tput + some signals on specific pins: + - LSCO (Low Speed Clock Output) that allow to output LSE clock on a = pin. + - Alarm out that allow to send a pulse on a pin when alarm A of the = RTC + expires. + additionalProperties: false + properties: + function: + enum: + - lsco + - alarm-a + pins: + enum: + - out1 + - out2 + - out2_rmp + allOf: - if: properties: @@ -68,6 +90,9 @@ allOf: =20 clock-names: false =20 + patternProperties: + "^rtc-[a-z]+-[0-9]+$": false + required: - st,syscfg =20 @@ -83,6 +108,9 @@ allOf: minItems: 2 maxItems: 2 =20 + patternProperties: + "^rtc-[a-z]+-[0-9]+$": false + required: - clock-names - st,syscfg --=20 2.25.1 From nobody Thu Dec 18 08:27:24 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8D6B224E8; Wed, 17 Jul 2024 07:50:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 17 Jul 2024 09:49:37 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 560F140047; Wed, 17 Jul 2024 09:49:33 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id AB06F24148B; Wed, 17 Jul 2024 09:48:55 +0200 (CEST) Received: from localhost (10.48.86.111) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Wed, 17 Jul 2024 09:48:55 +0200 From: Valentin Caron To: Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Torgue CC: , , , , , Amelie Delaunay , Valentin Caron Subject: [PATCH v2 2/4] rtc: stm32: add pinctrl and pinmux interfaces Date: Wed, 17 Jul 2024 09:48:33 +0200 Message-ID: <20240717074835.2210411-3-valentin.caron@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240717074835.2210411-1-valentin.caron@foss.st.com> References: <20240717074835.2210411-1-valentin.caron@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-17_04,2024-07-16_02,2024-05-17_01 Content-Type: text/plain; charset="utf-8" STM32 RTC is capable to handle 3 specific pins of the soc. "out1, out2 and out2_rmp". To handle this, we use pinctrl framework. There is a single pin per group. Signed-off-by: Valentin Caron --- drivers/rtc/Kconfig | 2 + drivers/rtc/rtc-stm32.c | 120 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 122 insertions(+) diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 2a95b05982ad..9c88eb580209 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1922,6 +1922,8 @@ config RTC_DRV_R7301 config RTC_DRV_STM32 tristate "STM32 RTC" select REGMAP_MMIO + select PINMUX + select GENERIC_PINCONF depends on ARCH_STM32 || COMPILE_TEST help If you say yes here you get support for the STM32 On-Chip diff --git a/drivers/rtc/rtc-stm32.c b/drivers/rtc/rtc-stm32.c index 98b07969609d..6dfd9dc07e2e 100644 --- a/drivers/rtc/rtc-stm32.c +++ b/drivers/rtc/rtc-stm32.c @@ -13,6 +13,9 @@ #include #include #include +#include +#include +#include #include #include #include @@ -107,6 +110,14 @@ /* STM32 RTC driver time helpers */ #define SEC_PER_DAY (24 * 60 * 60) =20 +/* STM32 RTC pinctrl helpers */ +#define STM32_RTC_PINMUX(_name, _action, ...) { \ + .name =3D (_name), \ + .action =3D (_action), \ + .groups =3D ((const char *[]){ __VA_ARGS__ }), \ + .num_groups =3D ARRAY_SIZE(((const char *[]){ __VA_ARGS__ })), \ +} + struct stm32_rtc; =20 struct stm32_rtc_registers { @@ -171,6 +182,106 @@ static void stm32_rtc_wpr_lock(struct stm32_rtc *rtc) writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + regs->wpr); } =20 +enum stm32_rtc_pin_name { + NONE, + OUT1, + OUT2, + OUT2_RMP +}; + +static const struct pinctrl_pin_desc stm32_rtc_pinctrl_pins[] =3D { + PINCTRL_PIN(OUT1, "out1"), + PINCTRL_PIN(OUT2, "out2"), + PINCTRL_PIN(OUT2_RMP, "out2_rmp"), +}; + +static int stm32_rtc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(stm32_rtc_pinctrl_pins); +} + +static const char *stm32_rtc_pinctrl_get_group_name(struct pinctrl_dev *pc= tldev, + unsigned int selector) +{ + return stm32_rtc_pinctrl_pins[selector].name; +} + +static int stm32_rtc_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + *pins =3D &stm32_rtc_pinctrl_pins[selector].number; + *num_pins =3D 1; + return 0; +} + +static const struct pinctrl_ops stm32_rtc_pinctrl_ops =3D { + .dt_node_to_map =3D pinconf_generic_dt_node_to_map_all, + .dt_free_map =3D pinconf_generic_dt_free_map, + .get_groups_count =3D stm32_rtc_pinctrl_get_groups_count, + .get_group_name =3D stm32_rtc_pinctrl_get_group_name, + .get_group_pins =3D stm32_rtc_pinctrl_get_group_pins, +}; + +struct stm32_rtc_pinmux_func { + const char *name; + const char * const *groups; + const unsigned int num_groups; + int (*action)(struct pinctrl_dev *pctl_dev, unsigned int pin); +}; + +static const struct stm32_rtc_pinmux_func stm32_rtc_pinmux_functions[] =3D= { +}; + +static int stm32_rtc_pinmux_get_functions_count(struct pinctrl_dev *pctlde= v) +{ + return ARRAY_SIZE(stm32_rtc_pinmux_functions); +} + +static const char *stm32_rtc_pinmux_get_fname(struct pinctrl_dev *pctldev,= unsigned int selector) +{ + return stm32_rtc_pinmux_functions[selector].name; +} + +static int stm32_rtc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsign= ed int selector, + const char * const **groups, unsigned int * const num_groups) +{ + *groups =3D stm32_rtc_pinmux_functions[selector].groups; + *num_groups =3D stm32_rtc_pinmux_functions[selector].num_groups; + return 0; +} + +static int stm32_rtc_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned = int selector, + unsigned int group) +{ + struct stm32_rtc_pinmux_func selected_func =3D stm32_rtc_pinmux_functions= [selector]; + struct pinctrl_pin_desc pin =3D stm32_rtc_pinctrl_pins[group]; + + /* Call action */ + if (selected_func.action) + return selected_func.action(pctldev, pin.number); + + return -EINVAL; +} + +static const struct pinmux_ops stm32_rtc_pinmux_ops =3D { + .get_functions_count =3D stm32_rtc_pinmux_get_functions_count, + .get_function_name =3D stm32_rtc_pinmux_get_fname, + .get_function_groups =3D stm32_rtc_pinmux_get_groups, + .set_mux =3D stm32_rtc_pinmux_set_mux, + .strict =3D true, +}; + +static struct pinctrl_desc stm32_rtc_pdesc =3D { + .name =3D DRIVER_NAME, + .pins =3D stm32_rtc_pinctrl_pins, + .npins =3D ARRAY_SIZE(stm32_rtc_pinctrl_pins), + .owner =3D THIS_MODULE, + .pctlops =3D &stm32_rtc_pinctrl_ops, + .pmxops =3D &stm32_rtc_pinmux_ops, +}; + static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc) { const struct stm32_rtc_registers *regs =3D &rtc->data->regs; @@ -791,6 +902,7 @@ static int stm32_rtc_probe(struct platform_device *pdev) { struct stm32_rtc *rtc; const struct stm32_rtc_registers *regs; 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charset="utf-8" RTC is able to output on a pin the "LSE" internal clock. STM32 RTC is now registered as a clock provider. It provides rtc_lsco clock, that means RTC_LSCO is output on either RTC_OUT1 or RTC_OUT2_RMP, depending on pinmux DT property. The clock is marked as CLK_IGNORE_UNUSED and CLK_IS_CRITICAL because RTC_LSCO can be early required by devices needed it to init. Add LSCO in pinmux functions. Add "stm32_rtc_clean_outs" to disable LSCO. As RTC is part of "backup" power domain, it is not reset during shutdown or reboot. So force LSCO disable at probe. Co-developed-by: Amelie Delaunay Signed-off-by: Amelie Delaunay Signed-off-by: Valentin Caron --- drivers/rtc/Kconfig | 1 + drivers/rtc/rtc-stm32.c | 101 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 102 insertions(+) diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 9c88eb580209..52f5f9ec7e9f 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1924,6 +1924,7 @@ config RTC_DRV_STM32 select REGMAP_MMIO select PINMUX select GENERIC_PINCONF + select COMMON_CLK depends on ARCH_STM32 || COMPILE_TEST help If you say yes here you get support for the STM32 On-Chip diff --git a/drivers/rtc/rtc-stm32.c b/drivers/rtc/rtc-stm32.c index 6dfd9dc07e2e..675860a13051 100644 --- a/drivers/rtc/rtc-stm32.c +++ b/drivers/rtc/rtc-stm32.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -45,6 +46,10 @@ #define STM32_RTC_CR_FMT BIT(6) #define STM32_RTC_CR_ALRAE BIT(8) #define STM32_RTC_CR_ALRAIE BIT(12) +#define STM32_RTC_CR_OSEL GENMASK(22, 21) +#define STM32_RTC_CR_COE BIT(23) +#define STM32_RTC_CR_TAMPOE BIT(26) +#define STM32_RTC_CR_OUT2EN BIT(31) =20 /* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */ #define STM32_RTC_ISR_ALRAWF BIT(0) @@ -81,6 +86,12 @@ /* STM32_RTC_SR/_SCR bit fields */ #define STM32_RTC_SR_ALRA BIT(0) =20 +/* STM32_RTC_CFGR bit fields */ +#define STM32_RTC_CFGR_OUT2_RMP BIT(0) +#define STM32_RTC_CFGR_LSCOEN GENMASK(2, 1) +#define STM32_RTC_CFGR_LSCOEN_OUT1 1 +#define STM32_RTC_CFGR_LSCOEN_OUT2_RMP 2 + /* STM32_RTC_VERR bit fields */ #define STM32_RTC_VERR_MINREV_SHIFT 0 #define STM32_RTC_VERR_MINREV GENMASK(3, 0) @@ -130,6 +141,7 @@ struct stm32_rtc_registers { u16 wpr; u16 sr; u16 scr; + u16 cfgr; u16 verr; }; =20 @@ -145,6 +157,7 @@ struct stm32_rtc_data { bool need_dbp; bool need_accuracy; bool rif_protected; + bool has_lsco; }; =20 struct stm32_rtc { @@ -157,6 +170,7 @@ struct stm32_rtc { struct clk *rtc_ck; const struct stm32_rtc_data *data; int irq_alarm; + struct clk *clk_lsco; }; =20 struct stm32_rtc_rif_resource { @@ -231,7 +245,68 @@ struct stm32_rtc_pinmux_func { int (*action)(struct pinctrl_dev *pctl_dev, unsigned int pin); }; =20 +static int stm32_rtc_pinmux_lsco_available(struct pinctrl_dev *pctldev, un= signed int pin) +{ + struct stm32_rtc *rtc =3D pinctrl_dev_get_drvdata(pctldev); + struct stm32_rtc_registers regs =3D rtc->data->regs; + unsigned int cr =3D readl_relaxed(rtc->base + regs.cr); + unsigned int cfgr =3D readl_relaxed(rtc->base + regs.cfgr); + unsigned int calib =3D STM32_RTC_CR_COE; + unsigned int tampalrm =3D STM32_RTC_CR_TAMPOE | STM32_RTC_CR_OSEL; + + switch (pin) { + case OUT1: + if ((!(cr & STM32_RTC_CR_OUT2EN) && + ((cr & calib) || cr & tampalrm)) || + ((cr & calib) && (cr & tampalrm))) + return -EBUSY; + break; + case OUT2_RMP: + if ((cr & STM32_RTC_CR_OUT2EN) && + (cfgr & STM32_RTC_CFGR_OUT2_RMP) && + ((cr & calib) || (cr & tampalrm))) + return -EBUSY; + break; + default: + return -EINVAL; + } + + if (clk_get_rate(rtc->rtc_ck) !=3D 32768) + return -ERANGE; + + return 0; +} + +static int stm32_rtc_pinmux_action_lsco(struct pinctrl_dev *pctldev, unsig= ned int pin) +{ + struct stm32_rtc *rtc =3D pinctrl_dev_get_drvdata(pctldev); + struct stm32_rtc_registers regs =3D rtc->data->regs; + struct device *dev =3D rtc->rtc_dev->dev.parent; + u8 lscoen; + int ret; + + if (!rtc->data->has_lsco) + return -EPERM; + + ret =3D stm32_rtc_pinmux_lsco_available(pctldev, pin); + if (ret) + return ret; + + lscoen =3D (pin =3D=3D OUT1) ? STM32_RTC_CFGR_LSCOEN_OUT1 : STM32_RTC_CFG= R_LSCOEN_OUT2_RMP; + + rtc->clk_lsco =3D clk_register_gate(dev, "rtc_lsco", __clk_get_name(rtc->= rtc_ck), + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, + rtc->base + regs.cfgr, lscoen, 0, NULL); + if (IS_ERR(rtc->clk_lsco)) + return PTR_ERR(rtc->clk_lsco); + + of_clk_add_provider(dev->of_node, of_clk_src_simple_get, rtc->clk_lsco); + + return 0; +} + static const struct stm32_rtc_pinmux_func stm32_rtc_pinmux_functions[] =3D= { + STM32_RTC_PINMUX("lsco", &stm32_rtc_pinmux_action_lsco, "out1", "out2_rmp= "), }; =20 static int stm32_rtc_pinmux_get_functions_count(struct pinctrl_dev *pctlde= v) @@ -687,6 +762,7 @@ static const struct stm32_rtc_data stm32_rtc_data =3D { .need_dbp =3D true, .need_accuracy =3D false, .rif_protected =3D false, + .has_lsco =3D false, .regs =3D { .tr =3D 0x00, .dr =3D 0x04, @@ -697,6 +773,7 @@ static const struct stm32_rtc_data stm32_rtc_data =3D { .wpr =3D 0x24, .sr =3D 0x0C, /* set to ISR offset to ease alarm management */ .scr =3D UNDEF_REG, + .cfgr =3D UNDEF_REG, .verr =3D UNDEF_REG, }, .events =3D { @@ -710,6 +787,7 @@ static const struct stm32_rtc_data stm32h7_rtc_data =3D= { .need_dbp =3D true, .need_accuracy =3D false, .rif_protected =3D false, + .has_lsco =3D false, .regs =3D { .tr =3D 0x00, .dr =3D 0x04, @@ -720,6 +798,7 @@ static const struct stm32_rtc_data stm32h7_rtc_data =3D= { .wpr =3D 0x24, .sr =3D 0x0C, /* set to ISR offset to ease alarm management */ .scr =3D UNDEF_REG, + .cfgr =3D UNDEF_REG, .verr =3D UNDEF_REG, }, .events =3D { @@ -742,6 +821,7 @@ static const struct stm32_rtc_data stm32mp1_data =3D { .need_dbp =3D false, .need_accuracy =3D true, .rif_protected =3D false, + .has_lsco =3D true, .regs =3D { .tr =3D 0x00, .dr =3D 0x04, @@ -752,6 +832,7 @@ static const struct stm32_rtc_data stm32mp1_data =3D { .wpr =3D 0x24, .sr =3D 0x50, .scr =3D 0x5C, + .cfgr =3D 0x60, .verr =3D 0x3F4, }, .events =3D { @@ -765,6 +846,7 @@ static const struct stm32_rtc_data stm32mp25_data =3D { .need_dbp =3D false, .need_accuracy =3D true, .rif_protected =3D true, + .has_lsco =3D true, .regs =3D { .tr =3D 0x00, .dr =3D 0x04, @@ -775,6 +857,7 @@ static const struct stm32_rtc_data stm32mp25_data =3D { .wpr =3D 0x24, .sr =3D 0x50, .scr =3D 0x5C, + .cfgr =3D 0x60, .verr =3D 0x3F4, }, .events =3D { @@ -792,6 +875,19 @@ static const struct of_device_id stm32_rtc_of_match[] = =3D { }; MODULE_DEVICE_TABLE(of, stm32_rtc_of_match); =20 +static void stm32_rtc_clean_outs(struct stm32_rtc *rtc) +{ + struct stm32_rtc_registers regs =3D rtc->data->regs; + + if (regs.cfgr !=3D UNDEF_REG) { + unsigned int cfgr =3D readl_relaxed(rtc->base + regs.cfgr); + + cfgr &=3D ~STM32_RTC_CFGR_LSCOEN; + cfgr &=3D ~STM32_RTC_CFGR_OUT2_RMP; + writel_relaxed(cfgr, rtc->base + regs.cfgr); + } +} + static int stm32_rtc_check_rif(struct stm32_rtc *stm32_rtc, struct stm32_rtc_rif_resource res) { @@ -1024,6 +1120,8 @@ static int stm32_rtc_probe(struct platform_device *pd= ev) goto err; } =20 + stm32_rtc_clean_outs(rtc); + ret =3D devm_pinctrl_register_and_init(&pdev->dev, &stm32_rtc_pdesc, rtc,= &pctl); if (ret) return dev_err_probe(&pdev->dev, ret, "pinctrl register failed"); @@ -1070,6 +1168,9 @@ static void stm32_rtc_remove(struct platform_device *= pdev) const struct stm32_rtc_registers *regs =3D &rtc->data->regs; unsigned int cr; =20 + if (!IS_ERR_OR_NULL(rtc->clk_lsco)) + clk_unregister_gate(rtc->clk_lsco); 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charset="utf-8" STM32 RTC can pulse some SOC pins when an RTC alarm expires. This patch adds this functionality for alarm A. The pulse can out on three pins RTC_OUT1, RTC_OUT2, RTC_OUT2_RMP (PC13, PB2, PI8 on stm32mp15) (PC13, PB2, PI1 on stm32mp13) (PC13, PF4/PF6, PI8 on stm32mp25). This patch only adds the functionality for devices which are using st,stm32mp1-rtc and st,stm32mp25-rtc compatible. Add "alarm-a" in pinmux functions. Signed-off-by: Valentin Caron --- drivers/rtc/rtc-stm32.c | 60 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/drivers/rtc/rtc-stm32.c b/drivers/rtc/rtc-stm32.c index 675860a13051..3e4f2ee22b0b 100644 --- a/drivers/rtc/rtc-stm32.c +++ b/drivers/rtc/rtc-stm32.c @@ -47,8 +47,10 @@ #define STM32_RTC_CR_ALRAE BIT(8) #define STM32_RTC_CR_ALRAIE BIT(12) #define STM32_RTC_CR_OSEL GENMASK(22, 21) +#define STM32_RTC_CR_OSEL_ALARM_A FIELD_PREP(STM32_RTC_CR_OSEL, 0x01) #define STM32_RTC_CR_COE BIT(23) #define STM32_RTC_CR_TAMPOE BIT(26) +#define STM32_RTC_CR_TAMPALRM_TYPE BIT(30) #define STM32_RTC_CR_OUT2EN BIT(31) =20 /* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */ @@ -158,6 +160,7 @@ struct stm32_rtc_data { bool need_accuracy; bool rif_protected; bool has_lsco; + bool has_alarm_out; }; =20 struct stm32_rtc { @@ -245,6 +248,47 @@ struct stm32_rtc_pinmux_func { int (*action)(struct pinctrl_dev *pctl_dev, unsigned int pin); }; =20 +static int stm32_rtc_pinmux_action_alarm(struct pinctrl_dev *pctldev, unsi= gned int pin) +{ + struct stm32_rtc *rtc =3D pinctrl_dev_get_drvdata(pctldev); + struct stm32_rtc_registers regs =3D rtc->data->regs; + unsigned int cr =3D readl_relaxed(rtc->base + regs.cr); + unsigned int cfgr =3D readl_relaxed(rtc->base + regs.cfgr); + + if (!rtc->data->has_alarm_out) + return -EPERM; + + cr &=3D ~STM32_RTC_CR_OSEL; + cr |=3D STM32_RTC_CR_OSEL_ALARM_A; + cr &=3D ~STM32_RTC_CR_TAMPOE; + cr &=3D ~STM32_RTC_CR_COE; + cr &=3D ~STM32_RTC_CR_TAMPALRM_TYPE; + + switch (pin) { + case OUT1: + cr &=3D ~STM32_RTC_CR_OUT2EN; + cfgr &=3D ~STM32_RTC_CFGR_OUT2_RMP; + break; + case OUT2: + cr |=3D STM32_RTC_CR_OUT2EN; + cfgr &=3D ~STM32_RTC_CFGR_OUT2_RMP; + break; + case OUT2_RMP: + cr |=3D STM32_RTC_CR_OUT2EN; + cfgr |=3D STM32_RTC_CFGR_OUT2_RMP; + break; + default: + return -EINVAL; + } + + stm32_rtc_wpr_unlock(rtc); + writel_relaxed(cr, rtc->base + regs.cr); + writel_relaxed(cfgr, rtc->base + regs.cfgr); + stm32_rtc_wpr_lock(rtc); + + return 0; +} + static int stm32_rtc_pinmux_lsco_available(struct pinctrl_dev *pctldev, un= signed int pin) { struct stm32_rtc *rtc =3D pinctrl_dev_get_drvdata(pctldev); @@ -307,6 +351,7 @@ static int stm32_rtc_pinmux_action_lsco(struct pinctrl_= dev *pctldev, unsigned in =20 static const struct stm32_rtc_pinmux_func stm32_rtc_pinmux_functions[] =3D= { STM32_RTC_PINMUX("lsco", &stm32_rtc_pinmux_action_lsco, "out1", "out2_rmp= "), + STM32_RTC_PINMUX("alarm-a", &stm32_rtc_pinmux_action_alarm, "out1", "out2= ", "out2_rmp"), }; =20 static int stm32_rtc_pinmux_get_functions_count(struct pinctrl_dev *pctlde= v) @@ -763,6 +808,7 @@ static const struct stm32_rtc_data stm32_rtc_data =3D { .need_accuracy =3D false, .rif_protected =3D false, .has_lsco =3D false, + .has_alarm_out =3D false, .regs =3D { .tr =3D 0x00, .dr =3D 0x04, @@ -788,6 +834,7 @@ static const struct stm32_rtc_data stm32h7_rtc_data =3D= { .need_accuracy =3D false, .rif_protected =3D false, .has_lsco =3D false, + .has_alarm_out =3D false, .regs =3D { .tr =3D 0x00, .dr =3D 0x04, @@ -822,6 +869,7 @@ static const struct stm32_rtc_data stm32mp1_data =3D { .need_accuracy =3D true, .rif_protected =3D false, .has_lsco =3D true, + .has_alarm_out =3D true, .regs =3D { .tr =3D 0x00, .dr =3D 0x04, @@ -847,6 +895,7 @@ static const struct stm32_rtc_data stm32mp25_data =3D { .need_accuracy =3D true, .rif_protected =3D true, .has_lsco =3D true, + .has_alarm_out =3D true, .regs =3D { .tr =3D 0x00, .dr =3D 0x04, @@ -878,6 +927,17 @@ MODULE_DEVICE_TABLE(of, stm32_rtc_of_match); static void stm32_rtc_clean_outs(struct stm32_rtc *rtc) { struct stm32_rtc_registers regs =3D rtc->data->regs; + unsigned int cr =3D readl_relaxed(rtc->base + regs.cr); + + cr &=3D ~STM32_RTC_CR_OSEL; + cr &=3D ~STM32_RTC_CR_TAMPOE; + cr &=3D ~STM32_RTC_CR_COE; + cr &=3D ~STM32_RTC_CR_TAMPALRM_TYPE; + cr &=3D ~STM32_RTC_CR_OUT2EN; + + stm32_rtc_wpr_unlock(rtc); + writel_relaxed(cr, rtc->base + regs.cr); + stm32_rtc_wpr_lock(rtc); =20 if (regs.cfgr !=3D UNDEF_REG) { unsigned int cfgr =3D readl_relaxed(rtc->base + regs.cfgr); --=20 2.25.1