From nobody Thu Dec 18 12:17:01 2025 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B871181CE0; Wed, 17 Jul 2024 16:47:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721234835; cv=none; b=Am6otuf7qQCxF2jrv6+HSYY/Mh5MJW9NOEmXMBKAqKw0u5TpN5aLwEsbzEF5NPG2axV14UDwA8u2veJoniV5YjQMt/Et2OGga50PTckfHXl92wZnpaZvea/AukpK2E+7AfkM8XP6s1v88OtLmlKsn3Buj9FWn6l7ZBzqx7sC0ls= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721234835; c=relaxed/simple; bh=k9q0V9TcOQIA1PbY90EhLUeU/WhgnoateJ2JCPh/1u4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KStpHhPbutemS14m93JNMo3JyJH3U1SfdOZ0B381b7NFoRtYQ4f2Dj7F1KKLnwilVkWsQoZ/MYZTPXm0k4fvb2gNH2VrlwopOfLLGwOGn+95B0JWq2NwCuzVWu0SwEWZc7oSXeXJreWB3WkhRdswHER2Z9PX1YCbrBEwt5GF1yM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=zJGWl85i; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="zJGWl85i" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1721234829; bh=k9q0V9TcOQIA1PbY90EhLUeU/WhgnoateJ2JCPh/1u4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=zJGWl85iKQ0TazdnXhopSNq0QA29dN0TLmeIcoVb1SSX4oKQYzpqk2/WDbpaC3bRO 53EjQqa9bgvXFHkmfPHhU3tS4LsJRcJjJogXH242aPI0rf1XKC8T7F59SarveOdmM1 rojrRHj54gDCg3ztnpUV0YEsvR4z2uAfQX0uviZ54GL8qX7YvG+S6xCd6VjiOVPwfr fU5iU0gzngHN/iBCNZyyK9gapCjdUapxPJq7N6uw5ub8olb9C84+sa36roMlzLj9BS 5GD1hZKUcgqzQe2ShPMfFZsnARirdirhRaTox98IUCRfeSPSSkcwJ8eNGPvf4lZ61P mpHYu+OLrcvpQ== Received: from [127.0.1.1] (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: obbardc) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 1C81937813C0; Wed, 17 Jul 2024 16:47:09 +0000 (UTC) From: Christopher Obbard Date: Wed, 17 Jul 2024 17:46:59 +0100 Subject: [PATCH v2 1/3] dt-bindings: arm: rockchip: Add Firefly Core-PX30-JD4 with baseboard Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240717-rockchip-px30-firefly-v2-1-06541a5a5946@collabora.com> References: <20240717-rockchip-px30-firefly-v2-0-06541a5a5946@collabora.com> In-Reply-To: <20240717-rockchip-px30-firefly-v2-0-06541a5a5946@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Kever Yang , Dragan Simic , Collabora Kernel Mailing List , Christopher Obbard X-Mailer: b4 0.13.0 Add binding for the Firefly Core-PX30-JD4 SoM when used in conjunction with the MB-JD4-RK3328 & PX30 baseboard. Signed-off-by: Christopher Obbard --- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 1ef09fbfdfaf5..33ca8028bc151 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -148,6 +148,12 @@ properties: - const: engicam,px30-core - const: rockchip,px30 =20 + - description: Firefly Core-PX30-JD4 with MB-JD4-PX30 baseboard + items: + - const: firefly,px30-mb-jd4 + - const: firefly,px30-core-jd4 + - const: rockchip,px30 + - description: Firefly Firefly-RK3288 items: - enum: --=20 2.45.2 From nobody Thu Dec 18 12:17:01 2025 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B7BA1E4B0; Wed, 17 Jul 2024 16:47:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721234835; cv=none; b=NCTQbm2G3Uponen4HD9T8lN/Wa5qkg/xBSrRNP9BeD6AytvkOPmLMoUKBb225HbHQFMP/y64rLAkpTipJ3JvZbrxGnpOJ0uQJCD7fCU4tzy+KcEPFonvVv7PaBO75HWPmM1s7u0deScsEZLfo8suIzBWz7GuKhkKSgfW1UQf7k0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721234835; c=relaxed/simple; bh=Xh5GR8VDy6JMx4VeUoNI9/vBtdUnYTt+fv/+4Xf2jhc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mKRlm9AM9L0yK44e6Y/sJ8JZw9y1Dkwnl3wiH+ZxjQoTlLwiZuWOYaxJdUzD1SAXHd5B4iqMg58tKK1E3W3GaojoW7OVe8FaCvM9xPj4dEPXPcK2+5FvrIu5Uiio41nnd3Wdjql7JrUiaWiyxQN+0U6PTKc2EKKLE+Ib6CWpGX8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=btG9vcmq; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="btG9vcmq" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1721234830; bh=Xh5GR8VDy6JMx4VeUoNI9/vBtdUnYTt+fv/+4Xf2jhc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=btG9vcmq9srT+6b3SJ8spS/vyAn3k5ccx5w7BPOPYVTXelROCnJvsmAAokp0uH/FQ FmPWjSt/2GmkUHSZzuPiQh7hpRUiSoAt7hlMS0QCakbqnmotwd90ZIUpIObji/j++7 WExgkO0mB/fdc4Jlnov9+/uYlgGxh3dCm91rdKS0RxIFLfP2N/1xFW61/MzQEF7OYO 3xK2pWMcC+cxEVKEkwsOfUTlj7OrftvjXFoed2dvC87R+6p2Jys5u+th8r5PXnwBJg olburWwXKmiHjKi+by1Ry5457EX3vLxy8wA8LTc+6aKY6GRS9qPmQXmNzS/P/TYMOe hIvv/ZfzcF9PQ== Received: from [127.0.1.1] (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: obbardc) by madrid.collaboradmins.com (Postfix) with ESMTPSA id D643D378202D; Wed, 17 Jul 2024 16:47:09 +0000 (UTC) From: Christopher Obbard Date: Wed, 17 Jul 2024 17:47:00 +0100 Subject: [PATCH v2 2/3] arm64: dts: rockchip: add Firefly Core-PX30-JD4 SoM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240717-rockchip-px30-firefly-v2-2-06541a5a5946@collabora.com> References: <20240717-rockchip-px30-firefly-v2-0-06541a5a5946@collabora.com> In-Reply-To: <20240717-rockchip-px30-firefly-v2-0-06541a5a5946@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Kever Yang , Dragan Simic , Collabora Kernel Mailing List , Christopher Obbard X-Mailer: b4 0.13.0 The Firefly Core-PX30-JD4 SoM is a 69.6x49.6mm (260 pin SODIMM connector) system-on-module from Firefly, featuring the Rockchip PX30. It provides the following feature set: * on-module DDR3 (1GB/2GB) * on-module eMMC 5.1 (8GB/16GB/32GB/64GB/128GB) * on-module NPU (optional) * SD card (on a baseboard) via edge connector * 100mbps Ethernet (on a baseboard) via edge connector * MIPI-DSI (on a baseboard) via edge connector * Audio (on a baseboard) via edge connector - 1x SPDIF - 1x 8-channel I2S/TDM - 1x 2-channel I2S/TDM - 1x 8-channel PDM * USB (on a baseboard) via edge connector - 1x USB 2.0 OTG - 1x USB 2.0 host * Various GPIO (on a baseboard) via edge connector Signed-off-by: Christopher Obbard --- .../boot/dts/rockchip/px30-firefly-jd4-core.dtsi | 322 +++++++++++++++++= ++++ 1 file changed, 322 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/px30-firefly-jd4-core.dtsi b/arch= /arm64/boot/dts/rockchip/px30-firefly-jd4-core.dtsi new file mode 100644 index 0000000000000..88d3d77cc0dbe --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-firefly-jd4-core.dtsi @@ -0,0 +1,322 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include +#include +#include "px30.dtsi" + +/ { + compatible =3D "firefly,px30-core-jd4", "rockchip,px30"; + + emmc_pwrseq: emmc-pwrseq { + compatible =3D "mmc-pwrseq-emmc"; + pinctrl-0 =3D <&emmc_reset>; + pinctrl-names =3D "default"; + reset-gpios =3D <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_baseboard>; + }; +}; + +&cpu0 { + cpu-supply =3D <&vdd_arm>; +}; + +&cpu1 { + cpu-supply =3D <&vdd_arm>; +}; + +&cpu2 { + cpu-supply =3D <&vdd_arm>; +}; + +&cpu3 { + cpu-supply =3D <&vdd_arm>; +}; + +&emmc { + bus-width =3D <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + mmc-pwrseq =3D <&emmc_pwrseq>; + vmmc-supply =3D <&vcc_3v0>; + vqmmc-supply =3D <&vccio_flash>; + status =3D "okay"; +}; + +&gpu { + mali-supply =3D <&vdd_log>; + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; + + rk809: pmic@20 { + compatible =3D "rockchip,rk809"; + reg =3D <0x20>; + interrupt-parent =3D <&gpio0>; + interrupts =3D <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells =3D <0>; + clock-output-names =3D "xin32k"; + + vcc1-supply =3D <&vcc5v0_sys>; + vcc2-supply =3D <&vcc5v0_sys>; + vcc3-supply =3D <&vcc5v0_sys>; + vcc4-supply =3D <&vcc5v0_sys>; + vcc5-supply =3D <&vcc3v3_sys>; + vcc6-supply =3D <&vcc3v3_sys>; + vcc7-supply =3D <&vcc3v3_sys>; + vcc8-supply =3D <&vcc3v3_sys>; + vcc9-supply =3D <&vcc5v0_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name =3D "vdd_log"; + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name =3D "vdd_arm"; + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name =3D "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0: vcc_rmii: DCDC_REG4 { + regulator-name =3D "vcc_3v0"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3000000>; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-name =3D "vcc3v3_sys"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-name =3D "vcc_1v0"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1000000>; + }; + }; + + vcc_1v8: vccio_flash: vccio_sdio: LDO_REG2 { + regulator-name =3D "vcc_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd_1v0: LDO_REG3 { + regulator-name =3D "vdd_1v0"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-name =3D "vcc3v0_pmu"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3000000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name =3D "vccio_sd"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-name =3D "vcc_sd"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-name =3D "vcc2v8_dvp"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-name =3D "vcc1v8_dvp"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcc1v5_dvp: LDO_REG9 { + regulator-name =3D "vcc1v5_dvp"; + regulator-min-microvolt =3D <1500000>; + regulator-max-microvolt =3D <1500000>; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <1500000>; + }; + }; + + vcc3v3_lcd: SWITCH_REG1 { + regulator-name =3D "vcc3v3_lcd"; + regulator-boot-on; + }; + + vcc5v0_host: SWITCH_REG2 { + regulator-name =3D "vcc5v0_host"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&io_domains { + status =3D "okay"; + + vccio1-supply =3D <&vccio_sdio>; + vccio2-supply =3D <&vccio_sd>; + vccio3-supply =3D <&vcc_3v0>; + vccio4-supply =3D <&vcc3v0_pmu>; + vccio5-supply =3D <&vcc_3v0>; + vccio6-supply =3D <&vccio_flash>; +}; + +&pinctrl { + emmc { + emmc_reset: emmc-reset { + rockchip,pins =3D <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins =3D + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + status =3D "okay"; + + pmuio1-supply =3D <&vcc3v0_pmu>; + pmuio2-supply =3D <&vcc3v0_pmu>; +}; + +&saradc { + vref-supply =3D <&vcc_1v8>; + status =3D "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode =3D <1>; + rockchip,hw-tshut-polarity =3D <1>; + status =3D "okay"; +}; --=20 2.45.2 From nobody Thu Dec 18 12:17:01 2025 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 987E5181CF2; Wed, 17 Jul 2024 16:47:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721234835; cv=none; b=YbkKJAF+k5qHv4EDOzhOegfLP1IlVQ6dLZGCEi6sO7dLnEEgOoQSg10bnPV04seiBpNXn1Hy7J3ujmSMYFR4jPkWO0oGf+2emyF42OQIN/xNBeH0WozOfwTl4DiUcKfLEkAbhvwB7fTyy+msUSLrhetAVRXPAPttoMu/RmlLnQ4= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240717-rockchip-px30-firefly-v2-3-06541a5a5946@collabora.com> References: <20240717-rockchip-px30-firefly-v2-0-06541a5a5946@collabora.com> In-Reply-To: <20240717-rockchip-px30-firefly-v2-0-06541a5a5946@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Kever Yang , Dragan Simic , Collabora Kernel Mailing List , Christopher Obbard X-Mailer: b4 0.13.0 The Firefly MB-PX30-JD4 is a baseboard for the Core-PX30-JD4 SoM. Signed-off-by: Christopher Obbard --- arch/arm64/boot/dts/rockchip/Makefile | 1 + arch/arm64/boot/dts/rockchip/px30-firefly-jd4.dts | 178 ++++++++++++++++++= ++++ 2 files changed, 179 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index fda1b980eb4bc..24e1e5b606876 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-engicam-px30-core-ctouch2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-engicam-px30-core-ctouch2-of10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-engicam-px30-core-edimm2.2.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-firefly-jd4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-ringneck-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3308-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3308-roc-cc.dtb diff --git a/arch/arm64/boot/dts/rockchip/px30-firefly-jd4.dts b/arch/arm64= /boot/dts/rockchip/px30-firefly-jd4.dts new file mode 100644 index 0000000000000..bb79a7eb9f028 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-firefly-jd4.dts @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include +#include +#include "px30-firefly-jd4-core.dtsi" + +/ { + model =3D "Firefly Core-PX30-JD4 with MB-JD4-PX30 baseboard"; + compatible =3D "firefly,px30-mb-jd4", "firefly,px30-core-jd4", "rockchip,= px30"; + + aliases { + ethernet0 =3D &gmac; + mmc0 =3D &sdmmc; + mmc1 =3D &sdio; + mmc2 =3D &emmc; + }; + + chosen { + stdout-path =3D "serial2:115200n8"; + }; + + dc_12v: dc-12v-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + adc-keys { + compatible =3D "adc-keys"; + io-channels =3D <&saradc 2>; + io-channel-names =3D "buttons"; + keyup-threshold-microvolt =3D <1500000>; + poll-interval =3D <100>; + + button-recovery { + label =3D "Recovery"; + linux,code =3D ; + press-threshold-microvolt =3D <18000>; + }; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&blue_led>, <&green_led>; + + blue-led { + color =3D ; + default-state =3D "on"; + function =3D LED_FUNCTION_HEARTBEAT; + gpios =3D <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + label =3D "px30-mb-jd4:blue:work"; + linux,default-trigger =3D "heartbeat"; + }; + + green-led { + color =3D ; + default-state =3D "on"; + function =3D LED_FUNCTION_POWER; + gpios =3D <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + label =3D "px30-mb-jd4:blue:diy"; + linux,default-trigger =3D "default-on"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios =3D <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ + }; + + vcc5v0_baseboard: vcc5v0-baseboard-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_baseboard"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&dc_12v>; + }; +}; + +&gmac { + clock_in_out =3D "output"; + phy-supply =3D <&vcc_rmii>; + snps,reset-gpio =3D <&gpio2 13 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us =3D <0 50000 50000>; + status =3D "okay"; +}; + +&pinctrl { + leds { + blue_led: blue-led { + rockchip,pins =3D <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + green_led: green-led { + rockchip,pins =3D <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins =3D + <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width =3D <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay =3D <800>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc_sd>; + vqmmc-supply =3D <&vccio_sd>; + status =3D "okay"; +}; + +&sdio { + bus-width =3D <4>; + cap-sd-highspeed; + keep-power-in-suspend; + non-removable; + mmc-pwrseq =3D <&sdio_pwrseq>; + sd-uhs-sdr104; + status =3D "okay"; +}; + +&u2phy { + status =3D "okay"; + + u2phy_host: host-port { + status =3D "okay"; + }; + + u2phy_otg: otg-port { + status =3D "okay"; + }; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart2m1_xfer>; + status =3D "okay"; +}; + +&usb20_otg { + status =3D "okay"; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; --=20 2.45.2