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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240717-dispcc-sm8550-fixes-v2-1-5c4a3128c40b@linaro.org> References: <20240717-dispcc-sm8550-fixes-v2-0-5c4a3128c40b@linaro.org> In-Reply-To: <20240717-dispcc-sm8550-fixes-v2-0-5c4a3128c40b@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Neil Armstrong , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1411; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=R7ejJV5ehRe2QOtosJ5fq8CEVBDmVLRLrq5b9Ilcn4o=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBml5ctpaOu3O44R8JnE0xsEJUtcOhq1jLo0Nu69 nIeG/aQsdyJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZpeXLQAKCRCLPIo+Aiko 1dsRCACctM+cJQjzz66Im/WucEYM99McFLX6C8woUaCDnORV7jQl4+MF89/qaZTs306K71TP2NF okcP3J9ouOfhDaOjvfswXnjj6GJAyucRWrZV1TN6QU69WIm5uVmlxbS3n8HAl1x/wQDgwas5jy7 8y/kEpoTgmGR93rk1QY0Lv8QfRuKLTU1eGJfM4R+w7TdYN2IJvf0CltEhFPNsJIiuq+Z25dqpXC fF0G9aresrDwhhcNsgXKq3zmBXXgzy/TuNdMfacTFzsXDqgIyr/xtc0qq0oLor9Ikt0VB+q8fma h7dr7u6UkIjrRFr155s+OL81RZZu9K8AeNCofDEN6Dbq04GN X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Fix seveal odd-looking places in SM8550's dispcc driver: - duplicate entries in disp_cc_parent_map_4 and disp_cc_parent_map_5 - using &disp_cc_mdss_dptx0_link_div_clk_src as a source for disp_cc_mdss_dptx1_usb_router_link_intf_clk The SM8650 driver has been used as a reference. Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong --- drivers/clk/qcom/dispcc-sm8550.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8= 550.c index 31ae46f180a5..954b0f6fcea2 100644 --- a/drivers/clk/qcom/dispcc-sm8550.c +++ b/drivers/clk/qcom/dispcc-sm8550.c @@ -196,7 +196,7 @@ static const struct clk_parent_data disp_cc_parent_data= _3[] =3D { static const struct parent_map disp_cc_parent_map_4[] =3D { { P_BI_TCXO, 0 }, { P_DP0_PHY_PLL_LINK_CLK, 1 }, - { P_DP1_PHY_PLL_VCO_DIV_CLK, 2 }, + { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 }, { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, @@ -213,7 +213,7 @@ static const struct clk_parent_data disp_cc_parent_data= _4[] =3D { =20 static const struct parent_map disp_cc_parent_map_5[] =3D { { P_BI_TCXO, 0 }, - { P_DSI0_PHY_PLL_OUT_BYTECLK, 4 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, }; 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a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A clk_dp_ops should only be used for DisplayPort pixel clocks. Use clk_rcg2_ops for disp_cc_mdss_dptx1_aux_clk_src. Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong --- drivers/clk/qcom/dispcc-sm8550.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8= 550.c index 954b0f6fcea2..a98230540782 100644 --- a/drivers/clk/qcom/dispcc-sm8550.c +++ b/drivers/clk/qcom/dispcc-sm8550.c @@ -400,7 +400,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = =3D { .parent_data =3D disp_cc_parent_data_0, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_dp_ops, + .ops =3D &clk_rcg2_ops, }, }; =20 --=20 2.39.2 From nobody Wed Dec 17 15:36:21 2025 Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com [209.85.167.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30B6117F369 for ; Wed, 17 Jul 2024 10:04:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 17 Jul 2024 03:04:34 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52ed253924asm1425391e87.262.2024.07.17.03.04.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Jul 2024 03:04:33 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 17 Jul 2024 13:04:30 +0300 Subject: [PATCH v2 3/7] clk: qcom: dispcc-sm8550: make struct clk_init_data const Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240717-dispcc-sm8550-fixes-v2-3-5c4a3128c40b@linaro.org> References: <20240717-dispcc-sm8550-fixes-v2-0-5c4a3128c40b@linaro.org> In-Reply-To: <20240717-dispcc-sm8550-fixes-v2-0-5c4a3128c40b@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Neil Armstrong , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=31255; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=3U0IaWBEIqRdtwZA2UUJCobD4x7BHpMF9Uj+RLs3W+o=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBml5cuDq9oKuONko/iUueOTRUZbWeworrOnubHQ u6D2ipRJ3aJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZpeXLgAKCRCLPIo+Aiko 1cnPB/4tUkYVw0nNxCGLXejYy2ulCyBY90PmXqqrKglGc4NHzAKUIQEy7J96WUQ11oLfiJ9NAcY 0ucVRaWwkW+6qwnuqzVt6SrlpHZYEIisStpmwiv/HNsF2OvjwzWIZB476InIubZklB3lCZkJ7iN iShE5Zz15j9f5AVKKY0RWYJkCyTMxIivBvdseIFJk+Gdo2/dV3PuMI3fPe9ABg8LON6BP2T5v2h xFS4mQrWZSQqh+6pUEseLgSuCT2iGxzUdAohhM35Mx85fog8btxIMAJyJGJHgpxtteUqdYaBJzn 2N9BjeTa2JBxErDe2ciZK/HerIzUyWWB7M4NI5Hu/ZcuQZG5 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The clk_init_data instances are not changed at runtime. Mark them as constant data. Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong --- drivers/clk/qcom/dispcc-sm8550.c | 160 +++++++++++++++++++----------------= ---- 1 file changed, 80 insertions(+), 80 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8= 550.c index a98230540782..1604a6a4acdc 100644 --- a/drivers/clk/qcom/dispcc-sm8550.c +++ b/drivers/clk/qcom/dispcc-sm8550.c @@ -95,7 +95,7 @@ static struct clk_alpha_pll disp_cc_pll0 =3D { .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .clkr =3D { - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_pll0", .parent_data =3D &(const struct clk_parent_data) { .index =3D DT_BI_TCXO, @@ -126,7 +126,7 @@ static struct clk_alpha_pll disp_cc_pll1 =3D { .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .clkr =3D { - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_pll1", .parent_data =3D &(const struct clk_parent_data) { .index =3D DT_BI_TCXO, @@ -286,7 +286,7 @@ static struct clk_rcg2 disp_cc_mdss_ahb_clk_src =3D { .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_6, .freq_tbl =3D ftbl_disp_cc_mdss_ahb_clk_src, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_ahb_clk_src", .parent_data =3D disp_cc_parent_data_6, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_6), @@ -306,7 +306,7 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src =3D { .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_2, .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_byte0_clk_src", .parent_data =3D disp_cc_parent_data_2, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_2), @@ -321,7 +321,7 @@ static struct clk_rcg2 disp_cc_mdss_byte1_clk_src =3D { .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_2, .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_byte1_clk_src", .parent_data =3D disp_cc_parent_data_2, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_2), @@ -336,7 +336,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = =3D { .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_0, .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx0_aux_clk_src", .parent_data =3D disp_cc_parent_data_0, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), @@ -350,7 +350,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = =3D { .mnd_width =3D 0, .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_7, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx0_link_clk_src", .parent_data =3D disp_cc_parent_data_7, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_7), @@ -365,7 +365,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_sr= c =3D { .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_4, .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx0_pixel0_clk_src", .parent_data =3D disp_cc_parent_data_4, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_4), @@ -380,7 +380,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_sr= c =3D { .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_4, .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx0_pixel1_clk_src", .parent_data =3D disp_cc_parent_data_4, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_4), @@ -395,7 +395,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = =3D { .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_0, .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx1_aux_clk_src", .parent_data =3D disp_cc_parent_data_0, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), @@ -409,7 +409,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = =3D { .mnd_width =3D 0, .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_3, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx1_link_clk_src", .parent_data =3D disp_cc_parent_data_3, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), @@ -424,7 +424,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_sr= c =3D { .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_1, .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx1_pixel0_clk_src", .parent_data =3D disp_cc_parent_data_1, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), @@ -439,7 +439,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_sr= c =3D { .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_1, .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx1_pixel1_clk_src", .parent_data =3D disp_cc_parent_data_1, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), @@ -454,7 +454,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = =3D { .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_0, .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx2_aux_clk_src", .parent_data =3D disp_cc_parent_data_0, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), @@ -468,7 +468,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = =3D { .mnd_width =3D 0, .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_3, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx2_link_clk_src", .parent_data =3D disp_cc_parent_data_3, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), @@ -483,7 +483,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_sr= c =3D { .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_1, .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx2_pixel0_clk_src", .parent_data =3D disp_cc_parent_data_1, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), @@ -498,7 +498,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_sr= c =3D { .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_1, .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx2_pixel1_clk_src", .parent_data =3D disp_cc_parent_data_1, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), @@ -513,7 +513,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = =3D { .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_0, .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx3_aux_clk_src", .parent_data =3D disp_cc_parent_data_0, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), @@ -527,7 +527,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = =3D { .mnd_width =3D 0, .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_3, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx3_link_clk_src", .parent_data =3D disp_cc_parent_data_3, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), @@ -542,7 +542,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_sr= c =3D { .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_1, .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx3_pixel0_clk_src", .parent_data =3D disp_cc_parent_data_1, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), @@ -557,7 +557,7 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src =3D { .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_5, .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_esc0_clk_src", .parent_data =3D disp_cc_parent_data_5, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_5), @@ -572,7 +572,7 @@ static struct clk_rcg2 disp_cc_mdss_esc1_clk_src =3D { .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_5, .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_esc1_clk_src", .parent_data =3D disp_cc_parent_data_5, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_5), @@ -600,7 +600,7 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src =3D { .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_8, .freq_tbl =3D ftbl_disp_cc_mdss_mdp_clk_src, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_mdp_clk_src", .parent_data =3D disp_cc_parent_data_8, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_8), @@ -615,7 +615,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src =3D { .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_2, .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_pclk0_clk_src", .parent_data =3D disp_cc_parent_data_2, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_2), @@ -630,7 +630,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src =3D { .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_2, .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_pclk1_clk_src", .parent_data =3D disp_cc_parent_data_2, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_2), @@ -645,7 +645,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src =3D { .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_0, .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_vsync_clk_src", .parent_data =3D disp_cc_parent_data_0, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), @@ -665,7 +665,7 @@ static struct clk_rcg2 disp_cc_sleep_clk_src =3D { .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_9, .freq_tbl =3D ftbl_disp_cc_sleep_clk_src, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_sleep_clk_src", .parent_data =3D disp_cc_parent_data_9, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_9), @@ -680,7 +680,7 @@ static struct clk_rcg2 disp_cc_xo_clk_src =3D { .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_0, .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_xo_clk_src", .parent_data =3D disp_cc_parent_data_0_ao, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0_ao), @@ -693,7 +693,7 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk= _src =3D { .reg =3D 0x8120, .shift =3D 0, .width =3D 4, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_byte0_div_clk_src", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_byte0_clk_src.clkr.hw, @@ -707,7 +707,7 @@ static struct clk_regmap_div disp_cc_mdss_byte1_div_clk= _src =3D { .reg =3D 0x813c, .shift =3D 0, .width =3D 4, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_byte1_div_clk_src", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_byte1_clk_src.clkr.hw, @@ -721,7 +721,7 @@ static struct clk_regmap_div disp_cc_mdss_dptx0_link_di= v_clk_src =3D { .reg =3D 0x8188, .shift =3D 0, .width =3D 4, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx0_link_div_clk_src", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, @@ -736,7 +736,7 @@ static struct clk_regmap_div disp_cc_mdss_dptx1_link_di= v_clk_src =3D { .reg =3D 0x821c, .shift =3D 0, .width =3D 4, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx1_link_div_clk_src", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, @@ -751,7 +751,7 @@ static struct clk_regmap_div disp_cc_mdss_dptx2_link_di= v_clk_src =3D { .reg =3D 0x8250, .shift =3D 0, .width =3D 4, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx2_link_div_clk_src", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, @@ -766,7 +766,7 @@ static struct clk_regmap_div disp_cc_mdss_dptx3_link_di= v_clk_src =3D { .reg =3D 0x82cc, .shift =3D 0, .width =3D 4, - .clkr.hw.init =3D &(struct clk_init_data) { + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx3_link_div_clk_src", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, @@ -783,7 +783,7 @@ static struct clk_branch disp_cc_mdss_accu_clk =3D { .clkr =3D { .enable_reg =3D 0xe058, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_accu_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_xo_clk_src.clkr.hw, @@ -801,7 +801,7 @@ static struct clk_branch disp_cc_mdss_ahb1_clk =3D { .clkr =3D { .enable_reg =3D 0xa020, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_ahb1_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_ahb_clk_src.clkr.hw, @@ -819,7 +819,7 @@ static struct clk_branch disp_cc_mdss_ahb_clk =3D { .clkr =3D { .enable_reg =3D 0x80a4, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_ahb_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_ahb_clk_src.clkr.hw, @@ -837,7 +837,7 @@ static struct clk_branch disp_cc_mdss_byte0_clk =3D { .clkr =3D { .enable_reg =3D 0x8028, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_byte0_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_byte0_clk_src.clkr.hw, @@ -855,7 +855,7 @@ static struct clk_branch disp_cc_mdss_byte0_intf_clk = =3D { .clkr =3D { .enable_reg =3D 0x802c, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_byte0_intf_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_byte0_div_clk_src.clkr.hw, @@ -873,7 +873,7 @@ static struct clk_branch disp_cc_mdss_byte1_clk =3D { .clkr =3D { .enable_reg =3D 0x8030, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_byte1_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_byte1_clk_src.clkr.hw, @@ -891,7 +891,7 @@ static struct clk_branch disp_cc_mdss_byte1_intf_clk = =3D { .clkr =3D { .enable_reg =3D 0x8034, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_byte1_intf_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_byte1_div_clk_src.clkr.hw, @@ -909,7 +909,7 @@ static struct clk_branch disp_cc_mdss_dptx0_aux_clk =3D= { .clkr =3D { .enable_reg =3D 0x8058, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx0_aux_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, @@ -927,7 +927,7 @@ static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = =3D { .clkr =3D { .enable_reg =3D 0x804c, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx0_crypto_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, @@ -945,7 +945,7 @@ static struct clk_branch disp_cc_mdss_dptx0_link_clk = =3D { .clkr =3D { .enable_reg =3D 0x8040, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx0_link_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, @@ -963,7 +963,7 @@ static struct clk_branch disp_cc_mdss_dptx0_link_intf_c= lk =3D { .clkr =3D { .enable_reg =3D 0x8048, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx0_link_intf_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, @@ -981,7 +981,7 @@ static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = =3D { .clkr =3D { .enable_reg =3D 0x8050, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx0_pixel0_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, @@ -999,7 +999,7 @@ static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = =3D { .clkr =3D { .enable_reg =3D 0x8054, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx0_pixel1_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, @@ -1017,7 +1017,7 @@ static struct clk_branch disp_cc_mdss_dptx0_usb_route= r_link_intf_clk =3D { .clkr =3D { .enable_reg =3D 0x8044, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx0_usb_router_link_intf_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, @@ -1035,7 +1035,7 @@ static struct clk_branch disp_cc_mdss_dptx1_aux_clk = =3D { .clkr =3D { .enable_reg =3D 0x8074, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx1_aux_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw, @@ -1053,7 +1053,7 @@ static struct clk_branch disp_cc_mdss_dptx1_crypto_cl= k =3D { .clkr =3D { .enable_reg =3D 0x8070, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx1_crypto_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, @@ -1071,7 +1071,7 @@ static struct clk_branch disp_cc_mdss_dptx1_link_clk = =3D { .clkr =3D { .enable_reg =3D 0x8064, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx1_link_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, @@ -1089,7 +1089,7 @@ static struct clk_branch disp_cc_mdss_dptx1_link_intf= _clk =3D { .clkr =3D { .enable_reg =3D 0x806c, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx1_link_intf_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, @@ -1107,7 +1107,7 @@ static struct clk_branch disp_cc_mdss_dptx1_pixel0_cl= k =3D { .clkr =3D { .enable_reg =3D 0x805c, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx1_pixel0_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, @@ -1125,7 +1125,7 @@ static struct clk_branch disp_cc_mdss_dptx1_pixel1_cl= k =3D { .clkr =3D { .enable_reg =3D 0x8060, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx1_pixel1_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, @@ -1143,7 +1143,7 @@ static struct clk_branch disp_cc_mdss_dptx1_usb_route= r_link_intf_clk =3D { .clkr =3D { .enable_reg =3D 0x8068, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx1_usb_router_link_intf_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, @@ -1161,7 +1161,7 @@ static struct clk_branch disp_cc_mdss_dptx2_aux_clk = =3D { .clkr =3D { .enable_reg =3D 0x808c, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx2_aux_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw, @@ -1179,7 +1179,7 @@ static struct clk_branch disp_cc_mdss_dptx2_crypto_cl= k =3D { .clkr =3D { .enable_reg =3D 0x8088, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx2_crypto_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, @@ -1197,7 +1197,7 @@ static struct clk_branch disp_cc_mdss_dptx2_link_clk = =3D { .clkr =3D { .enable_reg =3D 0x8080, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx2_link_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, @@ -1215,7 +1215,7 @@ static struct clk_branch disp_cc_mdss_dptx2_link_intf= _clk =3D { .clkr =3D { .enable_reg =3D 0x8084, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx2_link_intf_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw, @@ -1233,7 +1233,7 @@ static struct clk_branch disp_cc_mdss_dptx2_pixel0_cl= k =3D { .clkr =3D { .enable_reg =3D 0x8078, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx2_pixel0_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, @@ -1251,7 +1251,7 @@ static struct clk_branch disp_cc_mdss_dptx2_pixel1_cl= k =3D { .clkr =3D { .enable_reg =3D 0x807c, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx2_pixel1_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, @@ -1269,7 +1269,7 @@ static struct clk_branch disp_cc_mdss_dptx3_aux_clk = =3D { .clkr =3D { .enable_reg =3D 0x809c, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx3_aux_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw, @@ -1287,7 +1287,7 @@ static struct clk_branch disp_cc_mdss_dptx3_crypto_cl= k =3D { .clkr =3D { .enable_reg =3D 0x80a0, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx3_crypto_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, @@ -1305,7 +1305,7 @@ static struct clk_branch disp_cc_mdss_dptx3_link_clk = =3D { .clkr =3D { .enable_reg =3D 0x8094, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx3_link_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, @@ -1323,7 +1323,7 @@ static struct clk_branch disp_cc_mdss_dptx3_link_intf= _clk =3D { .clkr =3D { .enable_reg =3D 0x8098, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx3_link_intf_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw, @@ -1341,7 +1341,7 @@ static struct clk_branch disp_cc_mdss_dptx3_pixel0_cl= k =3D { .clkr =3D { .enable_reg =3D 0x8090, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_dptx3_pixel0_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, @@ -1359,7 +1359,7 @@ static struct clk_branch disp_cc_mdss_esc0_clk =3D { .clkr =3D { .enable_reg =3D 0x8038, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_esc0_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_esc0_clk_src.clkr.hw, @@ -1377,7 +1377,7 @@ static struct clk_branch disp_cc_mdss_esc1_clk =3D { .clkr =3D { .enable_reg =3D 0x803c, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_esc1_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_esc1_clk_src.clkr.hw, @@ -1395,7 +1395,7 @@ static struct clk_branch disp_cc_mdss_mdp1_clk =3D { .clkr =3D { .enable_reg =3D 0xa004, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_mdp1_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_mdp_clk_src.clkr.hw, @@ -1413,7 +1413,7 @@ static struct clk_branch disp_cc_mdss_mdp_clk =3D { .clkr =3D { .enable_reg =3D 0x800c, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_mdp_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_mdp_clk_src.clkr.hw, @@ -1431,7 +1431,7 @@ static struct clk_branch disp_cc_mdss_mdp_lut1_clk = =3D { .clkr =3D { .enable_reg =3D 0xa010, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_mdp_lut1_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_mdp_clk_src.clkr.hw, @@ -1449,7 +1449,7 @@ static struct clk_branch disp_cc_mdss_mdp_lut_clk =3D= { .clkr =3D { .enable_reg =3D 0x8018, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_mdp_lut_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_mdp_clk_src.clkr.hw, @@ -1467,7 +1467,7 @@ static struct clk_branch disp_cc_mdss_non_gdsc_ahb_cl= k =3D { .clkr =3D { .enable_reg =3D 0xc004, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_non_gdsc_ahb_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_ahb_clk_src.clkr.hw, @@ -1485,7 +1485,7 @@ static struct clk_branch disp_cc_mdss_pclk0_clk =3D { .clkr =3D { .enable_reg =3D 0x8004, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_pclk0_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_pclk0_clk_src.clkr.hw, @@ -1503,7 +1503,7 @@ static struct clk_branch disp_cc_mdss_pclk1_clk =3D { .clkr =3D { .enable_reg =3D 0x8008, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_pclk1_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_pclk1_clk_src.clkr.hw, @@ -1521,7 +1521,7 @@ static struct clk_branch disp_cc_mdss_rscc_ahb_clk = =3D { .clkr =3D { .enable_reg =3D 0xc00c, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_rscc_ahb_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_ahb_clk_src.clkr.hw, @@ -1539,7 +1539,7 @@ static struct clk_branch disp_cc_mdss_rscc_vsync_clk = =3D { .clkr =3D { .enable_reg =3D 0xc008, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_rscc_vsync_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_vsync_clk_src.clkr.hw, @@ -1557,7 +1557,7 @@ static struct clk_branch disp_cc_mdss_vsync1_clk =3D { .clkr =3D { .enable_reg =3D 0xa01c, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data) { + .hw.init =3D &(const struct clk_init_data) { .name =3D "disp_cc_mdss_vsync1_clk", .parent_hws =3D (const struct clk_hw*[]) { &disp_cc_mdss_vsync_clk_src.clkr.hw, @@ -1575,7 +1575,7 @@ static struct clk_branch disp_cc_mdss_vsync_clk =3D { .clkr =3D { .enable_reg =3D 0x8024, .enable_mask =3D BIT(0), - .hw.init =3D &(struct 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<20240717-dispcc-sm8550-fixes-v2-0-5c4a3128c40b@linaro.org> In-Reply-To: <20240717-dispcc-sm8550-fixes-v2-0-5c4a3128c40b@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Neil Armstrong , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1043; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=xSYijA7D//yWyt82akVAYXvITlndr/u84aknEBgxoyo=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBml5cux1OaEy/tDtM3ebaQYLIoQtC3coJAZSdD0 7kX3z2l0C6JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZpeXLgAKCRCLPIo+Aiko 1W6IB/9s6d1XOqK1r1eJyN1ZKJImtuzDysw4jfpMr3g5Dzd2FR9iawLGuE+DGRm7R2obNkmFCX5 G9MvSGx9RVBLE1+HF97EZQi7jV+jePFoxovR7NIaXRLgCOuFF72ar4693aWYq/Z3blMxQj9w+ph hNduR0jBs4U6lhIeYYsVTbNJk2eFL11ZnMB5sUIaReguy0ixvli0/e7FIy2kNtdPvKqm2OzRjBv tgQV0Mf921EXGOYTaQiuMmRxYIyVEOO6chsJp31oN9zJu4BQHEHG/TNNRz/za064OqPFSQDKrmE SDZNBk5FqQQZJdm+i88q3EGNFOO5XdiCYxQIQSZZH2YgH13D X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Add missing POLL_CFG_GDSCR to the MDSS GDSC flags. Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong --- drivers/clk/qcom/dispcc-sm8550.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8= 550.c index 1604a6a4acdc..eebc4c2258d0 100644 --- a/drivers/clk/qcom/dispcc-sm8550.c +++ b/drivers/clk/qcom/dispcc-sm8550.c @@ -1611,7 +1611,7 @@ static struct gdsc mdss_gdsc =3D { .name =3D "mdss_gdsc", }, .pwrsts =3D PWRSTS_OFF_ON, - .flags =3D HW_CTRL | RETAIN_FF_ENABLE, + .flags =3D POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE, }; =20 static struct gdsc mdss_int2_gdsc =3D { @@ -1620,7 +1620,7 @@ static struct gdsc mdss_int2_gdsc =3D { .name =3D "mdss_int2_gdsc", }, .pwrsts =3D PWRSTS_OFF_ON, - .flags =3D HW_CTRL | RETAIN_FF_ENABLE, + .flags =3D POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE, }; =20 static struct clk_regmap *disp_cc_sm8550_clocks[] =3D { --=20 2.39.2 From nobody Wed Dec 17 15:36:21 2025 Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D84D417F4F6 for ; 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Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong --- drivers/clk/qcom/dispcc-sm8550.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8= 550.c index eebc4c2258d0..1d884e30d461 100644 --- a/drivers/clk/qcom/dispcc-sm8550.c +++ b/drivers/clk/qcom/dispcc-sm8550.c @@ -562,7 +562,7 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src =3D { .parent_data =3D disp_cc_parent_data_5, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_5), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }, }; =20 @@ -577,7 +577,7 @@ static struct clk_rcg2 disp_cc_mdss_esc1_clk_src =3D { .parent_data =3D disp_cc_parent_data_5, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_5), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }, }; =20 --=20 2.39.2 From nobody Wed Dec 17 15:36:21 2025 Received: from mail-lf1-f48.google.com (mail-lf1-f48.google.com [209.85.167.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20C5B17F387 for ; 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Wed, 17 Jul 2024 03:04:37 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52ed253924asm1425391e87.262.2024.07.17.03.04.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Jul 2024 03:04:36 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 17 Jul 2024 13:04:33 +0300 Subject: [PATCH v2 6/7] clk: qcom: fold dispcc-sm8650 info dispcc-sm8550 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240717-dispcc-sm8550-fixes-v2-6-5c4a3128c40b@linaro.org> References: <20240717-dispcc-sm8550-fixes-v2-0-5c4a3128c40b@linaro.org> In-Reply-To: <20240717-dispcc-sm8550-fixes-v2-0-5c4a3128c40b@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Neil Armstrong , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=58162; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=3N6j5xYMSkSDjPk/3hdqKOhmpjdFz3yirqRzrJJVTOQ=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBml5cuTFokIG/ofExoMi6mvhZ91eKP9OVkRnTGZ 7ayvjP+G12JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZpeXLgAKCRCLPIo+Aiko 1TfzB/9+2yqKym7XIZHFMVRANiqaT6c/uRvkoiB8H/USF8QH3SCtg5W03m5qW+opEncofygR1Pd 3TPEf/CJTqEwHemSDI1PSWkKqhgy2HbnfgQM0tQCoxrD4VAX/TXNqSE/mU8z/jxSM3nn6sTXjps KZFkD+98gmYMC39TqRCv2GE9onAgHnF8dg31ZAfAEDwf27yFVXai1DoqMO7DJgCQmLDtPkD04mC B8oh69A123AWlVPeACNyemZfSjc9Xzr8GGv9QnnA6vPNUKP9mHp++PrkG6F+FZHxL9GaMc5DpUo Kous+KNR1J1H8k+Dp7WAdg0+L1oz0PV1dv+fmPz0fnQDXCmU X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A There is a very minor difference between display clock controller drivers for SM8550 and SM8650 platforms. Fold the second one into the first one to reduce kernel footprint. The bindings for these two hardware blocks are fully compatible. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Neil Armstrong --- drivers/clk/qcom/Kconfig | 14 +- drivers/clk/qcom/Makefile | 1 - drivers/clk/qcom/dispcc-sm8550.c | 24 +- drivers/clk/qcom/dispcc-sm8650.c | 1796 ----------------------------------= ---- 4 files changed, 24 insertions(+), 1811 deletions(-) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 11ae28430dad..497eed16a7d7 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -931,20 +931,10 @@ config SM_DISPCC_8450 config SM_DISPCC_8550 tristate "SM8550 Display Clock Controller" depends on ARM64 || COMPILE_TEST - depends on SM_GCC_8550 + depends on SM_GCC_8550 || SM_GCC_8650 help Support for the display clock controller on Qualcomm Technologies, Inc - SM8550 devices. - Say Y if you want to support display devices and functionality such as - splash screen. - -config SM_DISPCC_8650 - tristate "SM8650 Display Clock Controller" - depends on ARM64 || COMPILE_TEST - select SM_GCC_8650 - help - Support for the display clock controller on Qualcomm Technologies, Inc - SM8650 devices. + SM8550 or SM8650 devices. Say Y if you want to support display devices and functionality such as splash screen. =20 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 0de5fce6113a..c8149ef37fe0 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -121,7 +121,6 @@ obj-$(CONFIG_SM_DISPCC_7150) +=3D dispcc-sm7150.o obj-$(CONFIG_SM_DISPCC_8250) +=3D dispcc-sm8250.o obj-$(CONFIG_SM_DISPCC_8450) +=3D dispcc-sm8450.o obj-$(CONFIG_SM_DISPCC_8550) +=3D dispcc-sm8550.o -obj-$(CONFIG_SM_DISPCC_8650) +=3D dispcc-sm8650.o obj-$(CONFIG_SM_GCC_4450) +=3D gcc-sm4450.o obj-$(CONFIG_SM_GCC_6115) +=3D gcc-sm6115.o obj-$(CONFIG_SM_GCC_6125) +=3D gcc-sm6125.o diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8= 550.c index 1d884e30d461..7f9021ca0ecb 100644 --- a/drivers/clk/qcom/dispcc-sm8550.c +++ b/drivers/clk/qcom/dispcc-sm8550.c @@ -71,7 +71,7 @@ enum { P_SLEEP_CLK, }; =20 -static const struct pll_vco lucid_ole_vco[] =3D { +static struct pll_vco lucid_ole_vco[] =3D { { 249600000, 2000000000, 0 }, }; =20 @@ -594,6 +594,18 @@ static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk= _src[] =3D { { } }; =20 +static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src_sm8650[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(402000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + static struct clk_rcg2 disp_cc_mdss_mdp_clk_src =3D { .cmd_rcgr =3D 0x80d8, .mnd_width =3D 0, @@ -1739,6 +1751,7 @@ static struct qcom_cc_desc disp_cc_sm8550_desc =3D { =20 static const struct of_device_id disp_cc_sm8550_match_table[] =3D { { .compatible =3D "qcom,sm8550-dispcc" }, + { .compatible =3D "qcom,sm8650-dispcc" }, { } }; MODULE_DEVICE_TABLE(of, disp_cc_sm8550_match_table); @@ -1762,6 +1775,13 @@ static int disp_cc_sm8550_probe(struct platform_devi= ce *pdev) goto err_put_rpm; } =20 + if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8650-dispcc")) { + lucid_ole_vco[0].max_freq =3D 2100000000; + disp_cc_mdss_mdp_clk_src.freq_tbl =3D ftbl_disp_cc_mdss_mdp_clk_src_sm86= 50; + disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr.hw.init->parent_hws[0] = =3D + &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw; + } + clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); clk_lucid_ole_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); =20 @@ -1795,5 +1815,5 @@ static struct platform_driver disp_cc_sm8550_driver = =3D { =20 module_platform_driver(disp_cc_sm8550_driver); =20 -MODULE_DESCRIPTION("QTI DISPCC SM8550 Driver"); +MODULE_DESCRIPTION("QTI DISPCC SM8550 / SM8650 Driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/dispcc-sm8650.c b/drivers/clk/qcom/dispcc-sm8= 650.c deleted file mode 100644 index ce563cf93235..000000000000 --- a/drivers/clk/qcom/dispcc-sm8650.c +++ /dev/null @@ -1,1796 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved - * Copyright (c) 2023, Linaro Ltd. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "common.h" -#include "clk-alpha-pll.h" -#include "clk-branch.h" -#include "clk-pll.h" -#include "clk-rcg.h" -#include "clk-regmap.h" -#include "clk-regmap-divider.h" -#include "reset.h" -#include "gdsc.h" - -/* Need to match the order of clocks in DT binding */ -enum { - DT_BI_TCXO, - DT_BI_TCXO_AO, - DT_AHB_CLK, - DT_SLEEP_CLK, - - DT_DSI0_PHY_PLL_OUT_BYTECLK, - DT_DSI0_PHY_PLL_OUT_DSICLK, - DT_DSI1_PHY_PLL_OUT_BYTECLK, - DT_DSI1_PHY_PLL_OUT_DSICLK, - - DT_DP0_PHY_PLL_LINK_CLK, - DT_DP0_PHY_PLL_VCO_DIV_CLK, - DT_DP1_PHY_PLL_LINK_CLK, - DT_DP1_PHY_PLL_VCO_DIV_CLK, - DT_DP2_PHY_PLL_LINK_CLK, - DT_DP2_PHY_PLL_VCO_DIV_CLK, - DT_DP3_PHY_PLL_LINK_CLK, - DT_DP3_PHY_PLL_VCO_DIV_CLK, -}; - -#define DISP_CC_MISC_CMD 0xF000 - -enum { - P_BI_TCXO, - P_DISP_CC_PLL0_OUT_MAIN, - P_DISP_CC_PLL1_OUT_EVEN, - P_DISP_CC_PLL1_OUT_MAIN, - P_DP0_PHY_PLL_LINK_CLK, - P_DP0_PHY_PLL_VCO_DIV_CLK, - P_DP1_PHY_PLL_LINK_CLK, - P_DP1_PHY_PLL_VCO_DIV_CLK, - P_DP2_PHY_PLL_LINK_CLK, - P_DP2_PHY_PLL_VCO_DIV_CLK, - P_DP3_PHY_PLL_LINK_CLK, - P_DP3_PHY_PLL_VCO_DIV_CLK, - P_DSI0_PHY_PLL_OUT_BYTECLK, - P_DSI0_PHY_PLL_OUT_DSICLK, - P_DSI1_PHY_PLL_OUT_BYTECLK, - P_DSI1_PHY_PLL_OUT_DSICLK, - P_SLEEP_CLK, -}; - -static const struct pll_vco lucid_ole_vco[] =3D { - { 249600000, 2100000000, 0 }, -}; - -static const struct alpha_pll_config disp_cc_pll0_config =3D { - .l =3D 0xd, - .alpha =3D 0x6492, - .config_ctl_val =3D 0x20485699, - .config_ctl_hi_val =3D 0x00182261, - .config_ctl_hi1_val =3D 0x82aa299c, - .test_ctl_val =3D 0x00000000, - .test_ctl_hi_val =3D 0x00000003, - .test_ctl_hi1_val =3D 0x00009000, - .test_ctl_hi2_val =3D 0x00000034, - .user_ctl_val =3D 0x00000000, - .user_ctl_hi_val =3D 0x00000005, -}; - -static struct clk_alpha_pll disp_cc_pll0 =3D { - .offset =3D 0x0, - .vco_table =3D lucid_ole_vco, - .num_vco =3D ARRAY_SIZE(lucid_ole_vco), - .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], - .clkr =3D { - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_pll0", - .parent_data =3D &(const struct clk_parent_data) { - .index =3D DT_BI_TCXO, - }, - .num_parents =3D 1, - .ops =3D &clk_alpha_pll_reset_lucid_ole_ops, - }, - }, -}; - -static const struct alpha_pll_config disp_cc_pll1_config =3D { - .l =3D 0x1f, - .alpha =3D 0x4000, - .config_ctl_val =3D 0x20485699, - .config_ctl_hi_val =3D 0x00182261, - .config_ctl_hi1_val =3D 0x82aa299c, - .test_ctl_val =3D 0x00000000, - .test_ctl_hi_val =3D 0x00000003, - .test_ctl_hi1_val =3D 0x00009000, - .test_ctl_hi2_val =3D 0x00000034, - .user_ctl_val =3D 0x00000000, - .user_ctl_hi_val =3D 0x00000005, -}; - -static struct clk_alpha_pll disp_cc_pll1 =3D { - .offset =3D 0x1000, - .vco_table =3D lucid_ole_vco, - .num_vco =3D ARRAY_SIZE(lucid_ole_vco), - .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], - .clkr =3D { - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_pll1", - .parent_data =3D &(const struct clk_parent_data) { - .index =3D DT_BI_TCXO, - }, - .num_parents =3D 1, - .ops =3D &clk_alpha_pll_reset_lucid_ole_ops, - }, - }, -}; - -static const struct parent_map disp_cc_parent_map_0[] =3D { - { P_BI_TCXO, 0 }, -}; - -static const struct clk_parent_data disp_cc_parent_data_0[] =3D { - { .index =3D DT_BI_TCXO }, -}; - -static const struct clk_parent_data disp_cc_parent_data_0_ao[] =3D { - { .index =3D DT_BI_TCXO_AO }, -}; - -static const struct parent_map disp_cc_parent_map_1[] =3D { - { P_BI_TCXO, 0 }, - { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, - { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, - { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, -}; - -static const struct clk_parent_data disp_cc_parent_data_1[] =3D { - { .index =3D DT_BI_TCXO }, - { .index =3D DT_DP3_PHY_PLL_VCO_DIV_CLK }, - { .index =3D DT_DP1_PHY_PLL_VCO_DIV_CLK }, - { .index =3D DT_DP2_PHY_PLL_VCO_DIV_CLK }, -}; - -static const struct parent_map disp_cc_parent_map_2[] =3D { - { P_BI_TCXO, 0 }, - { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, - { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, - { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, - { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, -}; - -static const struct clk_parent_data disp_cc_parent_data_2[] =3D { - { .index =3D DT_BI_TCXO }, - { .index =3D DT_DSI0_PHY_PLL_OUT_DSICLK }, - { .index =3D DT_DSI0_PHY_PLL_OUT_BYTECLK }, - { .index =3D DT_DSI1_PHY_PLL_OUT_DSICLK }, - { .index =3D DT_DSI1_PHY_PLL_OUT_BYTECLK }, -}; - -static const struct parent_map disp_cc_parent_map_3[] =3D { - { P_BI_TCXO, 0 }, - { P_DP1_PHY_PLL_LINK_CLK, 2 }, - { P_DP2_PHY_PLL_LINK_CLK, 3 }, - { P_DP3_PHY_PLL_LINK_CLK, 4 }, -}; - -static const struct clk_parent_data disp_cc_parent_data_3[] =3D { - { .index =3D DT_BI_TCXO }, - { .index =3D DT_DP1_PHY_PLL_LINK_CLK }, - { .index =3D DT_DP2_PHY_PLL_LINK_CLK }, - { .index =3D DT_DP3_PHY_PLL_LINK_CLK }, -}; - -static const struct parent_map disp_cc_parent_map_4[] =3D { - { P_BI_TCXO, 0 }, - { P_DP0_PHY_PLL_LINK_CLK, 1 }, - { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 }, - { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, - { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, - { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, -}; - -static const struct clk_parent_data disp_cc_parent_data_4[] =3D { - { .index =3D DT_BI_TCXO }, - { .index =3D DT_DP0_PHY_PLL_LINK_CLK }, - { .index =3D DT_DP0_PHY_PLL_VCO_DIV_CLK }, - { .index =3D DT_DP3_PHY_PLL_VCO_DIV_CLK }, - { .index =3D DT_DP1_PHY_PLL_VCO_DIV_CLK }, - { .index =3D DT_DP2_PHY_PLL_VCO_DIV_CLK }, -}; - -static const struct parent_map disp_cc_parent_map_5[] =3D { - { P_BI_TCXO, 0 }, - { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, - { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, -}; - -static const struct clk_parent_data disp_cc_parent_data_5[] =3D { - { .index =3D DT_BI_TCXO }, - { .index =3D DT_DSI0_PHY_PLL_OUT_BYTECLK }, - { .index =3D DT_DSI1_PHY_PLL_OUT_BYTECLK }, -}; - -static const struct parent_map disp_cc_parent_map_6[] =3D { - { P_BI_TCXO, 0 }, - { P_DISP_CC_PLL1_OUT_MAIN, 4 }, - { P_DISP_CC_PLL1_OUT_EVEN, 6 }, -}; - -static const struct clk_parent_data disp_cc_parent_data_6[] =3D { - { .index =3D DT_BI_TCXO }, - { .hw =3D &disp_cc_pll1.clkr.hw }, - { .hw =3D &disp_cc_pll1.clkr.hw }, -}; - -static const struct parent_map disp_cc_parent_map_7[] =3D { - { P_BI_TCXO, 0 }, - { P_DP0_PHY_PLL_LINK_CLK, 1 }, - { P_DP1_PHY_PLL_LINK_CLK, 2 }, - { P_DP2_PHY_PLL_LINK_CLK, 3 }, - { P_DP3_PHY_PLL_LINK_CLK, 4 }, -}; - -static const struct clk_parent_data disp_cc_parent_data_7[] =3D { - { .index =3D DT_BI_TCXO }, - { .index =3D DT_DP0_PHY_PLL_LINK_CLK }, - { .index =3D DT_DP1_PHY_PLL_LINK_CLK }, - { .index =3D DT_DP2_PHY_PLL_LINK_CLK }, - { .index =3D DT_DP3_PHY_PLL_LINK_CLK }, -}; - -static const struct parent_map disp_cc_parent_map_8[] =3D { - { P_BI_TCXO, 0 }, - { P_DISP_CC_PLL0_OUT_MAIN, 1 }, - { P_DISP_CC_PLL1_OUT_MAIN, 4 }, - { P_DISP_CC_PLL1_OUT_EVEN, 6 }, -}; - -static const struct clk_parent_data disp_cc_parent_data_8[] =3D { - { .index =3D DT_BI_TCXO }, - { .hw =3D &disp_cc_pll0.clkr.hw }, - { .hw =3D &disp_cc_pll1.clkr.hw }, - { .hw =3D &disp_cc_pll1.clkr.hw }, -}; - -static const struct parent_map disp_cc_parent_map_9[] =3D { - { P_SLEEP_CLK, 0 }, -}; - -static const struct clk_parent_data disp_cc_parent_data_9[] =3D { - { .index =3D DT_SLEEP_CLK }, -}; - -static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] =3D { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), - F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0), - { } -}; - -static struct clk_rcg2 disp_cc_mdss_ahb_clk_src =3D { - .cmd_rcgr =3D 0x82e8, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D disp_cc_parent_map_6, - .freq_tbl =3D ftbl_disp_cc_mdss_ahb_clk_src, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_ahb_clk_src", - .parent_data =3D disp_cc_parent_data_6, - .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_6), - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, - }, -}; - -static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] =3D { - F(19200000, P_BI_TCXO, 1, 0, 0), - { } -}; - -static struct clk_rcg2 disp_cc_mdss_byte0_clk_src =3D { - .cmd_rcgr =3D 0x8108, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D disp_cc_parent_map_2, - .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_byte0_clk_src", - .parent_data =3D disp_cc_parent_data_2, - .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_2), - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_byte2_ops, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_byte1_clk_src =3D { - .cmd_rcgr =3D 0x8124, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D disp_cc_parent_map_2, - .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_byte1_clk_src", - .parent_data =3D disp_cc_parent_data_2, - .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_2), - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_byte2_ops, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src =3D { - .cmd_rcgr =3D 0x81bc, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D disp_cc_parent_map_0, - .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx0_aux_clk_src", - .parent_data =3D disp_cc_parent_data_0, - .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src =3D { - .cmd_rcgr =3D 0x8170, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D disp_cc_parent_map_7, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx0_link_clk_src", - .parent_data =3D disp_cc_parent_data_7, - .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_7), - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_byte2_ops, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src =3D { - .cmd_rcgr =3D 0x818c, - .mnd_width =3D 16, - .hid_width =3D 5, - .parent_map =3D disp_cc_parent_map_4, - .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx0_pixel0_clk_src", - .parent_data =3D disp_cc_parent_data_4, - .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_4), - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_dp_ops, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src =3D { - .cmd_rcgr =3D 0x81a4, - .mnd_width =3D 16, - .hid_width =3D 5, - .parent_map =3D disp_cc_parent_map_4, - .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx0_pixel1_clk_src", - .parent_data =3D disp_cc_parent_data_4, - .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_4), - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_dp_ops, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src =3D { - .cmd_rcgr =3D 0x8220, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D disp_cc_parent_map_0, - .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx1_aux_clk_src", - .parent_data =3D disp_cc_parent_data_0, - .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src =3D { - .cmd_rcgr =3D 0x8204, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D disp_cc_parent_map_3, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx1_link_clk_src", - .parent_data =3D disp_cc_parent_data_3, - .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_byte2_ops, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src =3D { - .cmd_rcgr =3D 0x81d4, - .mnd_width =3D 16, - .hid_width =3D 5, - .parent_map =3D disp_cc_parent_map_1, - .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx1_pixel0_clk_src", - .parent_data =3D disp_cc_parent_data_1, - .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_dp_ops, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src =3D { - .cmd_rcgr =3D 0x81ec, - .mnd_width =3D 16, - .hid_width =3D 5, - .parent_map =3D disp_cc_parent_map_1, - .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx1_pixel1_clk_src", - .parent_data =3D disp_cc_parent_data_1, - .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_dp_ops, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src =3D { - .cmd_rcgr =3D 0x8284, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D disp_cc_parent_map_0, - .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx2_aux_clk_src", - .parent_data =3D disp_cc_parent_data_0, - .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src =3D { - .cmd_rcgr =3D 0x8238, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D disp_cc_parent_map_3, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx2_link_clk_src", - .parent_data =3D disp_cc_parent_data_3, - .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_byte2_ops, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src =3D { - .cmd_rcgr =3D 0x8254, - .mnd_width =3D 16, - .hid_width =3D 5, - .parent_map =3D disp_cc_parent_map_1, - .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx2_pixel0_clk_src", - .parent_data =3D disp_cc_parent_data_1, - .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_dp_ops, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src =3D { - .cmd_rcgr =3D 0x826c, - .mnd_width =3D 16, - .hid_width =3D 5, - .parent_map =3D disp_cc_parent_map_1, - .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx2_pixel1_clk_src", - .parent_data =3D disp_cc_parent_data_1, - .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_dp_ops, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src =3D { - .cmd_rcgr =3D 0x82d0, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D disp_cc_parent_map_0, - .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx3_aux_clk_src", - .parent_data =3D disp_cc_parent_data_0, - .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src =3D { - .cmd_rcgr =3D 0x82b4, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D disp_cc_parent_map_3, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx3_link_clk_src", - .parent_data =3D disp_cc_parent_data_3, - .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_byte2_ops, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src =3D { - .cmd_rcgr =3D 0x829c, - .mnd_width =3D 16, - .hid_width =3D 5, - .parent_map =3D disp_cc_parent_map_1, - .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx3_pixel0_clk_src", - .parent_data =3D disp_cc_parent_data_1, - .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_dp_ops, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_esc0_clk_src =3D { - .cmd_rcgr =3D 0x8140, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D disp_cc_parent_map_5, - .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_esc0_clk_src", - .parent_data =3D disp_cc_parent_data_5, - .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_5), - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_esc1_clk_src =3D { - .cmd_rcgr =3D 0x8158, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D disp_cc_parent_map_5, - .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_esc1_clk_src", - .parent_data =3D disp_cc_parent_data_5, - .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_5), - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, - }, -}; - -static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] =3D { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), - F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), - F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), - F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), - F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), - F(402000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), - F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), - { } -}; - -static struct clk_rcg2 disp_cc_mdss_mdp_clk_src =3D { - .cmd_rcgr =3D 0x80d8, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D disp_cc_parent_map_8, - .freq_tbl =3D ftbl_disp_cc_mdss_mdp_clk_src, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_mdp_clk_src", - .parent_data =3D disp_cc_parent_data_8, - .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_8), - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src =3D { - .cmd_rcgr =3D 0x80a8, - .mnd_width =3D 8, - .hid_width =3D 5, - .parent_map =3D disp_cc_parent_map_2, - .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_pclk0_clk_src", - .parent_data =3D disp_cc_parent_data_2, - .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_2), - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_pixel_ops, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src =3D { - .cmd_rcgr =3D 0x80c0, - .mnd_width =3D 8, - .hid_width =3D 5, - .parent_map =3D disp_cc_parent_map_2, - .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_pclk1_clk_src", - .parent_data =3D disp_cc_parent_data_2, - .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_2), - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_pixel_ops, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_vsync_clk_src =3D { - .cmd_rcgr =3D 0x80f0, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D disp_cc_parent_map_0, - .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_vsync_clk_src", - .parent_data =3D disp_cc_parent_data_0, - .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, - }, -}; - -static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] =3D { - F(32000, P_SLEEP_CLK, 1, 0, 0), - { } -}; - -static struct clk_rcg2 disp_cc_sleep_clk_src =3D { - .cmd_rcgr =3D 0xe05c, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D disp_cc_parent_map_9, - .freq_tbl =3D ftbl_disp_cc_sleep_clk_src, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_sleep_clk_src", - .parent_data =3D disp_cc_parent_data_9, - .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_9), - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 disp_cc_xo_clk_src =3D { - .cmd_rcgr =3D 0xe03c, - .mnd_width =3D 0, - .hid_width =3D 5, - .parent_map =3D disp_cc_parent_map_0, - .freq_tbl =3D ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_xo_clk_src", - .parent_data =3D disp_cc_parent_data_0_ao, - .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0_ao), - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, - }, -}; - -static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src =3D { - .reg =3D 0x8120, - .shift =3D 0, - .width =3D 4, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_byte0_div_clk_src", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_byte0_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .ops =3D &clk_regmap_div_ops, - }, -}; - -static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src =3D { - .reg =3D 0x813c, - .shift =3D 0, - .width =3D 4, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_byte1_div_clk_src", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_byte1_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .ops =3D &clk_regmap_div_ops, - }, -}; - -static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src =3D { - .reg =3D 0x8188, - .shift =3D 0, - .width =3D 4, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx0_link_div_clk_src", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_regmap_div_ro_ops, - }, -}; - -static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src =3D { - .reg =3D 0x821c, - .shift =3D 0, - .width =3D 4, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx1_link_div_clk_src", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_regmap_div_ro_ops, - }, -}; - -static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src =3D { - .reg =3D 0x8250, - .shift =3D 0, - .width =3D 4, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx2_link_div_clk_src", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_regmap_div_ro_ops, - }, -}; - -static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src =3D { - .reg =3D 0x82cc, - .shift =3D 0, - .width =3D 4, - .clkr.hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx3_link_div_clk_src", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_regmap_div_ro_ops, - }, -}; - -static struct clk_branch disp_cc_mdss_accu_clk =3D { - .halt_reg =3D 0xe058, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0xe058, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_accu_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_xo_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_ahb1_clk =3D { - .halt_reg =3D 0xa020, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0xa020, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_ahb1_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_ahb_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_ahb_clk =3D { - .halt_reg =3D 0x80a4, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x80a4, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_ahb_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_ahb_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_byte0_clk =3D { - .halt_reg =3D 0x8028, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8028, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_byte0_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_byte0_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_byte0_intf_clk =3D { - .halt_reg =3D 0x802c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x802c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_byte0_intf_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_byte0_div_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_byte1_clk =3D { - .halt_reg =3D 0x8030, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8030, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_byte1_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_byte1_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_byte1_intf_clk =3D { - .halt_reg =3D 0x8034, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8034, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_byte1_intf_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_byte1_div_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dptx0_aux_clk =3D { - .halt_reg =3D 0x8058, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8058, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx0_aux_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dptx0_crypto_clk =3D { - .halt_reg =3D 0x804c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x804c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx0_crypto_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dptx0_link_clk =3D { - .halt_reg =3D 0x8040, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8040, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx0_link_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk =3D { - .halt_reg =3D 0x8048, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8048, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx0_link_intf_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk =3D { - .halt_reg =3D 0x8050, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8050, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx0_pixel0_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk =3D { - .halt_reg =3D 0x8054, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8054, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx0_pixel1_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk =3D { - .halt_reg =3D 0x8044, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8044, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx0_usb_router_link_intf_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dptx1_aux_clk =3D { - .halt_reg =3D 0x8074, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8074, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx1_aux_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dptx1_crypto_clk =3D { - .halt_reg =3D 0x8070, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8070, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx1_crypto_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dptx1_link_clk =3D { - .halt_reg =3D 0x8064, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8064, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx1_link_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk =3D { - .halt_reg =3D 0x806c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x806c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx1_link_intf_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk =3D { - .halt_reg =3D 0x805c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x805c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx1_pixel0_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk =3D { - .halt_reg =3D 0x8060, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8060, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx1_pixel1_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk =3D { - .halt_reg =3D 0x8068, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8068, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx1_usb_router_link_intf_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dptx2_aux_clk =3D { - .halt_reg =3D 0x808c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x808c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx2_aux_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dptx2_crypto_clk =3D { - .halt_reg =3D 0x8088, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8088, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx2_crypto_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dptx2_link_clk =3D { - .halt_reg =3D 0x8080, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8080, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx2_link_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk =3D { - .halt_reg =3D 0x8084, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8084, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx2_link_intf_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk =3D { - .halt_reg =3D 0x8078, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8078, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx2_pixel0_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk =3D { - .halt_reg =3D 0x807c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x807c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx2_pixel1_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dptx3_aux_clk =3D { - .halt_reg =3D 0x809c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x809c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx3_aux_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dptx3_crypto_clk =3D { - .halt_reg =3D 0x80a0, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x80a0, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx3_crypto_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dptx3_link_clk =3D { - .halt_reg =3D 0x8094, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8094, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx3_link_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk =3D { - .halt_reg =3D 0x8098, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8098, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx3_link_intf_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk =3D { - .halt_reg =3D 0x8090, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8090, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_dptx3_pixel0_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_esc0_clk =3D { - .halt_reg =3D 0x8038, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8038, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_esc0_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_esc0_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_esc1_clk =3D { - .halt_reg =3D 0x803c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x803c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_esc1_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_esc1_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_mdp1_clk =3D { - .halt_reg =3D 0xa004, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0xa004, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_mdp1_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_mdp_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_mdp_clk =3D { - .halt_reg =3D 0x800c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x800c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_mdp_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_mdp_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_mdp_lut1_clk =3D { - .halt_reg =3D 0xa010, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0xa010, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_mdp_lut1_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_mdp_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_mdp_lut_clk =3D { - .halt_reg =3D 0x8018, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x8018, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_mdp_lut_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_mdp_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk =3D { - .halt_reg =3D 0xc004, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0xc004, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_non_gdsc_ahb_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_ahb_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_pclk0_clk =3D { - .halt_reg =3D 0x8004, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8004, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_pclk0_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_pclk0_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_pclk1_clk =3D { - .halt_reg =3D 0x8008, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8008, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_pclk1_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_pclk1_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_rscc_ahb_clk =3D { - .halt_reg =3D 0xc00c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0xc00c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_rscc_ahb_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_ahb_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_rscc_vsync_clk =3D { - .halt_reg =3D 0xc008, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0xc008, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_rscc_vsync_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_vsync_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_vsync1_clk =3D { - .halt_reg =3D 0xa01c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0xa01c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_vsync1_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_vsync_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_vsync_clk =3D { - .halt_reg =3D 0x8024, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x8024, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_mdss_vsync_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_mdss_vsync_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_sleep_clk =3D { - .halt_reg =3D 0xe074, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0xe074, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "disp_cc_sleep_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &disp_cc_sleep_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct gdsc mdss_gdsc =3D { - .gdscr =3D 0x9000, - .pd =3D { - .name =3D "mdss_gdsc", - }, - .pwrsts =3D PWRSTS_OFF_ON, - .flags =3D POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE, -}; - -static struct gdsc mdss_int2_gdsc =3D { - .gdscr =3D 0xb000, - .pd =3D { - .name =3D "mdss_int2_gdsc", - }, - .pwrsts =3D PWRSTS_OFF_ON, - .flags =3D POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE, -}; - -static struct clk_regmap *disp_cc_sm8650_clocks[] =3D { - [DISP_CC_MDSS_ACCU_CLK] =3D &disp_cc_mdss_accu_clk.clkr, - [DISP_CC_MDSS_AHB1_CLK] =3D &disp_cc_mdss_ahb1_clk.clkr, - [DISP_CC_MDSS_AHB_CLK] =3D &disp_cc_mdss_ahb_clk.clkr, - [DISP_CC_MDSS_AHB_CLK_SRC] =3D &disp_cc_mdss_ahb_clk_src.clkr, - [DISP_CC_MDSS_BYTE0_CLK] =3D &disp_cc_mdss_byte0_clk.clkr, - [DISP_CC_MDSS_BYTE0_CLK_SRC] =3D &disp_cc_mdss_byte0_clk_src.clkr, - [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] =3D &disp_cc_mdss_byte0_div_clk_src.clkr, - [DISP_CC_MDSS_BYTE0_INTF_CLK] =3D &disp_cc_mdss_byte0_intf_clk.clkr, - [DISP_CC_MDSS_BYTE1_CLK] =3D &disp_cc_mdss_byte1_clk.clkr, - [DISP_CC_MDSS_BYTE1_CLK_SRC] =3D &disp_cc_mdss_byte1_clk_src.clkr, - [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] =3D &disp_cc_mdss_byte1_div_clk_src.clkr, - [DISP_CC_MDSS_BYTE1_INTF_CLK] =3D &disp_cc_mdss_byte1_intf_clk.clkr, - [DISP_CC_MDSS_DPTX0_AUX_CLK] =3D &disp_cc_mdss_dptx0_aux_clk.clkr, - [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] =3D &disp_cc_mdss_dptx0_aux_clk_src.clkr, - [DISP_CC_MDSS_DPTX0_CRYPTO_CLK] =3D &disp_cc_mdss_dptx0_crypto_clk.clkr, - [DISP_CC_MDSS_DPTX0_LINK_CLK] =3D &disp_cc_mdss_dptx0_link_clk.clkr, - [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] =3D &disp_cc_mdss_dptx0_link_clk_src.cl= kr, - [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] =3D &disp_cc_mdss_dptx0_link_div_cl= k_src.clkr, - [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] =3D &disp_cc_mdss_dptx0_link_intf_clk.= clkr, - [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] =3D &disp_cc_mdss_dptx0_pixel0_clk.clkr, - [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] =3D &disp_cc_mdss_dptx0_pixel0_clk_sr= c.clkr, - [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] =3D &disp_cc_mdss_dptx0_pixel1_clk.clkr, - [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] =3D &disp_cc_mdss_dptx0_pixel1_clk_sr= c.clkr, - [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =3D - &disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, - [DISP_CC_MDSS_DPTX1_AUX_CLK] =3D &disp_cc_mdss_dptx1_aux_clk.clkr, - [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] =3D &disp_cc_mdss_dptx1_aux_clk_src.clkr, - [DISP_CC_MDSS_DPTX1_CRYPTO_CLK] =3D &disp_cc_mdss_dptx1_crypto_clk.clkr, - [DISP_CC_MDSS_DPTX1_LINK_CLK] =3D &disp_cc_mdss_dptx1_link_clk.clkr, - [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] =3D &disp_cc_mdss_dptx1_link_clk_src.cl= kr, - [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] =3D &disp_cc_mdss_dptx1_link_div_cl= k_src.clkr, - [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] =3D &disp_cc_mdss_dptx1_link_intf_clk.= clkr, - [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] =3D &disp_cc_mdss_dptx1_pixel0_clk.clkr, - [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] =3D &disp_cc_mdss_dptx1_pixel0_clk_sr= c.clkr, - [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] =3D &disp_cc_mdss_dptx1_pixel1_clk.clkr, - [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] =3D &disp_cc_mdss_dptx1_pixel1_clk_sr= c.clkr, - [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] =3D - &disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr, - [DISP_CC_MDSS_DPTX2_AUX_CLK] =3D &disp_cc_mdss_dptx2_aux_clk.clkr, - [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] =3D &disp_cc_mdss_dptx2_aux_clk_src.clkr, - [DISP_CC_MDSS_DPTX2_CRYPTO_CLK] =3D &disp_cc_mdss_dptx2_crypto_clk.clkr, - [DISP_CC_MDSS_DPTX2_LINK_CLK] =3D &disp_cc_mdss_dptx2_link_clk.clkr, - [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] =3D &disp_cc_mdss_dptx2_link_clk_src.cl= kr, - [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] =3D &disp_cc_mdss_dptx2_link_div_cl= k_src.clkr, - [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] =3D &disp_cc_mdss_dptx2_link_intf_clk.= clkr, - [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] =3D &disp_cc_mdss_dptx2_pixel0_clk.clkr, - [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] =3D &disp_cc_mdss_dptx2_pixel0_clk_sr= c.clkr, - [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] =3D &disp_cc_mdss_dptx2_pixel1_clk.clkr, - [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] =3D &disp_cc_mdss_dptx2_pixel1_clk_sr= c.clkr, - [DISP_CC_MDSS_DPTX3_AUX_CLK] =3D &disp_cc_mdss_dptx3_aux_clk.clkr, - [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] =3D &disp_cc_mdss_dptx3_aux_clk_src.clkr, - [DISP_CC_MDSS_DPTX3_CRYPTO_CLK] =3D &disp_cc_mdss_dptx3_crypto_clk.clkr, - [DISP_CC_MDSS_DPTX3_LINK_CLK] =3D &disp_cc_mdss_dptx3_link_clk.clkr, - [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] =3D &disp_cc_mdss_dptx3_link_clk_src.cl= kr, - [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] =3D &disp_cc_mdss_dptx3_link_div_cl= k_src.clkr, - [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] =3D &disp_cc_mdss_dptx3_link_intf_clk.= clkr, - [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] =3D &disp_cc_mdss_dptx3_pixel0_clk.clkr, - [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] =3D &disp_cc_mdss_dptx3_pixel0_clk_sr= c.clkr, - [DISP_CC_MDSS_ESC0_CLK] =3D &disp_cc_mdss_esc0_clk.clkr, - [DISP_CC_MDSS_ESC0_CLK_SRC] =3D &disp_cc_mdss_esc0_clk_src.clkr, - [DISP_CC_MDSS_ESC1_CLK] =3D &disp_cc_mdss_esc1_clk.clkr, - [DISP_CC_MDSS_ESC1_CLK_SRC] =3D &disp_cc_mdss_esc1_clk_src.clkr, - [DISP_CC_MDSS_MDP1_CLK] =3D &disp_cc_mdss_mdp1_clk.clkr, - [DISP_CC_MDSS_MDP_CLK] =3D &disp_cc_mdss_mdp_clk.clkr, - [DISP_CC_MDSS_MDP_CLK_SRC] =3D &disp_cc_mdss_mdp_clk_src.clkr, - [DISP_CC_MDSS_MDP_LUT1_CLK] =3D &disp_cc_mdss_mdp_lut1_clk.clkr, - [DISP_CC_MDSS_MDP_LUT_CLK] =3D &disp_cc_mdss_mdp_lut_clk.clkr, - [DISP_CC_MDSS_NON_GDSC_AHB_CLK] =3D &disp_cc_mdss_non_gdsc_ahb_clk.clkr, - [DISP_CC_MDSS_PCLK0_CLK] =3D &disp_cc_mdss_pclk0_clk.clkr, - [DISP_CC_MDSS_PCLK0_CLK_SRC] =3D &disp_cc_mdss_pclk0_clk_src.clkr, - [DISP_CC_MDSS_PCLK1_CLK] =3D &disp_cc_mdss_pclk1_clk.clkr, - [DISP_CC_MDSS_PCLK1_CLK_SRC] =3D &disp_cc_mdss_pclk1_clk_src.clkr, - [DISP_CC_MDSS_RSCC_AHB_CLK] =3D &disp_cc_mdss_rscc_ahb_clk.clkr, - [DISP_CC_MDSS_RSCC_VSYNC_CLK] =3D &disp_cc_mdss_rscc_vsync_clk.clkr, - [DISP_CC_MDSS_VSYNC1_CLK] =3D &disp_cc_mdss_vsync1_clk.clkr, - [DISP_CC_MDSS_VSYNC_CLK] =3D &disp_cc_mdss_vsync_clk.clkr, - [DISP_CC_MDSS_VSYNC_CLK_SRC] =3D &disp_cc_mdss_vsync_clk_src.clkr, - [DISP_CC_PLL0] =3D &disp_cc_pll0.clkr, - [DISP_CC_PLL1] =3D &disp_cc_pll1.clkr, - [DISP_CC_SLEEP_CLK] =3D &disp_cc_sleep_clk.clkr, - [DISP_CC_SLEEP_CLK_SRC] =3D &disp_cc_sleep_clk_src.clkr, - [DISP_CC_XO_CLK_SRC] =3D &disp_cc_xo_clk_src.clkr, -}; - -static const struct qcom_reset_map disp_cc_sm8650_resets[] =3D { - [DISP_CC_MDSS_CORE_BCR] =3D { 0x8000 }, - [DISP_CC_MDSS_CORE_INT2_BCR] =3D { 0xa000 }, - [DISP_CC_MDSS_RSCC_BCR] =3D { 0xc000 }, -}; - -static struct gdsc *disp_cc_sm8650_gdscs[] =3D { - [MDSS_GDSC] =3D &mdss_gdsc, - [MDSS_INT2_GDSC] =3D &mdss_int2_gdsc, -}; - -static const struct regmap_config disp_cc_sm8650_regmap_config =3D { - .reg_bits =3D 32, - .reg_stride =3D 4, - .val_bits =3D 32, - .max_register =3D 0x11008, - .fast_io =3D true, -}; - -static struct qcom_cc_desc disp_cc_sm8650_desc =3D { - .config =3D &disp_cc_sm8650_regmap_config, - .clks =3D disp_cc_sm8650_clocks, - .num_clks =3D ARRAY_SIZE(disp_cc_sm8650_clocks), - .resets =3D disp_cc_sm8650_resets, - .num_resets =3D ARRAY_SIZE(disp_cc_sm8650_resets), - .gdscs =3D disp_cc_sm8650_gdscs, - .num_gdscs =3D ARRAY_SIZE(disp_cc_sm8650_gdscs), -}; - -static const struct of_device_id disp_cc_sm8650_match_table[] =3D { - { .compatible =3D "qcom,sm8650-dispcc" }, - { } -}; -MODULE_DEVICE_TABLE(of, disp_cc_sm8650_match_table); - -static int disp_cc_sm8650_probe(struct platform_device *pdev) -{ - struct regmap *regmap; - int ret; - - ret =3D devm_pm_runtime_enable(&pdev->dev); - if (ret) - return ret; - - ret =3D pm_runtime_resume_and_get(&pdev->dev); - if (ret) - return ret; - - regmap =3D qcom_cc_map(pdev, &disp_cc_sm8650_desc); - if (IS_ERR(regmap)) { - ret =3D PTR_ERR(regmap); - goto err_put_rpm; - } - - clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); - clk_lucid_ole_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); - - /* Enable clock gating for MDP clocks */ - regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); - - /* Keep some clocks always-on */ - qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */ - - ret =3D qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8650_desc, regmap); - if (ret) - goto err_put_rpm; - - pm_runtime_put(&pdev->dev); - - return 0; - -err_put_rpm: - pm_runtime_put_sync(&pdev->dev); - - return ret; -} - -static struct platform_driver disp_cc_sm8650_driver =3D { - .probe =3D disp_cc_sm8650_probe, - .driver =3D { - .name =3D "disp_cc-sm8650", - .of_match_table =3D disp_cc_sm8650_match_table, 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smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52ed253924asm1425391e87.262.2024.07.17.03.04.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Jul 2024 03:04:37 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 17 Jul 2024 13:04:34 +0300 Subject: [PATCH v2 7/7] dt-bindings: clock: qcom,sm8650-dispcc: replace with symlink Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240717-dispcc-sm8550-fixes-v2-7-5c4a3128c40b@linaro.org> References: <20240717-dispcc-sm8550-fixes-v2-0-5c4a3128c40b@linaro.org> In-Reply-To: <20240717-dispcc-sm8550-fixes-v2-0-5c4a3128c40b@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Neil Armstrong , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5097; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=Rks5U6PDlX023HI5XO41XNs0HluLCmpOuaHzGf+O+RI=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBml5cumjXDiqUDeaTnkOwBbgAiBvt3/BiawV0+4 vNaAZm9LGOJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZpeXLgAKCRCLPIo+Aiko 1QqgB/9Zo5Ua2kMBkjo2TX2ytRlJEYg3mdFcP2dEyrA8cWqHyVC5hPGIi5DH+KwoemoIeD4sKm7 L8/m3rVWLKQ/hYJ+H2P924jGuOv6K92QEyZwtR4WBVQ7bsbJmwKHhwDi4bOj8Nz7TWHvfVH9QlS fYlPvH9DMtG4N1k6DfaGfEApfGGs1ahaYpzBPwt6mL8rPnVzbMznIhnl0YbwncTErtpOhXTF3LO NGSr50Xoe22EhnCUUxQp/9zdr84SPDof8Ql6a3bIMqC4BbRs3zpMpvKFGF0VrKyYklSp+cLM+UR OHjkeocm6ucOSxTCutGeFUyvu8/r9D+UiAWVNxwc7GZ7oMUi X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The display clock controller indices for SM8650 and SM8550 are completely equal. Replace the header file for qcom,sm8650-dispcc with the symlink to the qcom,sm8550-dispcc header file. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong --- include/dt-bindings/clock/qcom,sm8650-dispcc.h | 103 +--------------------= ---- 1 file changed, 1 insertion(+), 102 deletions(-) diff --git a/include/dt-bindings/clock/qcom,sm8650-dispcc.h b/include/dt-bi= ndings/clock/qcom,sm8650-dispcc.h deleted file mode 100644 index b0a668b395a5..000000000000 --- a/include/dt-bindings/clock/qcom,sm8650-dispcc.h +++ /dev/null @@ -1,102 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved - * Copyright (c) 2023, Linaro Ltd. - */ - -#ifndef _DT_BINDINGS_CLK_QCOM_SM8650_DISP_CC_H -#define _DT_BINDINGS_CLK_QCOM_SM8650_DISP_CC_H - -/* DISP_CC clocks */ -#define DISP_CC_MDSS_ACCU_CLK 0 -#define DISP_CC_MDSS_AHB1_CLK 1 -#define DISP_CC_MDSS_AHB_CLK 2 -#define DISP_CC_MDSS_AHB_CLK_SRC 3 -#define DISP_CC_MDSS_BYTE0_CLK 4 -#define DISP_CC_MDSS_BYTE0_CLK_SRC 5 -#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6 -#define DISP_CC_MDSS_BYTE0_INTF_CLK 7 -#define DISP_CC_MDSS_BYTE1_CLK 8 -#define DISP_CC_MDSS_BYTE1_CLK_SRC 9 -#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 10 -#define DISP_CC_MDSS_BYTE1_INTF_CLK 11 -#define DISP_CC_MDSS_DPTX0_AUX_CLK 12 -#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 13 -#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 14 -#define DISP_CC_MDSS_DPTX0_LINK_CLK 15 -#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 16 -#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 17 -#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 18 -#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 19 -#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 20 -#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 21 -#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 22 -#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 23 -#define DISP_CC_MDSS_DPTX1_AUX_CLK 24 -#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 25 -#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 26 -#define DISP_CC_MDSS_DPTX1_LINK_CLK 27 -#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 28 -#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 29 -#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 30 -#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 31 -#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 32 -#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 33 -#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 34 -#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 35 -#define DISP_CC_MDSS_DPTX2_AUX_CLK 36 -#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 37 -#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 38 -#define DISP_CC_MDSS_DPTX2_LINK_CLK 39 -#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 40 -#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 41 -#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 42 -#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 43 -#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 44 -#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 45 -#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 46 -#define DISP_CC_MDSS_DPTX3_AUX_CLK 47 -#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 48 -#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 49 -#define DISP_CC_MDSS_DPTX3_LINK_CLK 50 -#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 51 -#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 52 -#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 53 -#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 54 -#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 55 -#define DISP_CC_MDSS_ESC0_CLK 56 -#define DISP_CC_MDSS_ESC0_CLK_SRC 57 -#define DISP_CC_MDSS_ESC1_CLK 58 -#define DISP_CC_MDSS_ESC1_CLK_SRC 59 -#define DISP_CC_MDSS_MDP1_CLK 60 -#define DISP_CC_MDSS_MDP_CLK 61 -#define DISP_CC_MDSS_MDP_CLK_SRC 62 -#define DISP_CC_MDSS_MDP_LUT1_CLK 63 -#define DISP_CC_MDSS_MDP_LUT_CLK 64 -#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 65 -#define DISP_CC_MDSS_PCLK0_CLK 66 -#define DISP_CC_MDSS_PCLK0_CLK_SRC 67 -#define DISP_CC_MDSS_PCLK1_CLK 68 -#define DISP_CC_MDSS_PCLK1_CLK_SRC 69 -#define DISP_CC_MDSS_RSCC_AHB_CLK 70 -#define DISP_CC_MDSS_RSCC_VSYNC_CLK 71 -#define DISP_CC_MDSS_VSYNC1_CLK 72 -#define DISP_CC_MDSS_VSYNC_CLK 73 -#define DISP_CC_MDSS_VSYNC_CLK_SRC 74 -#define DISP_CC_PLL0 75 -#define DISP_CC_PLL1 76 -#define DISP_CC_SLEEP_CLK 77 -#define DISP_CC_SLEEP_CLK_SRC 78 -#define DISP_CC_XO_CLK 79 -#define DISP_CC_XO_CLK_SRC 80 - -/* DISP_CC resets */ -#define DISP_CC_MDSS_CORE_BCR 0 -#define DISP_CC_MDSS_CORE_INT2_BCR 1 -#define DISP_CC_MDSS_RSCC_BCR 2 - -/* DISP_CC GDSCR */ -#define MDSS_GDSC 0 -#define MDSS_INT2_GDSC 1 - -#endif diff --git a/include/dt-bindings/clock/qcom,sm8650-dispcc.h b/include/dt-bi= ndings/clock/qcom,sm8650-dispcc.h new file mode 120000 index 000000000000..c0a291188f28 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8650-dispcc.h @@ -0,0 +1 @@ +qcom,sm8550-dispcc.h \ No newline at end of file --=20 2.39.2