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([82.78.167.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427a5e77488sm121546145e9.9.2024.07.16.03.30.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 03:30:36 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 01/11] dt-bindings: mfd: renesas,r9a08g045-vbattb: Document VBATTB Date: Tue, 16 Jul 2024 13:30:15 +0300 Message-Id: <20240716103025.1198495-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> References: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC, the tamper detector and a small general usage memory of 128B. Add documentation for it. Signed-off-by: Claudiu Beznea --- Changes in v2: - changed file name and compatible - updated title, description sections - added clock controller part documentation and drop dedicated file for it included in v1 - used items to describe interrupts, interrupt-names, clocks, clock-names, resets - dropped node labels and status - updated clock-names for clock controller to cope with the new logic on detecting the necessity to setup bypass .../mfd/renesas,r9a08g045-vbattb.yaml | 136 ++++++++++++++++++ 1 file changed, 136 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/renesas,r9a08g045= -vbattb.yaml diff --git a/Documentation/devicetree/bindings/mfd/renesas,r9a08g045-vbattb= .yaml b/Documentation/devicetree/bindings/mfd/renesas,r9a08g045-vbattb.yaml new file mode 100644 index 000000000000..30e4da65e2f6 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/renesas,r9a08g045-vbattb.yaml @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/renesas,r9a08g045-vbattb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Battery Backup Function (VBATTB) + +description: + Renesas VBATTB is an always on powered module (backed by battery) which + controls the RTC clock (VBATTCLK), tamper detection logic and a small + general usage memory (128B). + +maintainers: + - Claudiu Beznea + +properties: + compatible: + const: renesas,r9a08g045-vbattb + + reg: + maxItems: 1 + + ranges: true + + interrupts: + items: + - description: tamper detector interrupt + + interrupt-names: + items: + - const: tampdi + + clocks: + items: + - description: VBATTB module clock + + clock-names: + items: + - const: bclk + + power-domains: + maxItems: 1 + + resets: + items: + - description: VBATTB module reset + + '#address-cells': + const: 2 + + '#size-cells': + const: 2 + +patternProperties: + "^clock-controller@1c+$": + type: object + description: VBATTCLK clock + + properties: + compatible: + const: renesas,r9a08g045-vbattb-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: input clock for VBATTCLK + + clock-names: + description: | + Use xin if connected to an external crystal oscillator. + Use clkin if connected to an external hardware device generating= the + clock. + enum: + - xin + - clkin + + '#clock-cells': + const: 0 + + renesas,vbattb-load-nanofarads: + description: load capacitance of the on board xtal + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 4000, 7000, 9000, 12500 ] + + required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - renesas,vbattb-load-nanofarads + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include + #include + + vbattb@1005c000 { + compatible =3D "renesas,r9a08g045-vbattb"; + reg =3D <0x1005c000 0x1000>; + ranges =3D <0 0 0x1005c000 0 0x1000>; + interrupts =3D ; + interrupt-names =3D "tampdi"; + clocks =3D <&cpg CPG_MOD R9A08G045_VBAT_BCLK>; + clock-names =3D "bclk"; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A08G045_VBAT_BRESETN>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@1c { + compatible =3D "renesas,r9a08g045-vbattb-clk"; + reg =3D <0 0x1c 0 0x10>; + clocks =3D <&vbattb_xtal>; + clock-names =3D "xin"; + #clock-cells =3D <0>; + renesas,vbattb-load-nanofarads =3D <12500>; + }; + }; --=20 2.39.2 From nobody Wed Dec 17 15:39:51 2025 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF94F198E76 for ; Tue, 16 Jul 2024 10:30:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; 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([82.78.167.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427a5e77488sm121546145e9.9.2024.07.16.03.30.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 03:30:38 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 02/11] mfd: renesas-vbattb: Add a MFD driver for the Renesas VBATTB IP Date: Tue, 16 Jul 2024 13:30:16 +0300 Message-Id: <20240716103025.1198495-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> References: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Renesas VBATTB IP has logic to control the RTC clock, tamper detection and a small 128B memory. Add a MFD driver to do the basic initialization of the VBATTB IP for the inner components to work. Signed-off-by: Claudiu Beznea --- Changes in v2: - none; this driver is new drivers/mfd/Kconfig | 8 ++++ drivers/mfd/Makefile | 1 + drivers/mfd/renesas-vbattb.c | 78 ++++++++++++++++++++++++++++++++++++ 3 files changed, 87 insertions(+) create mode 100644 drivers/mfd/renesas-vbattb.c diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index bc8be2e593b6..df93e8b05065 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1383,6 +1383,14 @@ config MFD_SC27XX_PMIC This driver provides common support for accessing the SC27xx PMICs, and it also adds the irq_chip parts for handling the PMIC chip events. =20 +config MFD_RENESAS_VBATTB + tristate "Renesas VBATTB driver" + depends on (ARCH_RZG2L && OF) || COMPILE_TEST + select MFD_CORE + help + Select this option to enable Renesas RZ/G3S VBATTB driver which + provides support for the RTC clock, tamper detector and 128B SRAM. + config RZ_MTU3 tristate "Renesas RZ/G2L MTU3a core driver" depends on (ARCH_RZG2L && OF) || COMPILE_TEST diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 02b651cd7535..cd2f27492df2 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -186,6 +186,7 @@ pcf50633-objs :=3D pcf50633-core.o pcf50633-irq.o obj-$(CONFIG_MFD_PCF50633) +=3D pcf50633.o obj-$(CONFIG_PCF50633_ADC) +=3D pcf50633-adc.o obj-$(CONFIG_PCF50633_GPIO) +=3D pcf50633-gpio.o +obj-$(CONFIG_MFD_RENESAS_VBATTB) +=3D renesas-vbattb.o obj-$(CONFIG_RZ_MTU3) +=3D rz-mtu3.o obj-$(CONFIG_ABX500_CORE) +=3D abx500-core.o obj-$(CONFIG_MFD_DB8500_PRCMU) +=3D db8500-prcmu.o diff --git a/drivers/mfd/renesas-vbattb.c b/drivers/mfd/renesas-vbattb.c new file mode 100644 index 000000000000..5d71565b8cbf --- /dev/null +++ b/drivers/mfd/renesas-vbattb.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * VBATTB driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include + +static int vbattb_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct reset_control *rstc; + int ret; + + rstc =3D devm_reset_control_array_get_exclusive(dev); + if (IS_ERR(rstc)) + return PTR_ERR(rstc); + + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + ret =3D reset_control_deassert(rstc); + if (ret) + goto rpm_put; + + platform_set_drvdata(pdev, rstc); + + ret =3D devm_of_platform_populate(dev); + if (ret) + goto reset_assert; + + return 0; + +reset_assert: + reset_control_assert(rstc); +rpm_put: + pm_runtime_put(dev); + return ret; +} + +static void vbattb_remove(struct platform_device *pdev) +{ + struct reset_control *rstc =3D platform_get_drvdata(pdev); + + reset_control_assert(rstc); + pm_runtime_put(&pdev->dev); +} + +static const struct of_device_id vbattb_match[] =3D { + { .compatible =3D "renesas,r9a08g045-vbattb" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, vbattb_match); + +static struct platform_driver vbattb_driver =3D { + .probe =3D vbattb_probe, + .remove_new =3D vbattb_remove, + .driver =3D { + .name =3D "renesas-vbattb", + .of_match_table =3D vbattb_match, + }, +}; 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([82.78.167.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427a5e77488sm121546145e9.9.2024.07.16.03.30.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 03:30:40 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 03/11] clk: renesas: clk-vbattb: Add VBATTB clock driver Date: Tue, 16 Jul 2024 13:30:17 +0300 Message-Id: <20240716103025.1198495-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> References: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that is used by the RTC. The input to the VBATTB could be a 32KHz crystal oscillator or an external clock device. The driver detects the type of the input clock based on the device tree clock name (xin for crystal, clkin for external clock device). The load capacitance of the on-board oscillator need to be configured with renesas,vbattb-load-nanofarads DT property. Signed-off-by: Claudiu Beznea --- Changes in v2: - updated patch description - added vendor name in Kconfig flag - used cleanup.h lock helpers - dropped the MFD code - updated registers offsets - added vbattb_clk_update_bits() and used it where possible - added vbattb_clk_need_bypass() to detect the bypass setup necessity - changed the compatible and driver names drivers/clk/renesas/Kconfig | 5 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/clk-vbattb.c | 212 +++++++++++++++++++++++++++++++ 3 files changed, 218 insertions(+) create mode 100644 drivers/clk/renesas/clk-vbattb.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 4410d16de4e2..1f5f38136eb2 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -228,6 +228,11 @@ config CLK_RZG2L bool "RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST select RESET_CONTROLLER =20 +config CLK_RENESAS_VBATTB + bool "Renesas VBATTB clock controller" + depends on MFD_RENESAS_VBATTB + select RESET_CONTROLLER + # Generic config CLK_RENESAS_CPG_MSSR bool "CPG/MSSR clock support" if COMPILE_TEST diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index f7e18679c3b8..84a2783a7b46 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -51,3 +51,4 @@ obj-$(CONFIG_CLK_RZG2L) +=3D rzg2l-cpg.o obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) +=3D renesas-cpg-mssr.o obj-$(CONFIG_CLK_RENESAS_CPG_MSTP) +=3D clk-mstp.o obj-$(CONFIG_CLK_RENESAS_DIV6) +=3D clk-div6.o +obj-$(CONFIG_CLK_RENESAS_VBATTB) +=3D clk-vbattb.o diff --git a/drivers/clk/renesas/clk-vbattb.c b/drivers/clk/renesas/clk-vba= ttb.c new file mode 100644 index 000000000000..8effe141fc0b --- /dev/null +++ b/drivers/clk/renesas/clk-vbattb.c @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * VBATTB clock driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define VBATTB_BKSCCR 0x0 +#define VBATTB_BKSCCR_SOSEL BIT(6) +#define VBATTB_SOSCCR2 0x8 +#define VBATTB_SOSCCR2_SOSTP2 BIT(0) +#define VBATTB_XOSCCR 0x14 +#define VBATTB_XOSCCR_OUTEN BIT(16) +#define VBATTB_XOSCCR_XSEL GENMASK(1, 0) +#define VBATTB_XOSCCR_XSEL_4_PF 0x0 +#define VBATTB_XOSCCR_XSEL_7_PF 0x1 +#define VBATTB_XOSCCR_XSEL_9_PF 0x2 +#define VBATTB_XOSCCR_XSEL_12_5_PF 0x3 + +/** + * struct vbattb_clk - VBATTB clock data structure + * @base: base address + * @hw: clk hw + * @lock: lock + * @load_capacitance: load capacitance + */ +struct vbattb_clk { + void __iomem *base; + struct clk_hw hw; + spinlock_t lock; + u8 load_capacitance; +}; + +#define to_vbattb_clk(_hw) container_of(_hw, struct vbattb_clk, hw) + +static void vbattb_clk_update_bits(void __iomem *base, u32 offset, u32 mas= k, u32 val) +{ + u32 tmp; + + tmp =3D readl_relaxed(base + offset); + tmp &=3D ~mask; + tmp |=3D (val & mask); + writel_relaxed(tmp, base + offset); +} + +static int vbattb_clk_enable(struct clk_hw *hw) +{ + struct vbattb_clk *vbclk =3D to_vbattb_clk(hw); + void __iomem *base =3D vbclk->base; + + guard(spinlock)(&vbclk->lock); + + vbattb_clk_update_bits(base, VBATTB_SOSCCR2, VBATTB_SOSCCR2_SOSTP2, 0); + vbattb_clk_update_bits(base, VBATTB_XOSCCR, VBATTB_XOSCCR_OUTEN | VBATTB_= XOSCCR_XSEL, + VBATTB_XOSCCR_OUTEN | vbclk->load_capacitance); + + return 0; +} + +static void vbattb_clk_disable(struct clk_hw *hw) +{ + struct vbattb_clk *vbclk =3D to_vbattb_clk(hw); + void __iomem *base =3D vbclk->base; + + guard(spinlock)(&vbclk->lock); + + vbattb_clk_update_bits(base, VBATTB_XOSCCR, VBATTB_XOSCCR_OUTEN, 0); + vbattb_clk_update_bits(base, VBATTB_SOSCCR2, VBATTB_SOSCCR2_SOSTP2, VBATT= B_SOSCCR2_SOSTP2); +} + +static int vbattb_clk_is_enabled(struct clk_hw *hw) +{ + struct vbattb_clk *vbclk =3D to_vbattb_clk(hw); + void __iomem *base =3D vbclk->base; + unsigned int xosccr, sosccr2; + + guard(spinlock)(&vbclk->lock); + + xosccr =3D readl_relaxed(base + VBATTB_XOSCCR); + sosccr2 =3D readl_relaxed(base + VBATTB_SOSCCR2); + + return ((xosccr & VBATTB_XOSCCR_OUTEN) && !(sosccr2 & VBATTB_SOSCCR2_SOST= P2)); +} + +static const struct clk_ops vbattb_clk_ops =3D { + .enable =3D vbattb_clk_enable, + .disable =3D vbattb_clk_disable, + .is_enabled =3D vbattb_clk_is_enabled, +}; + +static int vbattb_clk_validate_load_capacitance(struct vbattb_clk *vbclk, = u32 load_capacitance) +{ + switch (load_capacitance) { + case 4000: + vbclk->load_capacitance =3D VBATTB_XOSCCR_XSEL_4_PF; + break; + case 7000: + vbclk->load_capacitance =3D VBATTB_XOSCCR_XSEL_7_PF; + break; + case 9000: + vbclk->load_capacitance =3D VBATTB_XOSCCR_XSEL_9_PF; + break; + case 12500: + vbclk->load_capacitance =3D VBATTB_XOSCCR_XSEL_12_5_PF; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int vbattb_clk_need_bypass(struct device *dev) +{ + struct clk *clkin, *xin; + + clkin =3D devm_clk_get_optional(dev, "clkin"); + xin =3D devm_clk_get_optional(dev, "xin"); + + if (!IS_ERR_OR_NULL(clkin) && !IS_ERR_OR_NULL(xin)) + return -EINVAL; + else if (!clkin && !IS_ERR_OR_NULL(xin)) + return 0; + else if (!IS_ERR_OR_NULL(clkin) && !xin) + return 1; + + return -EINVAL; +} + +static int vbattb_clk_probe(struct platform_device *pdev) +{ + struct device_node *np =3D pdev->dev.of_node; + struct clk_parent_data parent_data =3D {}; + struct device *dev =3D &pdev->dev; + struct clk_init_data init =3D {}; + struct vbattb_clk *vbclk; + u32 load_capacitance; + struct clk_hw *hw; + int ret, bypass; + + vbclk =3D devm_kzalloc(dev, sizeof(*vbclk), GFP_KERNEL); + if (!vbclk) + return -ENOMEM; + + vbclk->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(vbclk->base)) + return PTR_ERR(vbclk->base); + + bypass =3D vbattb_clk_need_bypass(dev); + if (bypass < 0) { + return bypass; + } else if (bypass) { + parent_data.fw_name =3D "clkin"; + bypass =3D VBATTB_BKSCCR_SOSEL; + } else { + parent_data.fw_name =3D "xin"; + } + + ret =3D of_property_read_u32(np, "renesas,vbattb-load-nanofarads", &load_= capacitance); + if (ret) + return ret; + + ret =3D vbattb_clk_validate_load_capacitance(vbclk, load_capacitance); + if (ret) + return ret; + + vbattb_clk_update_bits(vbclk->base, VBATTB_BKSCCR, VBATTB_BKSCCR_SOSEL, b= ypass); + + spin_lock_init(&vbclk->lock); + + init.name =3D "vbattclk"; + init.ops =3D &vbattb_clk_ops; + init.parent_data =3D &parent_data; + init.num_parents =3D 1; + init.flags =3D 0; + + vbclk->hw.init =3D &init; + hw =3D &vbclk->hw; + + ret =3D devm_clk_hw_register(dev, hw); + if (ret) + return ret; + + return of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); +} + +static const struct of_device_id vbattb_clk_match[] =3D { + { .compatible =3D "renesas,r9a08g045-vbattb-clk" }, + { /* sentinel */ } +}; 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([82.78.167.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427a5e77488sm121546145e9.9.2024.07.16.03.30.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 03:30:42 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 04/11] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RTCA-3 IP Date: Tue, 16 Jul 2024 13:30:18 +0300 Message-Id: <20240716103025.1198495-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> References: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Document the RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC. The RTC IP available on Renesas RZ/V2H is almost identical with the one found on Renesas RZ/G3S (it misses the time capture functionality which is not yet implemented on proposed driver). For this, added also a generic compatible that will be used at the moment as fallback for both RZ/G3S and RZ/V2H. Signed-off-by: Claudiu Beznea Reviewed-by: Conor Dooley --- Changes in v2: - updated patch description and title - included reference to rtc.yaml - updated compatible list with a generic compatible as explained in patch description; with this the node in examples section has also been updated - used items to describe interrupts, interrupt-names, clock, clock-names - updated title section .../bindings/rtc/renesas,rz-rtca3.yaml | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.= yaml diff --git a/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml b/= Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml new file mode 100644 index 000000000000..21f104b1e86b --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/renesas,rz-rtca3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RTCA-3 Real Time Clock + +maintainers: + - Claudiu Beznea + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + items: + - enum: + - renesas,r9a08g045-rtca3 # RZ/G3S + - const: renesas,rz-rtca3 + + reg: + maxItems: 1 + + interrupts: + items: + - description: Alarm interrupt + - description: Periodic interrupt + - description: Carry interrupt + + interrupt-names: + items: + - const: alarm + - const: period + - const: carry + + clocks: + items: + - description: RTC counter clock + + clock-names: + items: + - const: counter + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + rtc@1004ec00 { + compatible =3D "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; 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([82.78.167.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427a5e77488sm121546145e9.9.2024.07.16.03.30.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 03:30:43 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 05/11] rtc: renesas-rtca3: Add driver for RTCA-3 available on Renesas RZ/G3S SoC Date: Tue, 16 Jul 2024 13:30:19 +0300 Message-Id: <20240716103025.1198495-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> References: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Claudiu Beznea The RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC has calendar count mode and binary count mode (selectable though RCR2.CNTMD) capabilities, alarm capabilities, clock error correction capabilities. It can generate alarm, period, carry interrupts. Add a driver for RTCA-3 IP. The driver implements calendar count mode (as the conversion b/w RTC and system time is simpler, done with bcd2bin(), bin2bcd()), read and set time, read and set alarm, read and set an offset. Signed-off-by: Claudiu Beznea --- Changes in v2: - used cleanup.h helpers for locking - updated the MAINTAINERS entry with the new name for RTCA-3 documentation file and a new title (from "RENESAS RZ/G3S RTC DRIVER" to "RENESAS RTCA-3 RTC DRIVER") - used 24 hours mode - changed startup sequence (rtca3_initial_setup()) to avoid stopping the RTC if it's already configured - updated the RTC range to 2000-2099 - updated the compatible with the generic one (renesas,rz-rtca3) in the idea the driver will be also used by the RZ/V2H w/o the necessity to add a new compatible MAINTAINERS | 8 + drivers/rtc/Kconfig | 10 + drivers/rtc/Makefile | 1 + drivers/rtc/rtc-renesas-rtca3.c | 853 ++++++++++++++++++++++++++++++++ 4 files changed, 872 insertions(+) create mode 100644 drivers/rtc/rtc-renesas-rtca3.c diff --git a/MAINTAINERS b/MAINTAINERS index 3c9cc609cdfd..067f080a4d30 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19419,6 +19419,14 @@ S: Supported F: Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml F: drivers/counter/rz-mtu3-cnt.c =20 +RENESAS RTCA-3 RTC DRIVER +M: Claudiu Beznea +L: linux-rtc@vger.kernel.org +L: linux-renesas-soc@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml +F: drivers/rtc/rtc-renesas-rtca3.c + RENESAS RZ/N1 A5PSW SWITCH DRIVER M: Cl=C3=A9ment L=C3=A9ger L: linux-renesas-soc@vger.kernel.org diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 2a95b05982ad..3b29b35e48e0 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1978,6 +1978,16 @@ config RTC_DRV_MA35D1 This driver can also be built as a module, if so, the module will be called "rtc-ma35d1". =20 +config RTC_DRV_RENESAS_RTCA3 + tristate "Renesas RTCA-3 RTC" + depends on ARCH_RENESAS + help + If you say yes here you get support for the Renesas RTCA-3 RTC + available on the Renesas RZ/G3S SoC. + + This driver can also be built as a module, if so, the module + will be called "rtc-rtca3". + comment "HID Sensor RTC drivers" =20 config RTC_DRV_HID_SENSOR_TIME diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 3004e372f25f..52844f13b247 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -157,6 +157,7 @@ obj-$(CONFIG_RTC_DRV_RX8025) +=3D rtc-rx8025.o obj-$(CONFIG_RTC_DRV_RX8111) +=3D rtc-rx8111.o obj-$(CONFIG_RTC_DRV_RX8581) +=3D rtc-rx8581.o obj-$(CONFIG_RTC_DRV_RZN1) +=3D rtc-rzn1.o +obj-$(CONFIG_RTC_DRV_RENESAS_RTCA3) +=3D rtc-renesas-rtca3.o obj-$(CONFIG_RTC_DRV_S35390A) +=3D rtc-s35390a.o obj-$(CONFIG_RTC_DRV_S3C) +=3D rtc-s3c.o obj-$(CONFIG_RTC_DRV_S5M) +=3D rtc-s5m.o diff --git a/drivers/rtc/rtc-renesas-rtca3.c b/drivers/rtc/rtc-renesas-rtca= 3.c new file mode 100644 index 000000000000..c25971ff847e --- /dev/null +++ b/drivers/rtc/rtc-renesas-rtca3.c @@ -0,0 +1,853 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * On-Chip RTC Support available on RZ/G3S SoC + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Counter registers. */ +#define RTCA3_RSECCNT 0x2 +#define RTCA3_RSECCNT_SEC GENMASK(6, 0) +#define RTCA3_RMINCNT 0x4 +#define RTCA3_RMINCNT_MIN GENMASK(6, 0) +#define RTCA3_RHRCNT 0x6 +#define RTCA3_RHRCNT_HR GENMASK(5, 0) +#define RTCA3_RHRCNT_PM BIT(6) +#define RTCA3_RWKCNT 0x8 +#define RTCA3_RWKCNT_WK GENMASK(2, 0) +#define RTCA3_RDAYCNT 0xa +#define RTCA3_RDAYCNT_DAY GENMASK(5, 0) +#define RTCA3_RMONCNT 0xc +#define RTCA3_RMONCNT_MONTH GENMASK(4, 0) +#define RTCA3_RYRCNT 0xe +#define RTCA3_RYRCNT_YEAR GENMASK(7, 0) + +/* Alarm registers. */ +#define RTCA3_RSECAR 0x10 +#define RTCA3_RSECAR_SEC GENMASK(6, 0) +#define RTCA3_RMINAR 0x12 +#define RTCA3_RMINAR_MIN GENMASK(6, 0) +#define RTCA3_RHRAR 0x14 +#define RTCA3_RHRAR_HR GENMASK(5, 0) +#define RTCA3_RHRAR_PM BIT(6) +#define RTCA3_RWKAR 0x16 +#define RTCA3_RWKAR_DAYW GENMASK(2, 0) +#define RTCA3_RDAYAR 0x18 +#define RTCA3_RDAYAR_DATE GENMASK(5, 0) +#define RTCA3_RMONAR 0x1a +#define RTCA3_RMONAR_MON GENMASK(4, 0) +#define RTCA3_RYRAR 0x1c +#define RTCA3_RYRAR_YR GENMASK(7, 0) +#define RTCA3_RYRAREN 0x1e + +/* Alarm enable bit (for all alarm registers). */ +#define RTCA3_AR_ENB BIT(7) + +/* Control registers. */ +#define RTCA3_RCR1 0x22 +#define RTCA3_RCR1_AIE BIT(0) +#define RTCA3_RCR1_CIE BIT(1) +#define RTCA3_RCR1_PIE BIT(2) +#define RTCA3_RCR1_PES GENMASK(7, 4) +#define RTCA3_RCR1_PES_1_64_SEC 0x8 +#define RTCA3_RCR2 0x24 +#define RTCA3_RCR2_START BIT(0) +#define RTCA3_RCR2_RESET BIT(1) +#define RTCA3_RCR2_AADJE BIT(4) +#define RTCA3_RCR2_ADJP BIT(5) +#define RTCA3_RCR2_HR24 BIT(6) +#define RTCA3_RCR2_CNTMD BIT(7) +#define RTCA3_RSR 0x20 +#define RTCA3_RSR_AF BIT(0) +#define RTCA3_RSR_CF BIT(1) +#define RTCA3_RSR_PF BIT(2) +#define RTCA3_RADJ 0x2e +#define RTCA3_RADJ_ADJ GENMASK(5, 0) +#define RTCA3_RADJ_ADJ_MAX 0x3f +#define RTCA3_RADJ_PMADJ GENMASK(7, 6) +#define RTCA3_RADJ_PMADJ_NONE 0 +#define RTCA3_RADJ_PMADJ_ADD 1 +#define RTCA3_RADJ_PMADJ_SUB 2 + +/* Polling operation timeouts. */ +#define RTCA3_DEFAULT_TIMEOUT_US 150 +#define RTCA3_IRQSET_TIMEOUT_US 5000 +#define RTCA3_START_TIMEOUT_US 150000 +#define RTCA3_RESET_TIMEOUT_US 200000 + +/** + * enum rtca3_alrm_set_step - RTCA3 alarm set steps + * @RTCA3_ALRM_SSTEP_DONE: alarm setup done step + * @RTCA3_ALRM_SSTEP_IRQ: two 1/64 periodic IRQs were generated step + * @RTCA3_ALRM_SSTEP_INIT: alarm setup initialization step + */ +enum rtca3_alrm_set_step { + RTCA3_ALRM_SSTEP_DONE =3D 0, + RTCA3_ALRM_SSTEP_IRQ =3D 1, + RTCA3_ALRM_SSTEP_INIT =3D 3, +}; + +/** + * struct rtca3_ppb_per_cycle - PPB per cycle + * @ten_sec: PPB per cycle in 10 seconds adjutment mode + * @sixty_sec: PPB per cycle in 60 seconds adjustment mode + */ +struct rtca3_ppb_per_cycle { + int ten_sec; + int sixty_sec; +}; + +/** + * struct rtca3_priv - RTCA3 private data structure + * @base: base address + * @clk: RTC clock + * @rtc_dev: RTC device + * @set_alarm_completion: alarm setup completion + * @alrm_sstep: alarm setup step (see enum rtca3_alrm_set_step) + * @lock: device lock + * @ppb: ppb per cycle for each the available adjustment modes + * @wakeup_irq: wakeup IRQ + */ +struct rtca3_priv { + void __iomem *base; + struct clk *clk; + struct rtc_device *rtc_dev; + struct completion set_alarm_completion; + atomic_t alrm_sstep; + spinlock_t lock; + struct rtca3_ppb_per_cycle ppb; + int wakeup_irq; +}; + +static void rtca3_byte_update_bits(struct rtca3_priv *priv, u8 off, u8 mas= k, u8 val) +{ + u8 tmp; + + tmp =3D readb(priv->base + off); + tmp &=3D ~mask; + tmp |=3D (val & mask); + writeb(tmp, priv->base + off); +} + +static u8 rtca3_alarm_handler_helper(struct rtca3_priv *priv) +{ + u8 val, pending; + + val =3D readb(priv->base + RTCA3_RSR); + pending =3D val & RTCA3_RSR_AF; + writeb(val & ~pending, priv->base + RTCA3_RSR); + + if (pending) + rtc_update_irq(priv->rtc_dev, 1, RTC_AF | RTC_IRQF); + + return pending; +} + +static irqreturn_t rtca3_alarm_handler(int irq, void *dev_id) +{ + struct rtca3_priv *priv =3D dev_id; + u8 pending; + + guard(spinlock)(&priv->lock); + + pending =3D rtca3_alarm_handler_helper(priv); + + return IRQ_RETVAL(pending); +} + +static irqreturn_t rtca3_periodic_handler(int irq, void *dev_id) +{ + struct rtca3_priv *priv =3D dev_id; + u8 val, pending; + + guard(spinlock)(&priv->lock); + + val =3D readb(priv->base + RTCA3_RSR); + pending =3D val & RTCA3_RSR_PF; + + if (pending) { + writeb(val & ~pending, priv->base + RTCA3_RSR); + + if (atomic_read(&priv->alrm_sstep) > RTCA3_ALRM_SSTEP_IRQ) { + /* Alarm setup in progress. */ + atomic_dec(&priv->alrm_sstep); + + if (atomic_read(&priv->alrm_sstep) =3D=3D RTCA3_ALRM_SSTEP_IRQ) { + /* + * We got 2 * 1/64 periodic interrupts. Disable + * interrupt and let alarm setup continue. + */ + rtca3_byte_update_bits(priv, RTCA3_RCR1, + RTCA3_RCR1_PIE, 0); + readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, val, + !(val & RTCA3_RCR1_PIE), + 10, RTCA3_DEFAULT_TIMEOUT_US); + complete(&priv->set_alarm_completion); + } + } + } + + return IRQ_RETVAL(pending); +} + +static void rtca3_prepare_cntalrm_regs_for_read(struct rtca3_priv *priv, b= ool cnt) +{ + /* Offset b/w time and alarm registers. */ + u8 offset =3D cnt ? 0 : 0xe; + + /* + * According to HW manual (section 22.6.4. Notes on writing to and + * reading from registers) after writing to count registers, alarm + * registers, year alarm enable register, bits RCR2.AADJE, AADJP, + * and HR24 register, we need to do 3 empty reads before being + * able to fetch the registers content. + */ + for (u8 i =3D 0; i < 3; i++) { + readb(priv->base + RTCA3_RSECCNT + offset); + readb(priv->base + RTCA3_RMINCNT + offset); + readb(priv->base + RTCA3_RHRCNT + offset); + readb(priv->base + RTCA3_RWKCNT + offset); + readb(priv->base + RTCA3_RDAYCNT + offset); + readw(priv->base + RTCA3_RYRCNT + offset); + if (!cnt) + readb(priv->base + RTCA3_RYRAREN); + } +} + +static int rtca3_read_time(struct device *dev, struct rtc_time *tm) +{ + struct rtca3_priv *priv =3D dev_get_drvdata(dev); + u8 sec, min, hour, wday, mday, month, tmp; + u8 trials =3D 0; + u32 year100; + u16 year; + + guard(spinlock_irqsave)(&priv->lock); + + tmp =3D readb(priv->base + RTCA3_RCR2); + if (!(tmp & RTCA3_RCR2_START)) + return -EINVAL; + + do { + /* Clear carry interrupt. */ + rtca3_byte_update_bits(priv, RTCA3_RSR, RTCA3_RSR_CF, 0); + + /* Read counters. */ + sec =3D readb(priv->base + RTCA3_RSECCNT); + min =3D readb(priv->base + RTCA3_RMINCNT); + hour =3D readb(priv->base + RTCA3_RHRCNT); + wday =3D readb(priv->base + RTCA3_RWKCNT); + mday =3D readb(priv->base + RTCA3_RDAYCNT); + month =3D readb(priv->base + RTCA3_RMONCNT); + year =3D readw(priv->base + RTCA3_RYRCNT); + + tmp =3D readb(priv->base + RTCA3_RSR); + + /* + * We cannot generate carries due to reading 64Hz counter as + * the driver doesn't implement carry, thus, carries will be + * generated once per seconds. Add a timeout of 5 trials here + * to avoid infinite loop, if any. + */ + } while ((tmp & RTCA3_RSR_CF) && ++trials < 5); + + if (trials >=3D 5) + return -ETIMEDOUT; + + tm->tm_sec =3D bcd2bin(FIELD_GET(RTCA3_RSECCNT_SEC, sec)); + tm->tm_min =3D bcd2bin(FIELD_GET(RTCA3_RMINCNT_MIN, min)); + tm->tm_hour =3D bcd2bin(FIELD_GET(RTCA3_RHRCNT_HR, hour)); + tm->tm_wday =3D bcd2bin(FIELD_GET(RTCA3_RWKCNT_WK, wday)); + tm->tm_mday =3D bcd2bin(FIELD_GET(RTCA3_RDAYCNT_DAY, mday)); + tm->tm_mon =3D bcd2bin(FIELD_GET(RTCA3_RMONCNT_MONTH, month)) - 1; + year =3D FIELD_GET(RTCA3_RYRCNT_YEAR, year); + year100 =3D bcd2bin((year =3D=3D 0x99) ? 0x19 : 0x20); + tm->tm_year =3D (year100 * 100 + bcd2bin(year)) - 1900; + + return 0; +} + +static int rtca3_set_time(struct device *dev, struct rtc_time *tm) +{ + struct rtca3_priv *priv =3D dev_get_drvdata(dev); + u8 rcr2, tmp; + int ret; + + guard(spinlock_irqsave)(&priv->lock); + + /* Stop the RTC. */ + rcr2 =3D readb(priv->base + RTCA3_RCR2); + writeb(rcr2 & ~RTCA3_RCR2_START, priv->base + RTCA3_RCR2); + ret =3D readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, + !(tmp & RTCA3_RCR2_START), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + /* Update time. */ + writeb(bin2bcd(tm->tm_sec), priv->base + RTCA3_RSECCNT); + writeb(bin2bcd(tm->tm_min), priv->base + RTCA3_RMINCNT); + writeb(bin2bcd(tm->tm_hour), priv->base + RTCA3_RHRCNT); + writeb(bin2bcd(tm->tm_wday), priv->base + RTCA3_RWKCNT); + writeb(bin2bcd(tm->tm_mday), priv->base + RTCA3_RDAYCNT); + writeb(bin2bcd(tm->tm_mon + 1), priv->base + RTCA3_RMONCNT); + writew(bin2bcd(tm->tm_year % 100), priv->base + RTCA3_RYRCNT); + + /* Make sure we can read back the counters. */ + rtca3_prepare_cntalrm_regs_for_read(priv, true); + + /* Start RTC. */ + writeb(rcr2 | RTCA3_RCR2_START, priv->base + RTCA3_RCR2); + return readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, + (tmp & RTCA3_RCR2_START), + 10, RTCA3_DEFAULT_TIMEOUT_US); +} + +static int rtca3_alarm_irq_enable_helper(struct rtca3_priv *priv, + unsigned int enabled) +{ + u8 tmp, mask; + + if (enabled) { + rtca3_byte_update_bits(priv, RTCA3_RSR, RTCA3_RSR_AF, 0); + mask =3D RTCA3_RCR1_AIE; + } else { + mask =3D 0; + } + + rtca3_byte_update_bits(priv, RTCA3_RCR1, RTCA3_RCR1_AIE, mask); + return readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, + ((tmp & RTCA3_RCR1_AIE) =3D=3D mask), + 10, RTCA3_IRQSET_TIMEOUT_US); +} + +static int rtca3_alarm_irq_enable(struct device *dev, unsigned int enabled) +{ + struct rtca3_priv *priv =3D dev_get_drvdata(dev); + + guard(spinlock_irqsave)(&priv->lock); + + return rtca3_alarm_irq_enable_helper(priv, enabled); +} + +static int rtca3_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) +{ + struct rtca3_priv *priv =3D dev_get_drvdata(dev); + u8 sec, min, hour, wday, mday, month; + struct rtc_time *tm =3D &wkalrm->time; + u32 year100; + u16 year; + + guard(spinlock_irqsave)(&priv->lock); + + sec =3D readb(priv->base + RTCA3_RSECAR); + min =3D readb(priv->base + RTCA3_RMINAR); + hour =3D readb(priv->base + RTCA3_RHRAR); + wday =3D readb(priv->base + RTCA3_RWKAR); + mday =3D readb(priv->base + RTCA3_RDAYAR); + month =3D readb(priv->base + RTCA3_RMONAR); + year =3D readw(priv->base + RTCA3_RYRAR); + + tm->tm_sec =3D bcd2bin(FIELD_GET(RTCA3_RSECAR_SEC, sec)); + tm->tm_min =3D bcd2bin(FIELD_GET(RTCA3_RMINAR_MIN, min)); + tm->tm_hour =3D bcd2bin(FIELD_GET(RTCA3_RHRAR_HR, hour)); + tm->tm_wday =3D bcd2bin(FIELD_GET(RTCA3_RWKAR_DAYW, wday)); + tm->tm_mday =3D bcd2bin(FIELD_GET(RTCA3_RDAYAR_DATE, mday)); + tm->tm_mon =3D bcd2bin(FIELD_GET(RTCA3_RMONAR_MON, month)) - 1; + year =3D FIELD_GET(RTCA3_RYRAR_YR, year); + year100 =3D bcd2bin((year =3D=3D 0x99) ? 0x19 : 0x20); + tm->tm_year =3D (year100 * 100 + bcd2bin(year)) - 1900; + + wkalrm->enabled =3D !!(readb(priv->base + RTCA3_RCR1) & RTCA3_RCR1_AIE); + + return 0; +} + +static int rtca3_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) +{ + struct rtca3_priv *priv =3D dev_get_drvdata(dev); + struct rtc_time *tm =3D &wkalrm->time; + u8 rcr1, tmp; + int ret; + + scoped_guard(spinlock_irqsave, &priv->lock) { + tmp =3D readb(priv->base + RTCA3_RCR2); + if (!(tmp & RTCA3_RCR2_START)) + return -EPERM; + + /* Disable AIE to prevent false interrupts. */ + rcr1 =3D readb(priv->base + RTCA3_RCR1); + rcr1 &=3D ~RTCA3_RCR1_AIE; + writeb(rcr1, priv->base + RTCA3_RCR1); + ret =3D readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, + !(tmp & RTCA3_RCR1_AIE), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + /* Set the time and enable the alarm. */ + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_sec), priv->base + RTCA3_RSECAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_min), priv->base + RTCA3_RMINAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_hour), priv->base + RTCA3_RHRAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_wday), priv->base + RTCA3_RWKAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_mday), priv->base + RTCA3_RDAYAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_mon + 1), priv->base + RTCA3_RMONAR= ); + + writew(bin2bcd(tm->tm_year % 100), priv->base + RTCA3_RYRAR); + writeb(RTCA3_AR_ENB, priv->base + RTCA3_RYRAREN); + + /* Make sure we can read back the counters. */ + rtca3_prepare_cntalrm_regs_for_read(priv, false); + + /* Need to wait for 2 * 1/64 periodic interrupts to be generated. */ + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_INIT); + reinit_completion(&priv->set_alarm_completion); + + /* Enable periodic interrupt. */ + rcr1 |=3D RTCA3_RCR1_PIE; + writeb(rcr1, priv->base + RTCA3_RCR1); + ret =3D readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, + (tmp & RTCA3_RCR1_PIE), + 10, RTCA3_IRQSET_TIMEOUT_US); + } + + if (ret) + goto setup_failed; + + /* Wait for the 2 * 1/64 periodic interrupts. */ + ret =3D wait_for_completion_interruptible_timeout(&priv->set_alarm_comple= tion, + msecs_to_jiffies(500)); + if (ret <=3D 0) { + ret =3D -ETIMEDOUT; + goto setup_failed; + } + + guard(spinlock_irqsave)(&priv->lock); + + ret =3D rtca3_alarm_irq_enable_helper(priv, wkalrm->enabled); + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); + + return ret; + +setup_failed: + scoped_guard(spinlock_irqsave, &priv->lock) { + /* + * Disable PIE to avoid interrupt storm in case HW needed more than + * specified timeout for setup. + */ + writeb(rcr1 & ~RTCA3_RCR1_PIE, priv->base + RTCA3_RCR1); + readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, !(tmp & ~RTCA3_R= CR1_PIE), + 10, RTCA3_DEFAULT_TIMEOUT_US); + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); + } + + return ret; +} + +static int rtca3_read_offset(struct device *dev, long *offset) +{ + struct rtca3_priv *priv =3D dev_get_drvdata(dev); + u8 val, radj, cycles; + u32 ppb_per_cycle; + + scoped_guard(spinlock_irqsave, &priv->lock) { + radj =3D readb(priv->base + RTCA3_RADJ); + val =3D readb(priv->base + RTCA3_RCR2); + } + + cycles =3D FIELD_GET(RTCA3_RADJ_ADJ, radj); + + if (!cycles) { + *offset =3D 0; + return 0; + } + + if (val & RTCA3_RCR2_ADJP) + ppb_per_cycle =3D priv->ppb.ten_sec; + else + ppb_per_cycle =3D priv->ppb.sixty_sec; + + *offset =3D cycles * ppb_per_cycle; + val =3D FIELD_GET(RTCA3_RADJ_PMADJ, radj); + if (val =3D=3D RTCA3_RADJ_PMADJ_SUB) + *offset =3D -(*offset); + + return 0; +} + +static int rtca3_set_offset(struct device *dev, long offset) +{ + struct rtca3_priv *priv =3D dev_get_drvdata(dev); + int cycles, cycles10, cycles60; + u8 radj, adjp, tmp; + int ret; + + /* + * Automatic time error adjustment could be set at intervals of 10 + * or 60 seconds. + */ + cycles10 =3D DIV_ROUND_CLOSEST(offset, priv->ppb.ten_sec); + cycles60 =3D DIV_ROUND_CLOSEST(offset, priv->ppb.sixty_sec); + + /* We can set b/w 1 and 63 clock cycles. */ + if (cycles60 >=3D -RTCA3_RADJ_ADJ_MAX && + cycles60 <=3D RTCA3_RADJ_ADJ_MAX) { + cycles =3D cycles60; + adjp =3D 0; + } else if (cycles10 >=3D -RTCA3_RADJ_ADJ_MAX && + cycles10 <=3D RTCA3_RADJ_ADJ_MAX) { + cycles =3D cycles10; + adjp =3D RTCA3_RCR2_ADJP; + } else { + return -ERANGE; + } + + radj =3D FIELD_PREP(RTCA3_RADJ_ADJ, abs(cycles)); + if (!cycles) + radj |=3D FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_NONE); + else if (cycles > 0) + radj |=3D FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_ADD); + else + radj |=3D FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_SUB); + + guard(spinlock_irqsave)(&priv->lock); + + tmp =3D readb(priv->base + RTCA3_RCR2); + + if ((tmp & RTCA3_RCR2_ADJP) !=3D adjp) { + /* RADJ.PMADJ need to be set to zero before setting RCR2.ADJP. */ + writeb(0, priv->base + RTCA3_RADJ); + ret =3D readb_poll_timeout_atomic(priv->base + RTCA3_RADJ, tmp, !tmp, + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + rtca3_byte_update_bits(priv, RTCA3_RCR2, RTCA3_RCR2_ADJP, adjp); + ret =3D readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, + ((tmp & RTCA3_RCR2_ADJP) =3D=3D adjp), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + } + + writeb(radj, priv->base + RTCA3_RADJ); + return readb_poll_timeout_atomic(priv->base + RTCA3_RADJ, tmp, (tmp =3D= =3D radj), + 10, RTCA3_DEFAULT_TIMEOUT_US); +} + +static const struct rtc_class_ops rtca3_ops =3D { + .read_time =3D rtca3_read_time, + .set_time =3D rtca3_set_time, + .read_alarm =3D rtca3_read_alarm, + .set_alarm =3D rtca3_set_alarm, + .alarm_irq_enable =3D rtca3_alarm_irq_enable, + .set_offset =3D rtca3_set_offset, + .read_offset =3D rtca3_read_offset, +}; + +static int rtca3_initial_setup(struct rtca3_priv *priv) +{ + unsigned long osc32k_rate; + u8 val, tmp, mask; + u32 sleep_us; + int ret; + + osc32k_rate =3D clk_get_rate(priv->clk); + if (!osc32k_rate) + return -EINVAL; + + sleep_us =3D DIV_ROUND_UP_ULL(1000000ULL, osc32k_rate) * 6; + + priv->ppb.ten_sec =3D DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate *= 10)); + priv->ppb.sixty_sec =3D DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate= * 60)); + + /* + * According to HW manual (section 22.4.2. Clock and count mode setting p= rocedure) + * we need to wait at least 6 cycles of the 32KHz clock after clock was e= nabled. + */ + usleep_range(sleep_us, sleep_us + 10); + + /* Disable alarm and carry interrupts. */ + mask =3D RTCA3_RCR1_AIE | RTCA3_RCR1_CIE; + rtca3_byte_update_bits(priv, RTCA3_RCR1, mask, 0); + ret =3D readb_poll_timeout(priv->base + RTCA3_RCR1, tmp, !(tmp & mask), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + mask =3D RTCA3_RCR2_START | RTCA3_RCR2_HR24; + val =3D readb(priv->base + RTCA3_RCR2); + /* Nothing to do if already started in 24 hours and calendar count mode. = */ + if ((val & mask) =3D=3D mask) + return 0; + + /* Reconfigure the RTC in 24 hours and calendar count mode. */ + mask =3D RTCA3_RCR2_START | RTCA3_RCR2_CNTMD; + writeb(0, priv->base + RTCA3_RCR2); + ret =3D readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + /* + * Set 24 hours mode. According to HW manual (section 22.3.19. RTC Control + * Register 2) this needs to be done separate from stop operation. + */ + mask =3D RTCA3_RCR2_HR24; + val =3D RTCA3_RCR2_HR24; + writeb(val, priv->base + RTCA3_RCR2); + ret =3D readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, (tmp & mask), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + /* Execute reset. */ + mask =3D RTCA3_RCR2_RESET; + writeb(val | RTCA3_RCR2_RESET, priv->base + RTCA3_RCR2); + ret =3D readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask), + 10, RTCA3_RESET_TIMEOUT_US); + if (ret) + return ret; + + /* + * According to HW manual (section 22.6.3. Notes on writing to and reading + * from registers) after reset we need to wait 6 clock cycles before + * writing to RTC registers. + */ + usleep_range(sleep_us, sleep_us + 10); + + /* Set no adjustment. */ + writeb(0, priv->base + RTCA3_RADJ); + ret =3D readb_poll_timeout(priv->base + RTCA3_RADJ, tmp, !tmp, 10, + RTCA3_DEFAULT_TIMEOUT_US); + + /* Start the RTC and enable automatic time error adjustment. */ + mask =3D RTCA3_RCR2_START | RTCA3_RCR2_AADJE; + val |=3D RTCA3_RCR2_START | RTCA3_RCR2_AADJE; + writeb(val, priv->base + RTCA3_RCR2); + ret =3D readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, ((tmp & mask) = =3D=3D mask), + 10, RTCA3_START_TIMEOUT_US); + if (ret) + return ret; + + /* + * According to HW manual (section 22.6.4. Notes on writing to and reading + * from registers) we need to wait 1/128 seconds while the clock is opera= ting + * (RCR2.START bit =3D 1) to be able to read the counters after a return = from + * reset. + */ + usleep_range(8000, 9000); + + /* Set period interrupt to 1/64 seconds. It is necessary for alarm setup.= */ + val =3D FIELD_PREP(RTCA3_RCR1_PES, RTCA3_RCR1_PES_1_64_SEC); + rtca3_byte_update_bits(priv, RTCA3_RCR1, RTCA3_RCR1_PES, val); + return readb_poll_timeout(priv->base + RTCA3_RCR1, tmp, ((tmp & RTCA3_RCR= 1_PES) =3D=3D val), + 10, RTCA3_DEFAULT_TIMEOUT_US); +} + +static int rtca3_request_irqs(struct platform_device *pdev, struct rtca3_p= riv *priv) +{ + struct device *dev =3D &pdev->dev; + int ret, irq; + + irq =3D platform_get_irq_byname(pdev, "alarm"); + if (irq < 0) + return dev_err_probe(dev, irq, "Failed to get alarm IRQ!\n"); + + ret =3D devm_request_irq(dev, irq, rtca3_alarm_handler, 0, "rtca3-alarm",= priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to request alarm IRQ!\n"); + priv->wakeup_irq =3D irq; + + irq =3D platform_get_irq_byname(pdev, "period"); + if (irq < 0) + return dev_err_probe(dev, irq, "Failed to get period IRQ!\n"); + + ret =3D devm_request_irq(dev, irq, rtca3_periodic_handler, 0, "rtca3-peri= od", priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to request period IRQ!\n"); + + /* + * Driver doesn't implement carry handler. Just get the IRQ here + * for backward compatibility, in case carry support will be added later. + */ + irq =3D platform_get_irq_byname(pdev, "carry"); + if (irq < 0) + return dev_err_probe(dev, irq, "Failed to get carry IRQ!\n"); + + return 0; +} + +static int rtca3_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct rtca3_priv *priv; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->clk =3D devm_clk_get_enabled(dev, "counter"); + if (IS_ERR(priv->clk)) + return PTR_ERR(priv->clk); + + platform_set_drvdata(pdev, priv); + + spin_lock_init(&priv->lock); + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); + init_completion(&priv->set_alarm_completion); + + ret =3D rtca3_initial_setup(priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to setup the RTC!\n"); + + ret =3D rtca3_request_irqs(pdev, priv); + if (ret) + return ret; + + device_init_wakeup(&pdev->dev, 1); + + priv->rtc_dev =3D devm_rtc_allocate_device(&pdev->dev); + if (IS_ERR(priv->rtc_dev)) + return PTR_ERR(priv->rtc_dev); + + priv->rtc_dev->ops =3D &rtca3_ops; + priv->rtc_dev->max_user_freq =3D 256; + priv->rtc_dev->range_min =3D mktime64(2000, 1, 1, 0, 0, 0); + priv->rtc_dev->range_max =3D mktime64(2099, 12, 31, 23, 59, 59); + + return devm_rtc_register_device(priv->rtc_dev); +} + +static void rtca3_remove(struct platform_device *pdev) +{ + struct rtca3_priv *priv =3D platform_get_drvdata(pdev); + u8 tmp, mask =3D RTCA3_RCR1_AIE | RTCA3_RCR1_PIE; + + guard(spinlock_irqsave)(&priv->lock); + + /* Disable alarm, periodic interrupt. */ + rtca3_byte_update_bits(priv, RTCA3_RCR1, mask, 0); + readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, !(tmp & mask), + 10, RTCA3_IRQSET_TIMEOUT_US); +} + +static int __maybe_unused rtca3_suspend(struct device *dev) +{ + struct rtca3_priv *priv =3D dev_get_drvdata(dev); + + if (!device_may_wakeup(dev)) + return 0; + + /* Alarm setup in progress. */ + if (atomic_read(&priv->alrm_sstep) !=3D RTCA3_ALRM_SSTEP_DONE) + return -EBUSY; + + enable_irq_wake(priv->wakeup_irq); + + return 0; +} + +static int rtca3_clean_alarm(struct rtca3_priv *priv) +{ + struct rtc_device *rtc_dev =3D priv->rtc_dev; + time64_t alarm_time, now; + struct rtc_wkalrm alarm; + struct rtc_time tm; + u8 pending; + int ret; + + ret =3D rtc_read_alarm(rtc_dev, &alarm); + if (ret) + return ret; + + if (!alarm.enabled) + return 0; + + ret =3D rtc_read_time(rtc_dev, &tm); + if (ret) + return ret; + + alarm_time =3D rtc_tm_to_time64(&alarm.time); + now =3D rtc_tm_to_time64(&tm); + if (alarm_time >=3D now) + return 0; + + /* + * Heuristically, it has been determined that when returning from deep + * sleep state the RTCA3_RSR.AF is zero even though the alarm expired. + * Call again the rtc_update_irq() if alarm helper detects this. + */ + + guard(spinlock_irqsave)(&priv->lock); + + pending =3D rtca3_alarm_handler_helper(priv); + if (!pending) + rtc_update_irq(priv->rtc_dev, 1, RTC_AF | RTC_IRQF); + + return 0; +} + +static int __maybe_unused rtca3_resume(struct device *dev) +{ + struct rtca3_priv *priv =3D dev_get_drvdata(dev); + + if (!device_may_wakeup(dev)) + return 0; + + disable_irq_wake(priv->wakeup_irq); + + /* + * According to the HW manual (section 22.6.4 Notes on writing to + * and reading from registers) we need to wait 1/128 seconds while + * RCR2.START =3D 1 to be able to read the counters after a return from l= ow + * power consumption state. + */ + mdelay(8); + + /* + * The alarm cannot wake the system from deep sleep states. In case + * we return from deep sleep states and the alarm expired we need + * to disable it to avoid failures when setting another alarm. + */ + return rtca3_clean_alarm(priv); +} + +static SIMPLE_DEV_PM_OPS(rtca3_pm_ops, rtca3_suspend, rtca3_resume); + +static const struct of_device_id rtca3_of_match[] =3D { + { .compatible =3D "renesas,rz-rtca3", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rtca3_of_match); + +static struct platform_driver rtca3_platform_driver =3D { + .driver =3D { + .name =3D "rtc-rtca3", + .pm =3D &rtca3_pm_ops, + .of_match_table =3D rtca3_of_match, + }, + .probe =3D rtca3_probe, + .remove_new =3D rtca3_remove, +}; +module_platform_driver(rtca3_platform_driver); + +MODULE_DESCRIPTION("Renesas RTCA-3 RTC driver"); +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_LICENSE("GPL"); --=20 2.39.2 From nobody Wed Dec 17 15:39:51 2025 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55239199384 for ; Tue, 16 Jul 2024 10:30:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721125850; cv=none; b=E06Y18kseSaAy4kp+7kvFRNf2ozTrEGzN+SlzFvvftcNLoG65BLc050u7B+tirDfmXzasNnzHchsuEE59At8LCZ7Uv8UOnuFbR8mq+NDnI0vdnwDuUOoDQOM31/chTTzDuk1VnapYwM1TZgoWJRLIDSIBDXCIUP+8W3r0ie4zpY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721125850; c=relaxed/simple; bh=EvwJ3uqjttJf5sOa7ZDrU8PDHXXQFC6izxqgjR1m4ec=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=q+EL2yaIoDUOAY6SeItVxINGqfXLRYqyBiFx7Jd9ycCtSaEQallQn0lTLeC/oVMQDQsO11RmX+9Bzy7+My1af3TTYWWd6OSOwKHiTty2XapQ42lqJEi/1IasUgm/9HeeAxejzrzA2G9cJ+OTv1nv3+/3NNcakuLW2n5ZQNhCqNg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=Ml3wGY/9; arc=none smtp.client-ip=209.85.128.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="Ml3wGY/9" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-427b9dcbb09so4800235e9.3 for ; Tue, 16 Jul 2024 03:30:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1721125846; x=1721730646; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Lfsm6nSG5J99n7fBjSEyZBKTrg1AsoRf03PyuQSS78k=; b=Ml3wGY/9+hx7Ksjye8B/vMKuZLzccSmMQGSFh3LtHVNiaHLvgwgal32tv8WkIFANqD JW7GQ0cE0oHMU/bc8ZeopQxGzyx0O7Lmx5AGNHJwuuRxl4J5RECPikMenJ6npZptPioY Ie0Qw3aEj/Yk0ZWeOvNpb1koI7OSg2Ko4j870QC71OBgDQzeFAX7j+/WTTwqeVaQy+JV LfHjTzs0PrDO0SYxRfYt9YsqxpPBBYf8gwVrjwXlyDPSQ9iyPGDZ5nlOehVkwGfSEAvB L5bzDNkf6mlOA7WasHIWFceXFN/ruvP4PI5HYGaTBPX5ij63YBBROX1LTtbzmyrVDVQF IDDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721125846; x=1721730646; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Lfsm6nSG5J99n7fBjSEyZBKTrg1AsoRf03PyuQSS78k=; b=FVzydGy20WdGCviubdBjK/XoP56TnyM+bvY9yW+kZmsgs893mvNIA3qEQzMSnNgNzT AejkIncv9BzZ4IUHKcqRLWJatZou8RM/rFKN7dSEppT7TrV2JMligJuaJ0XTNqCHBtcd CZDmWV6PRjNSyZXSGpufwrZ/VZL3+WRvEufVsE0irV4tsjHu+CbrWE3NDigNyOi5eUzg wCVwe6lBjb6xqnm17oidY2+Eggjc87WV7oZtqCGjEu+ZIXq+CxJr4dosMn+NG+gkS6oM 4D/kTkoDe4QG8uJ+u1kEhCKwPZMhY3wqD7AecBK0ZARvZh/1lPj1uR3I+o/WKzTjHTat YYxA== X-Forwarded-Encrypted: i=1; AJvYcCWHiPSzcruZioJxAhL/3Osjbx9UQoOPGfD/dp5LBiT8UKhdU8fS/F4pTH4cmz6zeeQJlU/oufavpzLeWutkl3qzGhwrbAHa40q96IDy X-Gm-Message-State: AOJu0Yxmcgj2G8B85BvA5gMFxME++XE3fLICs56omHuYKzzDyZ4FF4Im 2hVNi5OnmkzP4TE3Y1pL12GDK1zBO0O1tibQ/DJcPPmqyoDO6S7Cat+LLLEHuSs= X-Google-Smtp-Source: AGHT+IGdDT8jIaqfwHSd4jCsuylmV/YWlg71WG2lfw6K9e3FV4X+drTEDU0GFqSOCs5IcXpk4rI+eQ== X-Received: by 2002:a05:600c:35c5:b0:426:61af:e1d6 with SMTP id 5b1f17b1804b1-427ba6fa0d1mr12677545e9.29.1721125845829; Tue, 16 Jul 2024 03:30:45 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427a5e77488sm121546145e9.9.2024.07.16.03.30.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 03:30:45 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 06/11] arm64: dts: renesas: r9a08g045: Add VBATTB node Date: Tue, 16 Jul 2024 13:30:20 +0300 Message-Id: <20240716103025.1198495-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> References: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add the DT node for the VBATTB IP along with DT bindings for the clock it provides. Signed-off-by: Claudiu Beznea --- Changes in v2: - update compatibles - updated clocks and clock-names for clock-controller node - removed the power domain from the clock-controller as this is controlled by parent node in v2 arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g045.dtsi index 0d5c47a65e46..78b4e088a3a5 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -72,6 +72,30 @@ scif0: serial@1004b800 { status =3D "disabled"; }; =20 + vbattb: vbattb@1005c000 { + compatible =3D "renesas,r9a08g045-vbattb"; + reg =3D <0 0x1005c000 0 0x1000>; + ranges =3D <0 0 0 0x1005c000 0 0x1000>; + interrupts =3D ; + interrupt-names =3D "tampdi"; + clocks =3D <&cpg CPG_MOD R9A08G045_VBAT_BCLK>; + clock-names =3D "bclk"; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A08G045_VBAT_BRESETN>; + #address-cells =3D <2>; + #size-cells =3D <2>; + status =3D "disabled"; + + vbattclk: clock-controller@1c { + compatible =3D "renesas,r9a08g045-vbattb-clk"; + reg =3D <0 0x1c 0 0x10>; + clocks =3D <&vbattb_xtal>; + clock-names =3D "xin"; + #clock-cells =3D <0>; + status =3D "disabled"; + }; + }; + cpg: clock-controller@11010000 { compatible =3D "renesas,r9a08g045-cpg"; reg =3D <0 0x11010000 0 0x10000>; @@ -299,4 +323,11 @@ timer { interrupt-names =3D "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; }; + + vbattb_xtal: vbattb-xtal { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board. */ + clock-frequency =3D <0>; + }; }; --=20 2.39.2 From nobody Wed Dec 17 15:39:51 2025 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC6A71993A7 for ; Tue, 16 Jul 2024 10:30:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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([82.78.167.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427a5e77488sm121546145e9.9.2024.07.16.03.30.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 03:30:47 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 07/11] arm64: dts: renesas: r9a08g045: Add RTC node Date: Tue, 16 Jul 2024 13:30:21 +0300 Message-Id: <20240716103025.1198495-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> References: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add the DT node for the RTC IP available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea --- Changes in v2: - updated compatibles arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g045.dtsi index 78b4e088a3a5..22008407848c 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -72,6 +72,18 @@ scif0: serial@1004b800 { status =3D "disabled"; }; =20 + rtc: rtc@1004ec00 { + compatible =3D "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; + reg =3D <0 0x1004ec00 0 0x400>; + interrupts =3D , + , + ; + interrupt-names =3D "alarm", "period", "carry"; + clocks =3D <&vbattclk>; + clock-names =3D "counter"; + status =3D "disabled"; + }; + vbattb: vbattb@1005c000 { compatible =3D "renesas,r9a08g045-vbattb"; reg =3D <0 0x1005c000 0 0x1000>; --=20 2.39.2 From nobody Wed Dec 17 15:39:51 2025 Received: from mail-lj1-f180.google.com (mail-lj1-f180.google.com [209.85.208.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4D4E199E90 for ; Tue, 16 Jul 2024 10:30:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721125852; cv=none; b=fe9xJM5I8mDWId8ixrEp/iL+If2AvJLrMMUxxOSj58IKmifDgLh33S2GEtaJ7KFMiFYp2qb9La0NkWakiBnEhHBVW8J+f4hnzF8IchsMyoJB+W0F2mE0XvSlzbaQPokr78VPHKQjnBIkL4P6occaMGKBAz4hpr2tx4nYRykcuVA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721125852; c=relaxed/simple; bh=kHYvG6Jmfou0a/3H3JPJCy+a3te9zYGMB7WNF7i3CEI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FsmdaG8orKgPKWn4HKY9XZx2eG2IsA6LjNrq+YS14SVLtid9gA05uRCPCzI7CfFPpYfOXtq2rp9Wj6Yb5k6uYYZk1BHa2l9qmm89i3iIoHHt+AmmPu7nzhylU7/vHSU7jTexYnRS26g2cdNLlkp/4D77homMqgZHwATH7Rcc21s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=oOdrnT2j; arc=none smtp.client-ip=209.85.208.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="oOdrnT2j" Received: by mail-lj1-f180.google.com with SMTP id 38308e7fff4ca-2eebc76119aso60036531fa.2 for ; Tue, 16 Jul 2024 03:30:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1721125849; x=1721730649; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SgEFJU9TqEeEi7v4UfFzMf6SUYm8BDlnIzCjSGdepnE=; b=oOdrnT2jlbBMpxuKx3C0WXIRN4heqySo5g9u45cJHalGbz/kK0wpmpgg4xzpStvp2n omNnvyDO2vgDq5lY1yniqfUOiAd784/GJIc00gk/zaxDmAEVIrIWW0tG5dC7R98Ui45p FFy2zXBlWdGKcoZWotI39hVEy3FUwQ4HorhV3tVhvwDqE5ENL6PF3lO/6MNf/Tcif4y0 Uhz0iBxTnQpThrHwIzwSmdYhMy/DK8EZSSdB1whVlpYutT/pq7OUPBMVIXzjli0eGcef zHdHqzvlJC1K5wBu562357GNLliijHt2ikXQ8omDzAY37zdSlFu5U7C/vpN29zZsykXk vmxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721125849; x=1721730649; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SgEFJU9TqEeEi7v4UfFzMf6SUYm8BDlnIzCjSGdepnE=; b=A+LOxkismJAV8+ByES1Nkx81YOPqCJ8mm7oLvN+/VketHIF2rFj7n8fnSdTvD+f6eg AGkwbyWEdyqeYelGF3WCP/VX6Gel6o91KnxkzCxI7D5wdFF376inlSxv+C6GxtTZZ3wj VkkoviV4y8ir953MeLWyI0ddlmcKfQuUwwAGH1LsCQnUxzxg4s9N+qS6CXuN/49qEnOX 6Z2YCzzQ9RDvScJf863DlbgFd1Jd1TqPLR2odEmslobt58ufx76j73RUJ1i5iaNxLuTH E83+VmCnaoVI1dF93aNvVMQy1uAc3IRCdqG6a0TfxG0eqzYQDARJfttPPTdaHPeYJLYj tGXQ== X-Forwarded-Encrypted: i=1; AJvYcCXnxKDePcYHzrXbxElhpnmRAULhtI5ofntETPj1xAmol2EiBBBA3DDUJLbJvlPr1N9KSSoJCjnDeZR1i69i/iWXBssEW6Qv307DNS31 X-Gm-Message-State: AOJu0YzlHTRg10wsaF2JkJQ1tjV0QQr3+f9eBhWvgRfLAkibq943jXFR 4dOk3Cg4UOykV4zDNgaQ4BgtT7HO79HwPU+/iP3SUBWmlt091lH314WSpVXkWb4= X-Google-Smtp-Source: AGHT+IE4UrP8ocZy8DYCRi6ljSVc7gUaTDEwV0MlfP0Wt1LcKXTzKRIXgiUNL8wbFViSdsnBD2NBxA== X-Received: by 2002:a2e:9ed9:0:b0:2ec:5699:5e6 with SMTP id 38308e7fff4ca-2eef4190aedmr11234431fa.26.1721125848934; Tue, 16 Jul 2024 03:30:48 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427a5e77488sm121546145e9.9.2024.07.16.03.30.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 03:30:48 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 08/11] arm64: dts: renesas: rzg3s-smarc-som: Enable VBATTB clock Date: Tue, 16 Jul 2024 13:30:22 +0300 Message-Id: <20240716103025.1198495-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> References: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Enable the VBATTB clock controller. Signed-off-by: Claudiu Beznea --- Changes in v2: - none arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3s-smarc-som.dtsi index 8a3d302f1535..517ce275916a 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -341,6 +341,19 @@ mux { }; }; =20 +&vbattb_xtal { + clock-frequency =3D <32768>; +}; + +&vbattb { + status =3D "okay"; +}; + +&vbattclk { + renesas,vbattb-load-nanofarads =3D <12500>; + status =3D "okay"; +}; + &wdt0 { timeout-sec =3D <60>; status =3D "okay"; --=20 2.39.2 From nobody Wed Dec 17 15:39:51 2025 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20255199EA9 for ; Tue, 16 Jul 2024 10:30:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721125853; cv=none; b=fr9SkvrvuWNyW1qetuiZHnwt+9Gl4YhClsk0cES82vmRNXlvGSrvS6cn2DOdcfiOEai2keDr31hKy2fXZ+qXKMM2qXCGQHac14GXyIWJ+0ucA59ywmm3EX1LN3fXGfJK1BAgqLxKAti+tq8/AZAgmUVOB2tk2C9kLeHjFQ+mRX4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721125853; c=relaxed/simple; bh=Yma0qTMMXu0a2MbLRmuXJu/JnB7PKFVYrRohVbWmkNg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=TxnX7LOnUsPIAR7R+NT+nqwikFQZMtVNfxTw/SnoL9+H1lvB8x5ZSqE/u4EJcnjH0aM8UpfOrFU8cTVeuE6pul4hm58bDm6DKIJJZ3bq2VJgS6eGJAc1KlsZon7I/3v0woz2q83eBasnqSbA7bgTQLuZ/RvVR2G2L+UseuIBh3k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=KCU0FCGG; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="KCU0FCGG" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-42793fc0a6dso35911555e9.0 for ; Tue, 16 Jul 2024 03:30:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1721125850; x=1721730650; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/G5+44h167VOsiaOPrdd9U616TrltprIHsWsocA1F5A=; b=KCU0FCGGhREK7zVJjftkrnJWEpFCeocN6hdC1uV1OQd5HXNtrKkfvSl4dBD3Gs4OF3 o0Kx3sk/hxVFIPL9Tb9vviDxLMCig8wB9yx/7CtTMYDvJnrg2MZeP0K3pCHaJbL17Fig DINjVdIkZ3BFv+OfsUywi0Q4DP97bZyzk/F1Ke/hTTygyDP3KhGkfpiU6mIZz0qOTrvR Kv1m67I9zVotqgLPfRG/TzJqdVKCwrn7enQxUNCnRClnp+rVosJPcn65tsXkfM/yLdiZ ZVtWUBjUJ+819+hLDPCvjJWpHXnxPh/+bqM0727M66tdlSDCNtRRUJSB0G4YG8NScB0U ugSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721125850; x=1721730650; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/G5+44h167VOsiaOPrdd9U616TrltprIHsWsocA1F5A=; b=hBdWUxTh+PYwxzqCeya6nObnJUAhyD47UzR+2pPp3rHwP2wRpdyTfrCKkk6rycOqfB OekiqrOZYeeRnZbd0uVBjfEYoJz0yS98V4ByjtfwrBuRcqgbnNBJqDSGdkInRwfM2c2E MTmBnUMgl0GO4KIRj3BzgB14Q9qnOYEORvkJpAK9vGLJNrSIsoTKhJfWMOmhMa1+fhXi 9/tCiWQLv2hl/ejyQz3RHHEPREYhiXf29WorLgcvSc6ewukVKamS8o3tyhaW582Su8Mb FDfGpsRpWiLGGXKmSG4AJoRnrNfvI8UWdhDClsWFg5mTW+7Mq7qw6+6b6q1S4lmQBX9v ycZg== X-Forwarded-Encrypted: i=1; AJvYcCUoEBm9+f4Q1PwgqCOF76NOJ74j41oUjBN56+UhYrRKykDemZ1uaXfGTD5IF0pP5i8suiYbvPaXYW7TyMYH14TAHQ7Nd4Q0Igtqnyh7 X-Gm-Message-State: AOJu0Yz1FB2R6aEpgatHISOV599Z8mXnVVuVNn3k369uY5BjF6Ql86Ri Hn31Qz6B8MamSgA4I4jJoWv0uhbqr11lWK5Cquu+idxzpYILpLaX3O716tB5TbA= X-Google-Smtp-Source: AGHT+IF+j4vpd59rXfwJJpale0+2M2xjNcq85fj7Hc313ckK0UPmDoi685v/0yv7e97UdhOY9yZPEA== X-Received: by 2002:a05:600c:1547:b0:426:6f5f:9da6 with SMTP id 5b1f17b1804b1-427ba697bd1mr9207585e9.27.1721125850521; Tue, 16 Jul 2024 03:30:50 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427a5e77488sm121546145e9.9.2024.07.16.03.30.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 03:30:50 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 09/11] arm64: dts: renesas: rzg3s-smarc-som: Enable RTC Date: Tue, 16 Jul 2024 13:30:23 +0300 Message-Id: <20240716103025.1198495-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> References: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Enable RTC. Signed-off-by: Claudiu Beznea --- Changes in v2: - none arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3s-smarc-som.dtsi index 517ce275916a..82a80fd8e7ec 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -341,6 +341,10 @@ mux { }; }; =20 +&rtc { + status =3D "okay"; +}; + &vbattb_xtal { clock-frequency =3D <32768>; }; --=20 2.39.2 From nobody Wed Dec 17 15:39:51 2025 Received: from mail-lj1-f176.google.com (mail-lj1-f176.google.com [209.85.208.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CAEA19A841 for ; Tue, 16 Jul 2024 10:30:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721125856; cv=none; b=r+aLIqxA5yW0NkR6IhYxmgvwupL9F/8ctINbUQIjr5cJuhFQDOUfO79mlDk9B62FKLcbZFU9LhHIh9UchW0cCSqv3L89pEZ4CIjkog3bbRY6nIEfvy5QghVjLFgzckqI8iKI8kd9xS9vdFMn24NBnmPRP5BGU66roniF6NN17xk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721125856; c=relaxed/simple; bh=3FnnVqryGA1+fyj62llLLDqTN7Yctxhd6gzpR4TrpXA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=S3q3hnAEMjrDAKdk5m3pfqYTUytkNA1cdViwOsxRc/PjJ9dPUIyc049+3qZgnezfa9ozycbRgqFTjTb4VX3xH3Escprgyb+oXDKL9zg+xog7fWmhH0CjVv1vmiKZU0Y+/r4jth3M8nb3jHECIWF1MIrHJGx7CO4PARc+5MR8N84= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=MnqJtLqO; arc=none smtp.client-ip=209.85.208.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="MnqJtLqO" Received: by mail-lj1-f176.google.com with SMTP id 38308e7fff4ca-2eee083c044so33065631fa.3 for ; Tue, 16 Jul 2024 03:30:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1721125852; x=1721730652; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1Lc/uNU85i9gb0+79NrAcdA+6hL4Qt2Dc7/pD8w1sdo=; b=MnqJtLqOH1xetf+sej3CzzDckDmuqP8XGjAGqE5sikHYdKqGzb2HsUm89LJZZ+wPOl 9WPBtgKXIGtG3NHpglNcxuimRYRe+KvAF3bwzU03KuYzWPbN7VgW6BQxxwYQVleEkjgN 8u3dzB+ZW7wi6ILhJFS+Zl6ueCitHyszi9OUlTNLcH95rjaFq3sTS+iLcBJRK/wpYvPg 8OH4Sr/3Ic8JwR1upvbppFu7qmFqFxnzlK+maQEEtTMPvbpVZIDRUPlAjXgAn2eximfx MOY0ZinQtOQrs3g/Q0yjtR9bnhaXJnq01nET9VzvWwQXKocHJSLjAFx0X2qA/PSOsatL KmAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721125852; x=1721730652; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1Lc/uNU85i9gb0+79NrAcdA+6hL4Qt2Dc7/pD8w1sdo=; b=XWiEHS2rKvSOkqIs3GKLVp2MwUBnjq0LPkM1gnzQacUwnH+4+wEjQJRKsuK7Ab5Gf9 4ldmnLWBRyvCElzQD9pSnUv9nixZZKFu3E1Ap8YF0N4d9x6IMfOmFQu6MjxXoNSAb0yK ajROycm3VZRcTQ+P5/KGPpW59yNI3Kul9hr/0t+aRsdEBVvEWeywv0ElEMCpCFE1SH0s 1+oZI8qqOadvomkO2rVzkrJ/VCa6L3glNhhEsCvlSdjsIkwXL9aaJggH6MkoSnLF4zTd TegwRUIS9MxkLGDwjoffi9Dfv9JD4MEVwNKTjGbsEWfNqRpPspty0WpeuNYZeC9ocb/4 BgLw== X-Forwarded-Encrypted: i=1; AJvYcCW5Js2JqiWVYcIg6hI5ag3kYzJSXlabi9TtYNArgtDXeFGrYVxfJxzyjLUp1picQGHMf9XWcgVhdhdqPpDEBPmmjPa1q9WXF0ZgzWqj X-Gm-Message-State: AOJu0YxSEwKKpD7x7Fk8Df6R0VtlZ2mufnls3B3hCNrPQ4qQ048zTO19 heLItP0r9mYxFZZzhh1rDgRg2WFQY5YeB6l/GYkAuVxyOyA/6cG0G/4E1TwDHIU= X-Google-Smtp-Source: AGHT+IF1Lb+nVjAsf8fHP0AS1wIPQKQn9s1ZCjD3vT5CusZmhAU+Uik6JLX9tgQRYjTy6nqzNxi6bQ== X-Received: by 2002:a2e:9981:0:b0:2ec:f68:51de with SMTP id 38308e7fff4ca-2eef41e29femr10746011fa.47.1721125852148; Tue, 16 Jul 2024 03:30:52 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427a5e77488sm121546145e9.9.2024.07.16.03.30.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 03:30:51 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 10/11] arm64: defconfig: Enable VBATTB Date: Tue, 16 Jul 2024 13:30:24 +0300 Message-Id: <20240716103025.1198495-11-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> References: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Enable VBATTB MFD and clock driver flags. Signed-off-by: Claudiu Beznea --- Changes in v2: - added CONFIG_MFD_RENESAS_VBATTB - added vendor name in the VBATTB clock flag arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 5c9fcf9ad395..f35fd006bbbc 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -750,6 +750,7 @@ CONFIG_MFD_MAX77620=3Dy CONFIG_MFD_MT6360=3Dy CONFIG_MFD_MT6397=3Dy CONFIG_MFD_SPMI_PMIC=3Dy +CONFIG_MFD_RENESAS_VBATTB=3Dy CONFIG_MFD_RK8XX_I2C=3Dy CONFIG_MFD_RK8XX_SPI=3Dy CONFIG_MFD_SEC_CORE=3Dy @@ -1358,6 +1359,7 @@ CONFIG_SM_VIDEOCC_8250=3Dy CONFIG_QCOM_HFPLL=3Dy CONFIG_CLK_GFM_LPASS_SM8250=3Dm CONFIG_CLK_RCAR_USB2_CLOCK_SEL=3Dy +CONFIG_CLK_RENESAS_VBATTB=3Dy CONFIG_HWSPINLOCK=3Dy CONFIG_HWSPINLOCK_QCOM=3Dy CONFIG_TEGRA186_TIMER=3Dy --=20 2.39.2 From nobody Wed Dec 17 15:39:51 2025 Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91FEB19A867 for ; Tue, 16 Jul 2024 10:30:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721125858; cv=none; b=h+d0ntEGIiQuN0pwpJzECCA/4ZdaUwH3FkYO62zdwCtJtUean+HL89X+7fLqxod+z5FKjtJmBwNaV6iGPdmdAPkJzrs7Rx1GNIjk0B7IeZaguYtnF4GyfKQSBxCiMVKQs5JJsNN4YpJSGDRxZYbBfwpGv5TBq3O0e1nNoNMdOe0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721125858; c=relaxed/simple; bh=JipNE+kqEQPBn7Jx4UqjRRUM4WXbboTrnyw0mDx93KA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=WYtTceoiyIvwrYU+Tvh5mcz76FeAQPZSUmrmjCQvrHjUaAZ71DZBpQuHpWquhhaX3hkt6BDiMSmx4DEWc+CnMz0JJSsfOJkT2ZG12uNXz6HYRdQI9hhkgIwzE4ibHF+6fQ0Xzh961f/lhzqT4P24tjB8xCINEI39egBrpYxBZJ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=BlLLwGcN; arc=none smtp.client-ip=209.85.167.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="BlLLwGcN" Received: by mail-lf1-f47.google.com with SMTP id 2adb3069b0e04-52e9f863c46so5824506e87.1 for ; Tue, 16 Jul 2024 03:30:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1721125854; x=1721730654; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DAXdKc5Z+02xSdGxMpcMXF7UJmX+WtkbTbyJ/hK50W0=; b=BlLLwGcN5mUmW7Fw/0UW6QIyETSGj7d8hXPmhMifppK3O4TM/M+3EpH4Y77Z91LIdG +QKUxlUrAU1YA41ly59IxsHMDk7eP90M+7f69/ecHBwsB6Aqz0N9jeGCcx139e7BY+vK CFV6zL3sUklGCCH2yqsmLI03eMQnthm68cm0vKDc8n5/X8yiQ017VilaZ84Ahuh/whCk lmuaCVmj3xW2dxeEBe4DZ1609eaQij4OkDnbuXC03PqtIfFpZunUDlG3AQaScWe0kAJp 8XRUxU5xSZMA9SLEfRnf2g6fhQ/SDo3En9Vsftai6OcnphvLeGwg9TmRF77lQIiCphEY TtJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721125854; x=1721730654; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DAXdKc5Z+02xSdGxMpcMXF7UJmX+WtkbTbyJ/hK50W0=; b=O6vp/JbVnRS3TI2JmQXpffd/B256+4WEULMl333yRSwcGIbx9mTXWewFe9zLULCuQs LE/UbknyfyR5gHOhyPGRFyRS9Sm2D3wC0zQc5Jn2axL0W8XBMh2tLs1tUM0ZJ9mY3VrB EDuTgWVzVMY+kIlJr0p5QuAJ0XEFyswhYtoG2O1ubGcbzc+yryBo7YV4VSvOTvDZ0P6X Q/s3BzmJwhVE80ZSRzKNo0NGUaW7cupXlCo5tiiFT5fOolzDO2z9kzLrJ38its0pIg12 6i5X9uoMrc4XLX5dlAVurjvKr0KnWhEvwWKiIqxYrtgp1wSRgcFsAoWmkmkR7hyF20h4 WxfQ== X-Forwarded-Encrypted: i=1; AJvYcCX0zZe8Th+0CHjpGpQswrg0AvzkM30hI8M7AWaZ/iCntytLIZIAuQmJKxJjvST5129l+5huw6eY8p6iE3vTcJSvaE6/zLYrfbB2LqKa X-Gm-Message-State: AOJu0YzRZEDjkdJ9Wh3e/HReikODiIlUjUneks0Pn/3wb5Bi4qT4MZy2 R1+Iq0zP7aNu2uyLoxdiabvg7xGdGGgcMT87G8RAVDYn/uItNtyicWy6RH5V3Tg= X-Google-Smtp-Source: AGHT+IFbkiHtNVlSjCVJf3cVxZfgoUXWPkU+uRJ0BzsW0f977HEVh4lCus0KUh+9d9jKXgqmMYtbgA== X-Received: by 2002:a05:6512:3c8c:b0:52b:c025:859a with SMTP id 2adb3069b0e04-52edef1cc52mr1084908e87.2.1721125853907; Tue, 16 Jul 2024 03:30:53 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427a5e77488sm121546145e9.9.2024.07.16.03.30.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 03:30:53 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 11/11] arm64: defconfig: Enable Renesas RTCA-3 flag Date: Tue, 16 Jul 2024 13:30:25 +0300 Message-Id: <20240716103025.1198495-12-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> References: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Enable Renesas RTCA-3 flag for the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea --- Changes in v2: - none arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index f35fd006bbbc..e90578659447 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1213,6 +1213,7 @@ CONFIG_RTC_DRV_IMX_SC=3Dm CONFIG_RTC_DRV_MT6397=3Dm CONFIG_RTC_DRV_XGENE=3Dy CONFIG_RTC_DRV_TI_K3=3Dm +CONFIG_RTC_DRV_RENESAS_RTCA3=3Dy CONFIG_DMADEVICES=3Dy CONFIG_DMA_BCM2835=3Dy CONFIG_DMA_SUN6I=3Dm --=20 2.39.2