From nobody Wed Dec 17 15:38:20 2025 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7ADD27733; Tue, 16 Jul 2024 15:51:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721145069; cv=none; b=ppabfemFa+iyBsZSbrkBpCIhD6FgNG2IrUnHOXl9vCcVv9jjM2EdlLUaZbJdCvzp7sP5D0Jod/EMDYP3E6++UoQkWj95ZIr88iVgM3OmZRBWbg60CLh475lwfiXjJJH5ENqNQSqXjGSX3wWZiQe4HjC70clWrlQbM0HizKU7Dzs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721145069; c=relaxed/simple; bh=Q2Mlft8Y56s8Vjeg4O3l1zZuQNCYpMaZI5odbUhc1lE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GjnbYQbcXB0u7rFfM+fYqNyfEhPVrE1yildcbEuFDSxGT2X5EGJVffK/G5DdnzXHJHRwpd2e/aAreKkYbN1MfIQ5xCZdtHeFUV2teOTN3XmXsbvWHSdTBTUzyEbcUFIAlomTVzkBpn97YpONdukMgCefgmS1HSYSqAwPM7LKVSI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=0e4kOoNv; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="0e4kOoNv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1721145066; bh=Q2Mlft8Y56s8Vjeg4O3l1zZuQNCYpMaZI5odbUhc1lE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=0e4kOoNvRAg+zhLmyQowbrH3Entrkmhzhl4RK3TjIzQHF4On8mAgD2YaYtTMLJ82r ZsEvOu/6pKTE4eyAhtSjD+RjbfQ/doIW7M0IWyFB5wDzfiYy2QUV+46J3PU4tzi2OK TdXmY0lr2WLVtbcgJZCYdFyPy8CRZkrS7GRO79ZaKnXHqnhghU3NiyRUruFHjB/VYw 8F7RsB6PD1iNVtVp6UI9YVFC6sKoTAiWhk/DNGd0CYB2oeZM4pSMpW0SUwHzzhMdtz nDF3Xdoil3aSQEJZSgJMtiFcz3jAv8FU/JEK1hSp1UIMpSTCmWTgni+4Ha0H/aZNxk FN/Vn5MYzL6yw== Received: from [127.0.1.1] (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: obbardc) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 990B637821CE; Tue, 16 Jul 2024 15:51:05 +0000 (UTC) From: Christopher Obbard Date: Tue, 16 Jul 2024 16:51:04 +0100 Subject: [PATCH 1/2] dt-bindings: arm: rockchip: add Firefly CORE PX30 JD4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240716-rockchip-px30-firefly-v1-1-60cdad3023a3@collabora.com> References: <20240716-rockchip-px30-firefly-v1-0-60cdad3023a3@collabora.com> In-Reply-To: <20240716-rockchip-px30-firefly-v1-0-60cdad3023a3@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Kever Yang , Christopher Obbard X-Mailer: b4 0.13.0 The Firefly CORE PX30 JD4 board is a SOM and motherboard bundle from Firefly. Add devicetree binding documentation for it. Signed-off-by: Christopher Obbard --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index e04c213a0dee4..19e06e1253e15 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -148,6 +148,11 @@ properties: - const: engicam,px30-core - const: rockchip,px30 =20 + - description: Firefly Core PX30 JD4 + items: + - const: firefly,core-px30-jd4 + - const: rockchip,px30 + - description: Firefly Firefly-RK3288 items: - enum: --=20 2.45.2 From nobody Wed Dec 17 15:38:20 2025 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 940CE19B59C; Tue, 16 Jul 2024 15:51:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721145070; cv=none; b=ubJLJ795KsuWBU+70e2np9b1Qqzi2iaYl8DIn1Jm+kN+qBSaVQ6rmiTfQ02C5GqCqc58iqXfd4uyws14+mucmHvGkhrz3A+iRm1wTEacRm8O2sfzY5mgUpl2y9lx9HFXwkJ1Tejb+rkS6YYEGZzK8lBfHGVuaZdExqV3nij3nkI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721145070; c=relaxed/simple; bh=S07lHM7KbiSnF2U442Jk3eYiedadrdgVwUDyYF3U/mw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=W2amZEDEwwevvd3rSBpZthXAYE89iTLlgOD/xNiRe7T4Yaf4Ex4IIxDDga7Vi9cYOqX4dKltqkY6aHFXteI1hge9p8Vg38J41z/nb6dabQ0yFQIlxBmfuDZjO+pDx75agEPA6OJ6cyIkMX9NLHDNVa/qWbwzFtFQoIZ4Zj271Ig= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=T72nD/p/; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="T72nD/p/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1721145066; bh=S07lHM7KbiSnF2U442Jk3eYiedadrdgVwUDyYF3U/mw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=T72nD/p/VWg9LfOPvX/cMcGUTs5T5bTBKSX+6sHF4riFiKrYJEhs0FgGAIY5IpPmr d8JJjACEk0laiKLcfrrPqUpTSrpPdu0cXYterDdOdR9J99DQWUpyxYb11Fjf7jRbLi KHlXi7jntUlPLQgQOhIWYtA+NYtc21R2+lLBYdhKwQVQQZBQBRXI2niM4gUJB57YJr w+v7ufCz8dgw41ppSpKak8GZHJk7Zf7WegQ2xQ98V8wYZnpMb7JENcSm5CxWa30diC 0vSo7SonU8pGuKcPotzBZvt+7/cxBSeH+C+HaHRED4m4QofzifqPG8g8CISigFjZVv GFDldN6rvP66w== Received: from [127.0.1.1] (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: obbardc) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 3FD3C37821CD; Tue, 16 Jul 2024 15:51:06 +0000 (UTC) From: Christopher Obbard Date: Tue, 16 Jul 2024 16:51:05 +0100 Subject: [PATCH 2/2] arm64: dts: rockchip: add Firefly CORE PX30 JD4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240716-rockchip-px30-firefly-v1-2-60cdad3023a3@collabora.com> References: <20240716-rockchip-px30-firefly-v1-0-60cdad3023a3@collabora.com> In-Reply-To: <20240716-rockchip-px30-firefly-v1-0-60cdad3023a3@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Kever Yang , Christopher Obbard X-Mailer: b4 0.13.0 The Firefly CORE PX30 JD4 board is a SOM and motherboard bundle from Firefly. Add support for it. Signed-off-by: Christopher Obbard --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/px30-firefly-core-px30-jd4.dts | 562 +++++++++++++++++= ++++ 2 files changed, 563 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index f42fa62b4064a..5d19743a1c458 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-engicam-px30-core-ctouch2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-engicam-px30-core-ctouch2-of10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-engicam-px30-core-edimm2.2.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-firefly-core-px30-jd4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-ringneck-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3308-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3308-roc-cc.dtb diff --git a/arch/arm64/boot/dts/rockchip/px30-firefly-core-px30-jd4.dts b/= arch/arm64/boot/dts/rockchip/px30-firefly-core-px30-jd4.dts new file mode 100644 index 0000000000000..1c3235e4de2a2 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-firefly-core-px30-jd4.dts @@ -0,0 +1,562 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include +#include +#include +#include "px30.dtsi" + +/ { + model =3D "Firefly Core PX30 JD4"; + compatible =3D "firefly,core-px30-jd4", "rockchip,px30"; + + aliases { + ethernet0 =3D &gmac; + mmc0 =3D &sdmmc; + mmc1 =3D &sdio; + mmc2 =3D &emmc; + }; + + chosen { + stdout-path =3D "serial2:115200n8"; + }; + + adc-keys { + compatible =3D "adc-keys"; + io-channels =3D <&saradc 2>; + io-channel-names =3D "buttons"; + keyup-threshold-microvolt =3D <1800000>; + poll-interval =3D <100>; + + button-esc { + label =3D "esc"; + linux,code =3D ; + press-threshold-microvolt =3D <1310000>; + }; + + button-home { + label =3D "home"; + linux,code =3D ; + press-threshold-microvolt =3D <624000>; + }; + + button-menu { + label =3D "menu"; + linux,code =3D ; + press-threshold-microvolt =3D <987000>; + }; + + button-down { + label =3D "volume down"; + linux,code =3D ; + press-threshold-microvolt =3D <300000>; + }; + + button-up { + label =3D "volume up"; + linux,code =3D ; + press-threshold-microvolt =3D <17000>; + }; + }; + + backlight: backlight { + compatible =3D "pwm-backlight"; + pwms =3D <&pwm1 0 25000 0>; + power-supply =3D <&vcc3v3_lcd>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible =3D "mmc-pwrseq-emmc"; + pinctrl-0 =3D <&emmc_reset>; + pinctrl-names =3D "default"; + reset-gpios =3D <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios =3D <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ + }; + + vcc5v0_sys: vccsys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; +}; + +&cpu0 { + cpu-supply =3D <&vdd_arm>; +}; + +&cpu1 { + cpu-supply =3D <&vdd_arm>; +}; + +&cpu2 { + cpu-supply =3D <&vdd_arm>; +}; + +&cpu3 { + cpu-supply =3D <&vdd_arm>; +}; + +&display_subsystem { + status =3D "okay"; +}; + +&dsi { + status =3D "okay"; + + ports { + mipi_out: port@1 { + reg =3D <1>; + + mipi_out_panel: endpoint { + remote-endpoint =3D <&mipi_in_panel>; + }; + }; + }; + + panel@0 { + compatible =3D "sitronix,st7703"; + reg =3D <0>; + backlight =3D <&backlight>; + iovcc-supply =3D <&vcc_1v8>; + vci-supply =3D <&vcc3v3_lcd>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mipi_in_panel: endpoint { + remote-endpoint =3D <&mipi_out_panel>; + }; + }; + }; + }; +}; + +&dsi_dphy { + status =3D "okay"; +}; + +&emmc { + bus-width =3D <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + mmc-pwrseq =3D <&emmc_pwrseq>; + vmmc-supply =3D <&vcc_3v0>; + vqmmc-supply =3D <&vccio_flash>; + status =3D "okay"; +}; + +&gmac { + clock_in_out =3D "output"; + phy-supply =3D <&vcc_rmii>; + snps,reset-gpio =3D <&gpio2 13 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us =3D <0 50000 50000>; + status =3D "okay"; +}; + +&gpu { + mali-supply =3D <&vdd_log>; + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; + + rk809: pmic@20 { + compatible =3D "rockchip,rk809"; + reg =3D <0x20>; + interrupt-parent =3D <&gpio0>; + interrupts =3D <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells =3D <0>; + clock-output-names =3D "xin32k"; + + vcc1-supply =3D <&vcc5v0_sys>; + vcc2-supply =3D <&vcc5v0_sys>; + vcc3-supply =3D <&vcc5v0_sys>; + vcc4-supply =3D <&vcc5v0_sys>; + vcc5-supply =3D <&vcc3v3_sys>; + vcc6-supply =3D <&vcc3v3_sys>; + vcc7-supply =3D <&vcc3v3_sys>; + vcc8-supply =3D <&vcc3v3_sys>; + vcc9-supply =3D <&vcc5v0_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name =3D "vdd_log"; + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name =3D "vdd_arm"; + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name =3D "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0: vcc_rmii: DCDC_REG4 { + regulator-name =3D "vcc_3v0"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3000000>; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-name =3D "vcc3v3_sys"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-name =3D "vcc_1v0"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1000000>; + }; + }; + + vcc_1v8: vccio_flash: vccio_sdio: LDO_REG2 { + regulator-name =3D "vcc_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd_1v0: LDO_REG3 { + regulator-name =3D "vdd_1v0"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-name =3D "vcc3v0_pmu"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3000000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name =3D "vccio_sd"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-name =3D "vcc_sd"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-name =3D "vcc2v8_dvp"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-name =3D "vcc1v8_dvp"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcc1v5_dvp: LDO_REG9 { + regulator-name =3D "vcc1v5_dvp"; + regulator-min-microvolt =3D <1500000>; + regulator-max-microvolt =3D <1500000>; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <1500000>; + }; + }; + + vcc3v3_lcd: SWITCH_REG1 { + regulator-name =3D "vcc3v3_lcd"; + regulator-boot-on; + }; + + vcc5v0_host: SWITCH_REG2 { + regulator-name =3D "vcc5v0_host"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&i2s1_2ch { + status =3D "okay"; +}; + +&io_domains { + status =3D "okay"; + + vccio1-supply =3D <&vccio_sdio>; + vccio2-supply =3D <&vccio_sd>; + vccio3-supply =3D <&vcc_3v0>; + vccio4-supply =3D <&vcc3v0_pmu>; + vccio5-supply =3D <&vcc_3v0>; + vccio6-supply =3D <&vccio_flash>; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins =3D + <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + emmc { + emmc_reset: emmc-reset { + rockchip,pins =3D <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins =3D + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins =3D + <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins =3D + <0 RK_PA4 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins =3D + <0 RK_PA4 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins =3D + <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status =3D "okay"; + + pmuio1-supply =3D <&vcc3v0_pmu>; + pmuio2-supply =3D <&vcc3v0_pmu>; +}; + +&pwm1 { + status =3D "okay"; +}; + +&saradc { + vref-supply =3D <&vcc_1v8>; + status =3D "okay"; +}; + +&sdmmc { + bus-width =3D <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay =3D <800>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc_sd>; + vqmmc-supply =3D <&vccio_sd>; + status =3D "okay"; +}; + +&sdio { + bus-width =3D <4>; + cap-sd-highspeed; + keep-power-in-suspend; + non-removable; + mmc-pwrseq =3D <&sdio_pwrseq>; + sd-uhs-sdr104; + status =3D "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode =3D <1>; + rockchip,hw-tshut-polarity =3D <1>; + status =3D "okay"; +}; + +&u2phy { + status =3D "okay"; + + u2phy_host: host-port { + status =3D "okay"; + }; + + u2phy_otg: otg-port { + status =3D "okay"; + }; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1_xfer &uart1_cts>; + status =3D "okay"; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart2m1_xfer>; + status =3D "okay"; +}; + +&uart5 { + status =3D "okay"; +}; + +&usb20_otg { + status =3D "okay"; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; + +&vopb { + status =3D "okay"; +}; + +&vopb_mmu { + status =3D "okay"; +}; + +&vopl { + status =3D "okay"; +}; + +&vopl_mmu { + status =3D "okay"; +}; --=20 2.45.2