From nobody Sun Feb 8 13:48:16 2026 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57C5118C321; Mon, 15 Jul 2024 12:33:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721046795; cv=none; b=g0WPuZlOfBNEm2MdA43Fof9tTL4hpCN18MCjYp61nAd2/4iGaeT1+QZ82+QBhM4twobhULH6zntXF9dxSF29z5N9VO5s0QSyU02xzoRhAjl5AndkJLAFXnTNHqemDjt/7kNYIBJzXGIlyj5o5WGG4RubIw0FazEgK7wunTjbx/c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721046795; c=relaxed/simple; bh=a4Ky3/kCfEXL9iHXaYgdvM8RZtt9d+1v96s6+3khfLY=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=YVhSyHq2QwcLbVLTSTP/OmloK5G3hn9l4OvKWxSQ2Qb5AAqShcORR8nzexxtNPhpjbv9nq2vhTOqpWvjuixD3tYBCz+QGRKdU1vRi4iHpQn45XkJ1as7rHrGxyTRP8j3TuBwNEtg5OX26mh+vJA9OUm/erbez3/9RGZLt4+PDlk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=mPM5MfLb; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="mPM5MfLb" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 46FCX6B5029220; Mon, 15 Jul 2024 07:33:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1721046786; bh=PuxNX++HBVhZzDVby578GFLb+lupl999iKEMK0VNCwg=; h=From:To:CC:Subject:Date; b=mPM5MfLbaicn8GVatXi3jZyt8c6gkqM+4B26ahsgmY/5ptQUa2p7rhYCgZAfieJUe Nlh+KDTfNbDPud5SzNC+qHwr/sreU6AuCckD5aKMHkoG3gxD8BcQyGnM3hXBZ0NaNt eldYYvzhx1plToA4iAgmmpvO14PsYNa9zPSSXems= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 46FCX6Z7075919 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 15 Jul 2024 07:33:06 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 15 Jul 2024 07:33:06 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 15 Jul 2024 07:33:06 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.81]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 46FCX2LX109905; Mon, 15 Jul 2024 07:33:03 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH] arm64: dts: ti: k3-j784s4-main: Enable ACSPCIE output for PCIe1 Date: Mon, 15 Jul 2024 18:03:01 +0530 Message-ID: <20240715123301.1184833-1-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" The PCIe reference clock required by the PCIe Endpoints connected to the PCIe connector corresponding to the PCIe1 instance of PCIe on J784S4-EVM is driven by the ACSPCIE module. Add the device-tree support for enabling the same. Signed-off-by: Siddharth Vadapalli --- Hello, This patch is based on linux-next tagged next-20240715. Patch **depends** on the series at: https://lore.kernel.org/all/20240715120936.1150314-1-s-vadapalli@ti.com/ Patch has been tested on J784S4-EVM with the above series applied. Logs: https://gist.github.com/Siddharth-Vadapalli-at-TI/d825068cfe55bba7a869469c1= ef64ddd Regards, Siddharth. arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index f170f80f00c1..62a6c7de3af6 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -7,6 +7,7 @@ =20 #include #include +#include #include =20 #include "k3-serdes.h" @@ -81,6 +82,11 @@ pcie3_ctrl: pcie3-ctrl@407c { reg =3D <0x407c 0x4>; }; =20 + acspcie0_proxy_ctrl: acspcie0-ctrl@1a090 { + compatible =3D "ti,j784s4-acspcie-proxy-ctrl", "syscon"; + reg =3D <0x1a090 0x4>; + }; + serdes_ln_ctrl: mux-controller@4080 { compatible =3D "reg-mux"; reg =3D <0x00004080 0x30>; @@ -1094,11 +1100,12 @@ pcie1_rc: pcie@2910000 { interrupts =3D ; device_type =3D "pci"; ti,syscon-pcie-ctrl =3D <&pcie1_ctrl 0x0>; + ti,syscon-acspcie-proxy-ctrl =3D <&acspcie0_proxy_ctrl 0x1>; max-link-speed =3D <3>; num-lanes =3D <4>; power-domains =3D <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>; - clocks =3D <&k3_clks 333 0>; - clock-names =3D "fck"; + clocks =3D <&k3_clks 333 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; + clock-names =3D "fck", "pcie_refclk"; #address-cells =3D <3>; #size-cells =3D <2>; bus-range =3D <0x0 0xff>; --=20 2.40.1