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charset="utf-8" From: Lad Prabhakar Simplify the `rzg2l-cpg` driver by removing explicit passing of `clks` and `base` parameters in various clock registration functions. These values are now accessed directly from the `priv` structure. While at it, drop masking of parent clocks with 0xffff as nothing is ever stored in the high bits. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1->v2 - Squashed patches (2,3,4)/4 into single patch - Dropped masking of parent clock with 0xffff - Dropped creating local variable clks --- drivers/clk/renesas/rzg2l-cpg.c | 45 +++++++++++++-------------------- 1 file changed, 17 insertions(+), 28 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index 1fe71a18cf86..d6351140f1ab 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -339,8 +339,7 @@ static const struct clk_ops rzg3s_div_clk_ops =3D { }; =20 static struct clk * __init -rzg3s_cpg_div_clk_register(const struct cpg_core_clk *core, struct clk **c= lks, - void __iomem *base, struct rzg2l_cpg_priv *priv) +rzg3s_cpg_div_clk_register(const struct cpg_core_clk *core, struct rzg2l_c= pg_priv *priv) { struct div_hw_data *div_hw_data; struct clk_init_data init =3D {}; @@ -351,7 +350,7 @@ rzg3s_cpg_div_clk_register(const struct cpg_core_clk *c= ore, struct clk **clks, u32 max =3D 0; int ret; =20 - parent =3D clks[core->parent & 0xffff]; + parent =3D priv->clks[core->parent]; if (IS_ERR(parent)) return ERR_CAST(parent); =20 @@ -400,16 +399,15 @@ rzg3s_cpg_div_clk_register(const struct cpg_core_clk = *core, struct clk **clks, =20 static struct clk * __init rzg2l_cpg_div_clk_register(const struct cpg_core_clk *core, - struct clk **clks, - void __iomem *base, struct rzg2l_cpg_priv *priv) { + void __iomem *base =3D priv->base; struct device *dev =3D priv->dev; const struct clk *parent; const char *parent_name; struct clk_hw *clk_hw; =20 - parent =3D clks[core->parent & 0xffff]; + parent =3D priv->clks[core->parent]; if (IS_ERR(parent)) return ERR_CAST(parent); =20 @@ -440,7 +438,6 @@ rzg2l_cpg_div_clk_register(const struct cpg_core_clk *c= ore, =20 static struct clk * __init rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core, - void __iomem *base, struct rzg2l_cpg_priv *priv) { const struct clk_hw *clk_hw; @@ -448,7 +445,7 @@ rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *c= ore, clk_hw =3D devm_clk_hw_register_mux(priv->dev, core->name, core->parent_names, core->num_parents, core->flag, - base + GET_REG_OFFSET(core->conf), + priv->base + GET_REG_OFFSET(core->conf), GET_SHIFT(core->conf), GET_WIDTH(core->conf), core->mux_flags, &priv->rmw_lock); @@ -508,7 +505,6 @@ static const struct clk_ops rzg2l_cpg_sd_clk_mux_ops = =3D { =20 static struct clk * __init rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core, - void __iomem *base, struct rzg2l_cpg_priv *priv) { struct sd_mux_hw_data *sd_mux_hw_data; @@ -652,7 +648,6 @@ static const struct clk_ops rzg2l_cpg_dsi_div_ops =3D { =20 static struct clk * __init rzg2l_cpg_dsi_div_clk_register(const struct cpg_core_clk *core, - struct clk **clks, struct rzg2l_cpg_priv *priv) { struct dsi_div_hw_data *clk_hw_data; @@ -662,7 +657,7 @@ rzg2l_cpg_dsi_div_clk_register(const struct cpg_core_cl= k *core, struct clk_hw *clk_hw; int ret; =20 - parent =3D clks[core->parent & 0xffff]; + parent =3D priv->clks[core->parent]; if (IS_ERR(parent)) return ERR_CAST(parent); =20 @@ -900,7 +895,6 @@ static const struct clk_ops rzg2l_cpg_sipll5_ops =3D { =20 static struct clk * __init rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core, - struct clk **clks, struct rzg2l_cpg_priv *priv) { const struct clk *parent; @@ -910,7 +904,7 @@ rzg2l_cpg_sipll5_register(const struct cpg_core_clk *co= re, struct clk_hw *clk_hw; int ret; =20 - parent =3D clks[core->parent & 0xffff]; + parent =3D priv->clks[core->parent]; if (IS_ERR(parent)) return ERR_CAST(parent); =20 @@ -1013,8 +1007,6 @@ static const struct clk_ops rzg3s_cpg_pll_ops =3D { =20 static struct clk * __init rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core, - struct clk **clks, - void __iomem *base, struct rzg2l_cpg_priv *priv, const struct clk_ops *ops) { @@ -1025,7 +1017,7 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk = *core, struct pll_clk *pll_clk; int ret; =20 - parent =3D clks[core->parent & 0xffff]; + parent =3D priv->clks[core->parent]; if (IS_ERR(parent)) return ERR_CAST(parent); =20 @@ -1042,7 +1034,7 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk = *core, =20 pll_clk->hw.init =3D &init; pll_clk->conf =3D core->conf; - pll_clk->base =3D base; + pll_clk->base =3D priv->base; pll_clk->priv =3D priv; pll_clk->type =3D core->type; =20 @@ -1140,34 +1132,31 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_c= lk *core, clk =3D clk_hw->clk; break; case CLK_TYPE_SAM_PLL: - clk =3D rzg2l_cpg_pll_clk_register(core, priv->clks, priv->base, priv, - &rzg2l_cpg_pll_ops); + clk =3D rzg2l_cpg_pll_clk_register(core, priv, &rzg2l_cpg_pll_ops); break; case CLK_TYPE_G3S_PLL: - clk =3D rzg2l_cpg_pll_clk_register(core, priv->clks, priv->base, priv, - &rzg3s_cpg_pll_ops); + clk =3D rzg2l_cpg_pll_clk_register(core, priv, &rzg3s_cpg_pll_ops); break; case CLK_TYPE_SIPLL5: - clk =3D rzg2l_cpg_sipll5_register(core, priv->clks, priv); + clk =3D rzg2l_cpg_sipll5_register(core, priv); break; case CLK_TYPE_DIV: - clk =3D rzg2l_cpg_div_clk_register(core, priv->clks, - priv->base, priv); + clk =3D rzg2l_cpg_div_clk_register(core, priv); break; case CLK_TYPE_G3S_DIV: - clk =3D rzg3s_cpg_div_clk_register(core, priv->clks, priv->base, priv); + clk =3D rzg3s_cpg_div_clk_register(core, priv); break; case CLK_TYPE_MUX: - clk =3D rzg2l_cpg_mux_clk_register(core, priv->base, priv); + clk =3D rzg2l_cpg_mux_clk_register(core, priv); break; case CLK_TYPE_SD_MUX: - clk =3D rzg2l_cpg_sd_mux_clk_register(core, priv->base, priv); + clk =3D rzg2l_cpg_sd_mux_clk_register(core, priv); break; case CLK_TYPE_PLL5_4_MUX: clk =3D rzg2l_cpg_pll5_4_mux_clk_register(core, priv); break; case CLK_TYPE_DSI_DIV: - clk =3D rzg2l_cpg_dsi_div_clk_register(core, priv->clks, priv); + clk =3D rzg2l_cpg_dsi_div_clk_register(core, priv); break; default: goto fail; --=20 2.34.1